drivers/rtc/rtc-sun6i.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * An RTC driver for Allwinner A31/A23
   4  *
   5  * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
   6  *
   7  * based on rtc-sunxi.c
   8  *
   9  * An RTC driver for Allwinner A10/A20
  10  *
  11  * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/fs.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/rtc.h>
  29 #include <linux/slab.h>
  30 #include <linux/types.h>
  31
  32 /* Control register */
  33 #define SUN6I_LOSC_CTRL                         0x0000
  34 #define SUN6I_LOSC_CTRL_KEY                     (0x16aa << 16)
  35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS         BIT(15)
  36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC            BIT(9)
  37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC             BIT(8)
  38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC             BIT(7)
  39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN             BIT(4)
  40 #define SUN6I_LOSC_CTRL_EXT_OSC                 BIT(0)
  41 #define SUN6I_LOSC_CTRL_ACC_MASK                GENMASK(9, 7)
  42
  43 #define SUN6I_LOSC_CLK_PRESCAL                  0x0008
  44
  45 /* RTC */
  46 #define SUN6I_RTC_YMD                           0x0010
  47 #define SUN6I_RTC_HMS                           0x0014
  48
  49 /* Alarm 0 (counter) */
  50 #define SUN6I_ALRM_COUNTER                      0x0020
  51 #define SUN6I_ALRM_CUR_VAL                      0x0024
  52 #define SUN6I_ALRM_EN                           0x0028
  53 #define SUN6I_ALRM_EN_CNT_EN                    BIT(0)
  54 #define SUN6I_ALRM_IRQ_EN                       0x002c
  55 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN            BIT(0)
  56 #define SUN6I_ALRM_IRQ_STA                      0x0030
  57 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND         BIT(0)
  58
  59 /* Alarm 1 (wall clock) */
  60 #define SUN6I_ALRM1_EN                          0x0044
  61 #define SUN6I_ALRM1_IRQ_EN                      0x0048
  62 #define SUN6I_ALRM1_IRQ_STA                     0x004c
  63 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND       BIT(0)
  64
  65 /* Alarm config */
  66 #define SUN6I_ALARM_CONFIG                      0x0050
  67 #define SUN6I_ALARM_CONFIG_WAKEUP               BIT(0)
  68
  69 #define SUN6I_LOSC_OUT_GATING                   0x0060
  70 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET         0
  71
  72 /*
  73  * Get date values
  74  */
  75 #define SUN6I_DATE_GET_DAY_VALUE(x)             ((x)  & 0x0000001f)
  76 #define SUN6I_DATE_GET_MON_VALUE(x)             (((x) & 0x00000f00) >> 8)
  77 #define SUN6I_DATE_GET_YEAR_VALUE(x)            (((x) & 0x003f0000) >> 16)
  78 #define SUN6I_LEAP_GET_VALUE(x)                 (((x) & 0x00400000) >> 22)
  79
  80 /*
  81  * Get time values
  82  */
  83 #define SUN6I_TIME_GET_SEC_VALUE(x)             ((x)  & 0x0000003f)
  84 #define SUN6I_TIME_GET_MIN_VALUE(x)             (((x) & 0x00003f00) >> 8)
  85 #define SUN6I_TIME_GET_HOUR_VALUE(x)            (((x) & 0x001f0000) >> 16)
  86
  87 /*
  88  * Set date values
  89  */
  90 #define SUN6I_DATE_SET_DAY_VALUE(x)             ((x)       & 0x0000001f)
  91 #define SUN6I_DATE_SET_MON_VALUE(x)             ((x) <<  8 & 0x00000f00)
  92 #define SUN6I_DATE_SET_YEAR_VALUE(x)            ((x) << 16 & 0x003f0000)
  93 #define SUN6I_LEAP_SET_VALUE(x)                 ((x) << 22 & 0x00400000)
  94
  95 /*
  96  * Set time values
  97  */
  98 #define SUN6I_TIME_SET_SEC_VALUE(x)             ((x)       & 0x0000003f)
  99 #define SUN6I_TIME_SET_MIN_VALUE(x)             ((x) <<  8 & 0x00003f00)
 100 #define SUN6I_TIME_SET_HOUR_VALUE(x)            ((x) << 16 & 0x001f0000)
 101
 102 /*
 103  * The year parameter passed to the driver is usually an offset relative to
 104  * the year 1900. This macro is used to convert this offset to another one
 105  * relative to the minimum year allowed by the hardware.
 106  *
 107  * The year range is 1970 - 2033. This range is selected to match Allwinner's
 108  * driver, even though it is somewhat limited.
 109  */
 110 #define SUN6I_YEAR_MIN                          1970
 111 #define SUN6I_YEAR_MAX                          2033
 112 #define SUN6I_YEAR_OFF                          (SUN6I_YEAR_MIN - 1900)
 113
 114 /*
 115  * There are other differences between models, including:
 116  *
 117  *   - number of GPIO pins that can be configured to hold a certain level
 118  *   - crypto-key related registers (H5, H6)
 119  *   - boot process related (super standby, secondary processor entry address)
 120  *     registers (R40, H6)
 121  *   - SYS power domain controls (R40)
 122  *   - DCXO controls (H6)
 123  *   - RC oscillator calibration (H6)
 124  *
 125  * These functions are not covered by this driver.
 126  */
 127 struct sun6i_rtc_clk_data {
 128         unsigned long rc_osc_rate;
 129         unsigned int fixed_prescaler : 16;
 130         unsigned int has_prescaler : 1;
 131         unsigned int has_out_clk : 1;
 132         unsigned int export_iosc : 1;
 133         unsigned int has_losc_en : 1;
 134         unsigned int has_auto_swt : 1;
 135 };
 136
 137 struct sun6i_rtc_dev {
 138         struct rtc_device *rtc;
 139         const struct sun6i_rtc_clk_data *data;
 140         void __iomem *base;
 141         int irq;
 142         unsigned long alarm;
 143
 144         struct clk_hw hw;
 145         struct clk_hw *int_osc;
 146         struct clk *losc;
 147         struct clk *ext_losc;
 148
 149         spinlock_t lock;
 150 };
 151
 152 static struct sun6i_rtc_dev *sun6i_rtc;
 153
 154 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
 155                                                unsigned long parent_rate)
 156 {
 157         struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
 158         u32 val = 0;
 159
 160         val = readl(rtc->base + SUN6I_LOSC_CTRL);
 161         if (val & SUN6I_LOSC_CTRL_EXT_OSC)
 162                 return parent_rate;
 163
 164         if (rtc->data->fixed_prescaler)
 165                 parent_rate /= rtc->data->fixed_prescaler;
 166
 167         if (rtc->data->has_prescaler) {
 168                 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
 169                 val &= GENMASK(4, 0);
 170         }
 171
 172         return parent_rate / (val + 1);
 173 }
 174
 175 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
 176 {
 177         struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
 178
 179         return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
 180 }
 181
 182 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
 183 {
 184         struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
 185         unsigned long flags;
 186         u32 val;
 187
 188         if (index > 1)
 189                 return -EINVAL;
 190
 191         spin_lock_irqsave(&rtc->lock, flags);
 192         val = readl(rtc->base + SUN6I_LOSC_CTRL);
 193         val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
 194         val |= SUN6I_LOSC_CTRL_KEY;
 195         val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
 196         if (rtc->data->has_losc_en) {
 197                 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
 198                 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
 199         }
 200         writel(val, rtc->base + SUN6I_LOSC_CTRL);
 201         spin_unlock_irqrestore(&rtc->lock, flags);
 202
 203         return 0;
 204 }
 205
 206 static const struct clk_ops sun6i_rtc_osc_ops = {
 207         .recalc_rate    = sun6i_rtc_osc_recalc_rate,
 208
 209         .get_parent     = sun6i_rtc_osc_get_parent,
 210         .set_parent     = sun6i_rtc_osc_set_parent,
 211 };
 212
 213 static void __init sun6i_rtc_clk_init(struct device_node *node,
 214                                       const struct sun6i_rtc_clk_data *data)
 215 {
 216         struct clk_hw_onecell_data *clk_data;
 217         struct sun6i_rtc_dev *rtc;
 218         struct clk_init_data init = {
 219                 .ops            = &sun6i_rtc_osc_ops,
 220                 .name           = "losc",
 221         };
 222         const char *iosc_name = "rtc-int-osc";
 223         const char *clkout_name = "osc32k-out";
 224         const char *parents[2];
 225         u32 reg;
 226
 227         rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
 228         if (!rtc)
 229                 return;
 230
 231         rtc->data = data;
 232         clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
 233         if (!clk_data) {
 234                 kfree(rtc);
 235                 return;
 236         }
 237
 238         spin_lock_init(&rtc->lock);
 239
 240         rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
 241         if (IS_ERR(rtc->base)) {
 242                 pr_crit("Can't map RTC registers");
 243                 goto err;
 244         }
 245
 246         reg = SUN6I_LOSC_CTRL_KEY;
 247         if (rtc->data->has_auto_swt) {
 248                 /* Bypass auto-switch to int osc, on ext losc failure */
 249                 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
 250                 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
 251         }
 252
 253         /* Switch to the external, more precise, oscillator */
 254         reg |= SUN6I_LOSC_CTRL_EXT_OSC;
 255         if (rtc->data->has_losc_en)
 256                 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
 257         writel(reg, rtc->base + SUN6I_LOSC_CTRL);
 258
 259         /* Yes, I know, this is ugly. */
 260         sun6i_rtc = rtc;
 261
 262         /* Deal with old DTs */
 263         if (!of_get_property(node, "clocks", NULL))
 264                 goto err;
 265
 266         /* Only read IOSC name from device tree if it is exported */
 267         if (rtc->data->export_iosc)
 268                 of_property_read_string_index(node, "clock-output-names", 2,
 269                                               &iosc_name);
 270
 271         rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
 272                                                                 iosc_name,
 273                                                                 NULL, 0,
 274                                                                 rtc->data->rc_osc_rate,
 275                                                                 300000000);
 276         if (IS_ERR(rtc->int_osc)) {
 277                 pr_crit("Couldn't register the internal oscillator\n");
 278                 return;
 279         }
 280
 281         parents[0] = clk_hw_get_name(rtc->int_osc);
 282         parents[1] = of_clk_get_parent_name(node, 0);
 283
 284         rtc->hw.init = &init;
 285
 286         init.parent_names = parents;
 287         init.num_parents = of_clk_get_parent_count(node) + 1;
 288         of_property_read_string_index(node, "clock-output-names", 0,
 289                                       &init.name);
 290
 291         rtc->losc = clk_register(NULL, &rtc->hw);
 292         if (IS_ERR(rtc->losc)) {
 293                 pr_crit("Couldn't register the LOSC clock\n");
 294                 return;
 295         }
 296
 297         of_property_read_string_index(node, "clock-output-names", 1,
 298                                       &clkout_name);
 299         rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
 300                                           0, rtc->base + SUN6I_LOSC_OUT_GATING,
 301                                           SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
 302                                           &rtc->lock);
 303         if (IS_ERR(rtc->ext_losc)) {
 304                 pr_crit("Couldn't register the LOSC external gate\n");
 305                 return;
 306         }
 307
 308         clk_data->num = 2;
 309         clk_data->hws[0] = &rtc->hw;
 310         clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
 311         if (rtc->data->export_iosc) {
 312                 clk_data->hws[2] = rtc->int_osc;
 313                 clk_data->num = 3;
 314         }
 315         of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 316         return;
 317
 318 err:
 319         kfree(clk_data);
 320 }
 321
 322 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
 323         .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
 324         .has_prescaler = 1,
 325 };
 326
 327 static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
 328 {
 329         sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
 330 }
 331 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
 332                       sun6i_a31_rtc_clk_init);
 333
 334 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
 335         .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
 336         .has_prescaler = 1,
 337         .has_out_clk = 1,
 338 };
 339
 340 static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
 341 {
 342         sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
 343 }
 344 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
 345                       sun8i_a23_rtc_clk_init);
 346
 347 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
 348         .rc_osc_rate = 16000000,
 349         .fixed_prescaler = 32,
 350         .has_prescaler = 1,
 351         .has_out_clk = 1,
 352         .export_iosc = 1,
 353 };
 354
 355 static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
 356 {
 357         sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
 358 }
 359 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
 360                       sun8i_h3_rtc_clk_init);
 361 /* As far as we are concerned, clocks for H5 are the same as H3 */
 362 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
 363                       sun8i_h3_rtc_clk_init);
 364
 365 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
 366         .rc_osc_rate = 16000000,
 367         .fixed_prescaler = 32,
 368         .has_prescaler = 1,
 369         .has_out_clk = 1,
 370         .export_iosc = 1,
 371         .has_losc_en = 1,
 372         .has_auto_swt = 1,
 373 };
 374
 375 static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
 376 {
 377         sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
 378 }
 379 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
 380                       sun50i_h6_rtc_clk_init);
 381
 382 /*
 383  * The R40 user manual is self-conflicting on whether the prescaler is
 384  * fixed or configurable. The clock diagram shows it as fixed, but there
 385  * is also a configurable divider in the RTC block.
 386  */
 387 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
 388         .rc_osc_rate = 16000000,
 389         .fixed_prescaler = 512,
 390 };
 391 static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
 392 {
 393         sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
 394 }
 395 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
 396                       sun8i_r40_rtc_clk_init);
 397
 398 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
 399         .rc_osc_rate = 32000,
 400         .has_out_clk = 1,
 401 };
 402
 403 static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
 404 {
 405         sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
 406 }
 407 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
 408                       sun8i_v3_rtc_clk_init);
 409
 410 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
 411 {
 412         struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
 413         irqreturn_t ret = IRQ_NONE;
 414         u32 val;
 415
 416         spin_lock(&chip->lock);
 417         val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
 418
 419         if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
 420                 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
 421                 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
 422
 423                 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
 424
 425                 ret = IRQ_HANDLED;
 426         }
 427         spin_unlock(&chip->lock);
 428
 429         return ret;
 430 }
 431
 432 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
 433 {
 434         u32 alrm_val = 0;
 435         u32 alrm_irq_val = 0;
 436         u32 alrm_wake_val = 0;
 437         unsigned long flags;
 438
 439         if (to) {
 440                 alrm_val = SUN6I_ALRM_EN_CNT_EN;
 441                 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
 442                 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
 443         } else {
 444                 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
 445                        chip->base + SUN6I_ALRM_IRQ_STA);
 446         }
 447
 448         spin_lock_irqsave(&chip->lock, flags);
 449         writel(alrm_val, chip->base + SUN6I_ALRM_EN);
 450         writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
 451         writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
 452         spin_unlock_irqrestore(&chip->lock, flags);
 453 }
 454
 455 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
 456 {
 457         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 458         u32 date, time;
 459
 460         /*
 461          * read again in case it changes
 462          */
 463         do {
 464                 date = readl(chip->base + SUN6I_RTC_YMD);
 465                 time = readl(chip->base + SUN6I_RTC_HMS);
 466         } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
 467                  (time != readl(chip->base + SUN6I_RTC_HMS)));
 468
 469         rtc_tm->tm_sec  = SUN6I_TIME_GET_SEC_VALUE(time);
 470         rtc_tm->tm_min  = SUN6I_TIME_GET_MIN_VALUE(time);
 471         rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
 472
 473         rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
 474         rtc_tm->tm_mon  = SUN6I_DATE_GET_MON_VALUE(date);
 475         rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
 476
 477         rtc_tm->tm_mon  -= 1;
 478
 479         /*
 480          * switch from (data_year->min)-relative offset to
 481          * a (1900)-relative one
 482          */
 483         rtc_tm->tm_year += SUN6I_YEAR_OFF;
 484
 485         return 0;
 486 }
 487
 488 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 489 {
 490         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 491         unsigned long flags;
 492         u32 alrm_st;
 493         u32 alrm_en;
 494
 495         spin_lock_irqsave(&chip->lock, flags);
 496         alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
 497         alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
 498         spin_unlock_irqrestore(&chip->lock, flags);
 499
 500         wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
 501         wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
 502         rtc_time_to_tm(chip->alarm, &wkalrm->time);
 503
 504         return 0;
 505 }
 506
 507 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 508 {
 509         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 510         struct rtc_time *alrm_tm = &wkalrm->time;
 511         struct rtc_time tm_now;
 512         unsigned long time_now = 0;
 513         unsigned long time_set = 0;
 514         unsigned long time_gap = 0;
 515         int ret = 0;
 516
 517         ret = sun6i_rtc_gettime(dev, &tm_now);
 518         if (ret < 0) {
 519                 dev_err(dev, "Error in getting time\n");
 520                 return -EINVAL;
 521         }
 522
 523         rtc_tm_to_time(alrm_tm, &time_set);
 524         rtc_tm_to_time(&tm_now, &time_now);
 525         if (time_set <= time_now) {
 526                 dev_err(dev, "Date to set in the past\n");
 527                 return -EINVAL;
 528         }
 529
 530         time_gap = time_set - time_now;
 531
 532         if (time_gap > U32_MAX) {
 533                 dev_err(dev, "Date too far in the future\n");
 534                 return -EINVAL;
 535         }
 536
 537         sun6i_rtc_setaie(0, chip);
 538         writel(0, chip->base + SUN6I_ALRM_COUNTER);
 539         usleep_range(100, 300);
 540
 541         writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
 542         chip->alarm = time_set;
 543
 544         sun6i_rtc_setaie(wkalrm->enabled, chip);
 545
 546         return 0;
 547 }
 548
 549 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
 550                           unsigned int mask, unsigned int ms_timeout)
 551 {
 552         const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
 553         u32 reg;
 554
 555         do {
 556                 reg = readl(chip->base + offset);
 557                 reg &= mask;
 558
 559                 if (!reg)
 560                         return 0;
 561
 562         } while (time_before(jiffies, timeout));
 563
 564         return -ETIMEDOUT;
 565 }
 566
 567 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
 568 {
 569         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 570         u32 date = 0;
 571         u32 time = 0;
 572         int year;
 573
 574         year = rtc_tm->tm_year + 1900;
 575         if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
 576                 dev_err(dev, "rtc only supports year in range %d - %d\n",
 577                         SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
 578                 return -EINVAL;
 579         }
 580
 581         rtc_tm->tm_year -= SUN6I_YEAR_OFF;
 582         rtc_tm->tm_mon += 1;
 583
 584         date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
 585                 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
 586                 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
 587
 588         if (is_leap_year(year))
 589                 date |= SUN6I_LEAP_SET_VALUE(1);
 590
 591         time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
 592                 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min)  |
 593                 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
 594
 595         /* Check whether registers are writable */
 596         if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
 597                            SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
 598                 dev_err(dev, "rtc is still busy.\n");
 599                 return -EBUSY;
 600         }
 601
 602         writel(time, chip->base + SUN6I_RTC_HMS);
 603
 604         /*
 605          * After writing the RTC HH-MM-SS register, the
 606          * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
 607          * be cleared until the real writing operation is finished
 608          */
 609
 610         if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
 611                            SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
 612                 dev_err(dev, "Failed to set rtc time.\n");
 613                 return -ETIMEDOUT;
 614         }
 615
 616         writel(date, chip->base + SUN6I_RTC_YMD);
 617
 618         /*
 619          * After writing the RTC YY-MM-DD register, the
 620          * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
 621          * be cleared until the real writing operation is finished
 622          */
 623
 624         if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
 625                            SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
 626                 dev_err(dev, "Failed to set rtc time.\n");
 627                 return -ETIMEDOUT;
 628         }
 629
 630         return 0;
 631 }
 632
 633 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 634 {
 635         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 636
 637         if (!enabled)
 638                 sun6i_rtc_setaie(enabled, chip);
 639
 640         return 0;
 641 }
 642
 643 static const struct rtc_class_ops sun6i_rtc_ops = {
 644         .read_time              = sun6i_rtc_gettime,
 645         .set_time               = sun6i_rtc_settime,
 646         .read_alarm             = sun6i_rtc_getalarm,
 647         .set_alarm              = sun6i_rtc_setalarm,
 648         .alarm_irq_enable       = sun6i_rtc_alarm_irq_enable
 649 };
 650
 651 #ifdef CONFIG_PM_SLEEP
 652 /* Enable IRQ wake on suspend, to wake up from RTC. */
 653 static int sun6i_rtc_suspend(struct device *dev)
 654 {
 655         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 656
 657         if (device_may_wakeup(dev))
 658                 enable_irq_wake(chip->irq);
 659
 660         return 0;
 661 }
 662
 663 /* Disable IRQ wake on resume. */
 664 static int sun6i_rtc_resume(struct device *dev)
 665 {
 666         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 667
 668         if (device_may_wakeup(dev))
 669                 disable_irq_wake(chip->irq);
 670
 671         return 0;
 672 }
 673 #endif
 674
 675 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
 676         sun6i_rtc_suspend, sun6i_rtc_resume);
 677
 678 static int sun6i_rtc_probe(struct platform_device *pdev)
 679 {
 680         struct sun6i_rtc_dev *chip = sun6i_rtc;
 681         int ret;
 682
 683         if (!chip)
 684                 return -ENODEV;
 685
 686         platform_set_drvdata(pdev, chip);
 687
 688         chip->irq = platform_get_irq(pdev, 0);
 689         if (chip->irq < 0)
 690                 return chip->irq;
 691
 692         ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
 693                                0, dev_name(&pdev->dev), chip);
 694         if (ret) {
 695                 dev_err(&pdev->dev, "Could not request IRQ\n");
 696                 return ret;
 697         }
 698
 699         /* clear the alarm counter value */
 700         writel(0, chip->base + SUN6I_ALRM_COUNTER);
 701
 702         /* disable counter alarm */
 703         writel(0, chip->base + SUN6I_ALRM_EN);
 704
 705         /* disable counter alarm interrupt */
 706         writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
 707
 708         /* disable week alarm */
 709         writel(0, chip->base + SUN6I_ALRM1_EN);
 710
 711         /* disable week alarm interrupt */
 712         writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
 713
 714         /* clear counter alarm pending interrupts */
 715         writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
 716                chip->base + SUN6I_ALRM_IRQ_STA);
 717
 718         /* clear week alarm pending interrupts */
 719         writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
 720                chip->base + SUN6I_ALRM1_IRQ_STA);
 721
 722         /* disable alarm wakeup */
 723         writel(0, chip->base + SUN6I_ALARM_CONFIG);
 724
 725         clk_prepare_enable(chip->losc);
 726
 727         device_init_wakeup(&pdev->dev, 1);
 728
 729         chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i",
 730                                              &sun6i_rtc_ops, THIS_MODULE);
 731         if (IS_ERR(chip->rtc)) {
 732                 dev_err(&pdev->dev, "unable to register device\n");
 733                 return PTR_ERR(chip->rtc);
 734         }
 735
 736         dev_info(&pdev->dev, "RTC enabled\n");
 737
 738         return 0;
 739 }
 740
 741 /*
 742  * As far as RTC functionality goes, all models are the same. The
 743  * datasheets claim that different models have different number of
 744  * registers available for non-volatile storage, but experiments show
 745  * that all SoCs have 16 registers available for this purpose.
 746  */
 747 static const struct of_device_id sun6i_rtc_dt_ids[] = {
 748         { .compatible = "allwinner,sun6i-a31-rtc" },
 749         { .compatible = "allwinner,sun8i-a23-rtc" },
 750         { .compatible = "allwinner,sun8i-h3-rtc" },
 751         { .compatible = "allwinner,sun8i-r40-rtc" },
 752         { .compatible = "allwinner,sun8i-v3-rtc" },
 753         { .compatible = "allwinner,sun50i-h5-rtc" },
 754         { .compatible = "allwinner,sun50i-h6-rtc" },
 755         { /* sentinel */ },
 756 };
 757 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
 758
 759 static struct platform_driver sun6i_rtc_driver = {
 760         .probe          = sun6i_rtc_probe,
 761         .driver         = {
 762                 .name           = "sun6i-rtc",
 763                 .of_match_table = sun6i_rtc_dt_ids,
 764                 .pm = &sun6i_rtc_pm_ops,
 765         },
 766 };
 767 builtin_platform_driver(sun6i_rtc_driver);