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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / scsi / pm8001 / pm80xx_hwi.c
blob98dcdbd146d5049786c0ed4766f923741f29a5ce
1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46 #define SMP_DIRECT 1
47 #define SMP_INDIRECT 2
48
49
50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
51 {
52 u32 reg_val;
53 unsigned long start;
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55 /* confirm the setting is written */
56 start = jiffies + HZ; /* 1 sec */
57 do {
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 PM8001_FAIL_DBG(pm8001_ha,
62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
63 " = 0x%x\n", reg_val));
64 return -1;
65 }
66 return 0;
67 }
68
69 void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 const void *destination,
71 u32 dw_count, u32 bus_base_number)
72 {
73 u32 index, value, offset;
74 u32 *destination1;
75 destination1 = (u32 *)destination;
76
77 for (index = 0; index < dw_count; index += 4, destination1++) {
78 offset = (soffset + index);
79 if (offset < (64 * 1024)) {
80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
81 *destination1 = cpu_to_le32(value);
82 }
83 }
84 return;
85 }
86
87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
88 struct device_attribute *attr, char *buf)
89 {
90 struct Scsi_Host *shost = class_to_shost(cdev);
91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
94 u32 accum_len , reg_val, index, *temp;
95 u32 status = 1;
96 unsigned long start;
97 u8 *direct_data;
98 char *fatal_error_data = buf;
99 u32 length_to_read;
100 u32 offset;
101
102 pm8001_ha->forensic_info.data_buf.direct_data = buf;
103 if (pm8001_ha->chip_id == chip_8001) {
104 pm8001_ha->forensic_info.data_buf.direct_data +=
105 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
106 "Not supported for SPC controller");
107 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
108 (char *)buf;
109 }
110 /* initialize variables for very first call from host application */
111 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
112 PM8001_IO_DBG(pm8001_ha,
113 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
114 direct_data = (u8 *)fatal_error_data;
115 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
116 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
117 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
118 pm8001_ha->forensic_info.data_buf.read_len = 0;
119 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
120
121 /* Write signature to fatal dump table */
122 pm8001_mw32(fatal_table_address,
123 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
124
125 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
126 PM8001_IO_DBG(pm8001_ha,
127 pm8001_printk("ossaHwCB: status1 %d\n", status));
128 PM8001_IO_DBG(pm8001_ha,
129 pm8001_printk("ossaHwCB: read_len 0x%x\n",
130 pm8001_ha->forensic_info.data_buf.read_len));
131 PM8001_IO_DBG(pm8001_ha,
132 pm8001_printk("ossaHwCB: direct_len 0x%x\n",
133 pm8001_ha->forensic_info.data_buf.direct_len));
134 PM8001_IO_DBG(pm8001_ha,
135 pm8001_printk("ossaHwCB: direct_offset 0x%x\n",
136 pm8001_ha->forensic_info.data_buf.direct_offset));
137 }
138 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
139 /* start to get data */
140 /* Program the MEMBASE II Shifting Register with 0x00.*/
141 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
142 pm8001_ha->fatal_forensic_shift_offset);
143 pm8001_ha->forensic_last_offset = 0;
144 pm8001_ha->forensic_fatal_step = 0;
145 pm8001_ha->fatal_bar_loc = 0;
146 }
147
148 /* Read until accum_len is retrived */
149 accum_len = pm8001_mr32(fatal_table_address,
150 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
151 /* Determine length of data between previously stored transfer length
152 * and current accumulated transfer length
153 */
154 length_to_read =
155 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
156 PM8001_IO_DBG(pm8001_ha,
157 pm8001_printk("get_fatal_spcv: accum_len 0x%x\n", accum_len));
158 PM8001_IO_DBG(pm8001_ha,
159 pm8001_printk("get_fatal_spcv: length_to_read 0x%x\n",
160 length_to_read));
161 PM8001_IO_DBG(pm8001_ha,
162 pm8001_printk("get_fatal_spcv: last_offset 0x%x\n",
163 pm8001_ha->forensic_last_offset));
164 PM8001_IO_DBG(pm8001_ha,
165 pm8001_printk("get_fatal_spcv: read_len 0x%x\n",
166 pm8001_ha->forensic_info.data_buf.read_len));
167 PM8001_IO_DBG(pm8001_ha,
168 pm8001_printk("get_fatal_spcv:: direct_len 0x%x\n",
169 pm8001_ha->forensic_info.data_buf.direct_len));
170 PM8001_IO_DBG(pm8001_ha,
171 pm8001_printk("get_fatal_spcv:: direct_offset 0x%x\n",
172 pm8001_ha->forensic_info.data_buf.direct_offset));
173
174 /* If accumulated length failed to read correctly fail the attempt.*/
175 if (accum_len == 0xFFFFFFFF) {
176 PM8001_IO_DBG(pm8001_ha,
177 pm8001_printk("Possible PCI issue 0x%x not expected\n",
178 accum_len));
179 return status;
180 }
181 /* If accumulated length is zero fail the attempt */
182 if (accum_len == 0) {
183 pm8001_ha->forensic_info.data_buf.direct_data +=
184 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
185 "%08x ", 0xFFFFFFFF);
186 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
187 (char *)buf;
188 }
189 /* Accumulated length is good so start capturing the first data */
190 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
191 if (pm8001_ha->forensic_fatal_step == 0) {
192 moreData:
193 /* If data to read is less than SYSFS_OFFSET then reduce the
194 * length of dataLen
195 */
196 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
197 > length_to_read) {
198 pm8001_ha->forensic_info.data_buf.direct_len =
199 length_to_read -
200 pm8001_ha->forensic_last_offset;
201 } else {
202 pm8001_ha->forensic_info.data_buf.direct_len =
203 SYSFS_OFFSET;
204 }
205 if (pm8001_ha->forensic_info.data_buf.direct_data) {
206 /* Data is in bar, copy to host memory */
207 pm80xx_pci_mem_copy(pm8001_ha,
208 pm8001_ha->fatal_bar_loc,
209 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
210 pm8001_ha->forensic_info.data_buf.direct_len, 1);
211 }
212 pm8001_ha->fatal_bar_loc +=
213 pm8001_ha->forensic_info.data_buf.direct_len;
214 pm8001_ha->forensic_info.data_buf.direct_offset +=
215 pm8001_ha->forensic_info.data_buf.direct_len;
216 pm8001_ha->forensic_last_offset +=
217 pm8001_ha->forensic_info.data_buf.direct_len;
218 pm8001_ha->forensic_info.data_buf.read_len =
219 pm8001_ha->forensic_info.data_buf.direct_len;
220
221 if (pm8001_ha->forensic_last_offset >= length_to_read) {
222 pm8001_ha->forensic_info.data_buf.direct_data +=
223 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
224 "%08x ", 3);
225 for (index = 0; index <
226 (pm8001_ha->forensic_info.data_buf.direct_len
227 / 4); index++) {
228 pm8001_ha->forensic_info.data_buf.direct_data +=
229 sprintf(
230 pm8001_ha->forensic_info.data_buf.direct_data,
231 "%08x ", *(temp + index));
232 }
233
234 pm8001_ha->fatal_bar_loc = 0;
235 pm8001_ha->forensic_fatal_step = 1;
236 pm8001_ha->fatal_forensic_shift_offset = 0;
237 pm8001_ha->forensic_last_offset = 0;
238 status = 0;
239 offset = (int)
240 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
241 - (char *)buf);
242 PM8001_IO_DBG(pm8001_ha,
243 pm8001_printk("get_fatal_spcv:return1 0x%x\n", offset));
244 return (char *)pm8001_ha->
245 forensic_info.data_buf.direct_data -
246 (char *)buf;
247 }
248 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
249 pm8001_ha->forensic_info.data_buf.direct_data +=
250 sprintf(pm8001_ha->
251 forensic_info.data_buf.direct_data,
252 "%08x ", 2);
253 for (index = 0; index <
254 (pm8001_ha->forensic_info.data_buf.direct_len
255 / 4); index++) {
256 pm8001_ha->forensic_info.data_buf.direct_data
257 += sprintf(pm8001_ha->
258 forensic_info.data_buf.direct_data,
259 "%08x ", *(temp + index));
260 }
261 status = 0;
262 offset = (int)
263 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
264 - (char *)buf);
265 PM8001_IO_DBG(pm8001_ha,
266 pm8001_printk("get_fatal_spcv:return2 0x%x\n", offset));
267 return (char *)pm8001_ha->
268 forensic_info.data_buf.direct_data -
269 (char *)buf;
270 }
271
272 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
273 pm8001_ha->forensic_info.data_buf.direct_data +=
274 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
275 "%08x ", 2);
276 for (index = 0; index <
277 (pm8001_ha->forensic_info.data_buf.direct_len
278 / 4) ; index++) {
279 pm8001_ha->forensic_info.data_buf.direct_data +=
280 sprintf(pm8001_ha->
281 forensic_info.data_buf.direct_data,
282 "%08x ", *(temp + index));
283 }
284 pm8001_ha->fatal_forensic_shift_offset += 0x100;
285 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
286 pm8001_ha->fatal_forensic_shift_offset);
287 pm8001_ha->fatal_bar_loc = 0;
288 status = 0;
289 offset = (int)
290 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
291 - (char *)buf);
292 PM8001_IO_DBG(pm8001_ha,
293 pm8001_printk("get_fatal_spcv: return3 0x%x\n", offset));
294 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
295 (char *)buf;
296 }
297 if (pm8001_ha->forensic_fatal_step == 1) {
298 /* store previous accumulated length before triggering next
299 * accumulated length update
300 */
301 pm8001_ha->forensic_preserved_accumulated_transfer =
302 pm8001_mr32(fatal_table_address,
303 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
304
305 /* continue capturing the fatal log until Dump status is 0x3 */
306 if (pm8001_mr32(fatal_table_address,
307 MPI_FATAL_EDUMP_TABLE_STATUS) <
308 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
309
310 /* reset fddstat bit by writing to zero*/
311 pm8001_mw32(fatal_table_address,
312 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
313
314 /* set dump control value to '1' so that new data will
315 * be transferred to shared memory
316 */
317 pm8001_mw32(fatal_table_address,
318 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
319 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
320
321 /*Poll FDDHSHK until clear */
322 start = jiffies + (2 * HZ); /* 2 sec */
323
324 do {
325 reg_val = pm8001_mr32(fatal_table_address,
326 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
327 } while ((reg_val) && time_before(jiffies, start));
328
329 if (reg_val != 0) {
330 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
331 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
332 reg_val));
333 /* Fail the dump if a timeout occurs */
334 pm8001_ha->forensic_info.data_buf.direct_data +=
335 sprintf(
336 pm8001_ha->forensic_info.data_buf.direct_data,
337 "%08x ", 0xFFFFFFFF);
338 return((char *)
339 pm8001_ha->forensic_info.data_buf.direct_data
340 - (char *)buf);
341 }
342 /* Poll status register until set to 2 or
343 * 3 for up to 2 seconds
344 */
345 start = jiffies + (2 * HZ); /* 2 sec */
346
347 do {
348 reg_val = pm8001_mr32(fatal_table_address,
349 MPI_FATAL_EDUMP_TABLE_STATUS);
350 } while (((reg_val != 2) && (reg_val != 3)) &&
351 time_before(jiffies, start));
352
353 if (reg_val < 2) {
354 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
355 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
356 reg_val));
357 /* Fail the dump if a timeout occurs */
358 pm8001_ha->forensic_info.data_buf.direct_data +=
359 sprintf(
360 pm8001_ha->forensic_info.data_buf.direct_data,
361 "%08x ", 0xFFFFFFFF);
362 pm8001_cw32(pm8001_ha, 0,
363 MEMBASE_II_SHIFT_REGISTER,
364 pm8001_ha->fatal_forensic_shift_offset);
365 }
366 /* Read the next block of the debug data.*/
367 length_to_read = pm8001_mr32(fatal_table_address,
368 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
369 pm8001_ha->forensic_preserved_accumulated_transfer;
370 if (length_to_read != 0x0) {
371 pm8001_ha->forensic_fatal_step = 0;
372 goto moreData;
373 } else {
374 pm8001_ha->forensic_info.data_buf.direct_data +=
375 sprintf(
376 pm8001_ha->forensic_info.data_buf.direct_data,
377 "%08x ", 4);
378 pm8001_ha->forensic_info.data_buf.read_len
379 = 0xFFFFFFFF;
380 pm8001_ha->forensic_info.data_buf.direct_len
381 = 0;
382 pm8001_ha->forensic_info.data_buf.direct_offset
383 = 0;
384 pm8001_ha->forensic_info.data_buf.read_len = 0;
385 }
386 }
387 }
388 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
389 - (char *)buf);
390 PM8001_IO_DBG(pm8001_ha,
391 pm8001_printk("get_fatal_spcv: return4 0x%x\n", offset));
392 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
393 (char *)buf;
394 }
395
396 /**
397 * read_main_config_table - read the configure table and save it.
398 * @pm8001_ha: our hba card information
399 */
400 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
401 {
402 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
403
404 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
405 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
406 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
407 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
408 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
409 pm8001_mr32(address, MAIN_FW_REVISION);
410 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
411 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
412 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
413 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
414 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
415 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
416 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
417 pm8001_mr32(address, MAIN_GST_OFFSET);
418 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
419 pm8001_mr32(address, MAIN_IBQ_OFFSET);
420 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
421 pm8001_mr32(address, MAIN_OBQ_OFFSET);
422
423 /* read Error Dump Offset and Length */
424 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
425 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
426 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
427 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
428 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
429 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
430 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
431 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
432
433 /* read GPIO LED settings from the configuration table */
434 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
435 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
436
437 /* read analog Setting offset from the configuration table */
438 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
439 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
440
441 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
442 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
443 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
444 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
445 /* read port recover and reset timeout */
446 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
447 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
448 /* read ILA and inactive firmware version */
449 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
450 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
451 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
452 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
453
454 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
455 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
456 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
457 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
458 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev));
459
460 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
461 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
462 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
463 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
464 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
465 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
466 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset));
467
468 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
469 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
470 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
471 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version));
472 }
473
474 /**
475 * read_general_status_table - read the general status table and save it.
476 * @pm8001_ha: our hba card information
477 */
478 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
479 {
480 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
481 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
482 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
483 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
484 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
485 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
486 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
487 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
488 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
489 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
490 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
491 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
492 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
493 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
494 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
495 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
496 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
497 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
498 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
499 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
500 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
501 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
502 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
503 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
504 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
505 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
506 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
507 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
508 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
509 }
510 /**
511 * read_phy_attr_table - read the phy attribute table and save it.
512 * @pm8001_ha: our hba card information
513 */
514 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
515 {
516 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
517 pm8001_ha->phy_attr_table.phystart1_16[0] =
518 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
519 pm8001_ha->phy_attr_table.phystart1_16[1] =
520 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
521 pm8001_ha->phy_attr_table.phystart1_16[2] =
522 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
523 pm8001_ha->phy_attr_table.phystart1_16[3] =
524 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
525 pm8001_ha->phy_attr_table.phystart1_16[4] =
526 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
527 pm8001_ha->phy_attr_table.phystart1_16[5] =
528 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
529 pm8001_ha->phy_attr_table.phystart1_16[6] =
530 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
531 pm8001_ha->phy_attr_table.phystart1_16[7] =
532 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
533 pm8001_ha->phy_attr_table.phystart1_16[8] =
534 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
535 pm8001_ha->phy_attr_table.phystart1_16[9] =
536 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
537 pm8001_ha->phy_attr_table.phystart1_16[10] =
538 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
539 pm8001_ha->phy_attr_table.phystart1_16[11] =
540 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
541 pm8001_ha->phy_attr_table.phystart1_16[12] =
542 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
543 pm8001_ha->phy_attr_table.phystart1_16[13] =
544 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
545 pm8001_ha->phy_attr_table.phystart1_16[14] =
546 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
547 pm8001_ha->phy_attr_table.phystart1_16[15] =
548 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
549
550 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
551 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
552 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
553 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
554 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
555 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
556 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
557 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
558 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
559 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
560 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
561 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
562 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
563 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
564 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
565 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
566 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
567 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
568 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
569 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
570 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
571 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
572 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
573 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
574 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
575 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
576 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
577 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
578 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
579 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
580 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
581 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
582
583 }
584
585 /**
586 * read_inbnd_queue_table - read the inbound queue table and save it.
587 * @pm8001_ha: our hba card information
588 */
589 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
590 {
591 int i;
592 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
593 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
594 u32 offset = i * 0x20;
595 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
596 get_pci_bar_index(pm8001_mr32(address,
597 (offset + IB_PIPCI_BAR)));
598 pm8001_ha->inbnd_q_tbl[i].pi_offset =
599 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
600 }
601 }
602
603 /**
604 * read_outbnd_queue_table - read the outbound queue table and save it.
605 * @pm8001_ha: our hba card information
606 */
607 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
608 {
609 int i;
610 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
611 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
612 u32 offset = i * 0x24;
613 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
614 get_pci_bar_index(pm8001_mr32(address,
615 (offset + OB_CIPCI_BAR)));
616 pm8001_ha->outbnd_q_tbl[i].ci_offset =
617 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
618 }
619 }
620
621 /**
622 * init_default_table_values - init the default table.
623 * @pm8001_ha: our hba card information
624 */
625 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
626 {
627 int i;
628 u32 offsetib, offsetob;
629 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
630 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
631
632 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
633 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
634 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
635 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
636 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
637 PM8001_EVENT_LOG_SIZE;
638 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
639 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
640 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
641 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
642 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
643 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
644 PM8001_EVENT_LOG_SIZE;
645 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
646 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
647
648 /* Disable end to end CRC checking */
649 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
650
651 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
652 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
653 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
654 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
655 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
656 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
657 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
658 pm8001_ha->inbnd_q_tbl[i].base_virt =
659 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
660 pm8001_ha->inbnd_q_tbl[i].total_length =
661 pm8001_ha->memoryMap.region[IB + i].total_len;
662 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
663 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
664 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
665 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
666 pm8001_ha->inbnd_q_tbl[i].ci_virt =
667 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
668 offsetib = i * 0x20;
669 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
670 get_pci_bar_index(pm8001_mr32(addressib,
671 (offsetib + 0x14)));
672 pm8001_ha->inbnd_q_tbl[i].pi_offset =
673 pm8001_mr32(addressib, (offsetib + 0x18));
674 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
675 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
676
677 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
678 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
679 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
680 pm8001_ha->inbnd_q_tbl[i].pi_offset));
681 }
682 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
683 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
684 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
685 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
686 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
687 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
688 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
689 pm8001_ha->outbnd_q_tbl[i].base_virt =
690 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
691 pm8001_ha->outbnd_q_tbl[i].total_length =
692 pm8001_ha->memoryMap.region[OB + i].total_len;
693 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
694 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
695 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
696 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
697 /* interrupt vector based on oq */
698 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
699 pm8001_ha->outbnd_q_tbl[i].pi_virt =
700 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
701 offsetob = i * 0x24;
702 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
703 get_pci_bar_index(pm8001_mr32(addressob,
704 offsetob + 0x14));
705 pm8001_ha->outbnd_q_tbl[i].ci_offset =
706 pm8001_mr32(addressob, (offsetob + 0x18));
707 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
708 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
709
710 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
711 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
712 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
713 pm8001_ha->outbnd_q_tbl[i].ci_offset));
714 }
715 }
716
717 /**
718 * update_main_config_table - update the main default table to the HBA.
719 * @pm8001_ha: our hba card information
720 */
721 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
722 {
723 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
724 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
725 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
726 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
727 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
728 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
729 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
730 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
731 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
732 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
733 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
734 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
735 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
736 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
737 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
738 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
739 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
740 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
741 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
742 /* Update Fatal error interrupt vector */
743 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
744 ((pm8001_ha->number_of_intr - 1) << 8);
745 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
746 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
747 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
748 "Updated Fatal error interrupt vector 0x%x\n",
749 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)));
750
751 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
752 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
753
754 /* SPCv specific */
755 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
756 /* Set GPIOLED to 0x2 for LED indicator */
757 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
758 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
759 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
760 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
761 "Programming DW 0x21 in main cfg table with 0x%x\n",
762 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)));
763
764 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
765 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
766 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
767 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
768
769 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
770 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
771 PORT_RECOVERY_TIMEOUT;
772 if (pm8001_ha->chip_id == chip_8006) {
773 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
774 0x0000ffff;
775 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
776 CHIP_8006_PORT_RECOVERY_TIMEOUT;
777 }
778 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
779 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
780 }
781
782 /**
783 * update_inbnd_queue_table - update the inbound queue table to the HBA.
784 * @pm8001_ha: our hba card information
785 */
786 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
787 int number)
788 {
789 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
790 u16 offset = number * 0x20;
791 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
792 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
793 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
794 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
795 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
796 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
797 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
798 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
799 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
800 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
801
802 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
803 "IQ %d: Element pri size 0x%x\n",
804 number,
805 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt));
806
807 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
808 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
809 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
810 pm8001_ha->inbnd_q_tbl[number].lower_base_addr));
811
812 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
813 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
814 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
815 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr));
816 }
817
818 /**
819 * update_outbnd_queue_table - update the outbound queue table to the HBA.
820 * @pm8001_ha: our hba card information
821 */
822 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
823 int number)
824 {
825 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
826 u16 offset = number * 0x24;
827 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
828 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
829 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
830 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
831 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
832 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
833 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
834 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
835 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
836 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
837 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
838 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
839
840 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
841 "OQ %d: Element pri size 0x%x\n",
842 number,
843 pm8001_ha->outbnd_q_tbl[number].element_size_cnt));
844
845 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
846 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
847 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
848 pm8001_ha->outbnd_q_tbl[number].lower_base_addr));
849
850 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
851 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
852 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
853 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr));
854 }
855
856 /**
857 * mpi_init_check - check firmware initialization status.
858 * @pm8001_ha: our hba card information
859 */
860 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
861 {
862 u32 max_wait_count;
863 u32 value;
864 u32 gst_len_mpistate;
865
866 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
867 table is updated */
868 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
869 /* wait until Inbound DoorBell Clear Register toggled */
870 if (IS_SPCV_12G(pm8001_ha->pdev)) {
871 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
872 } else {
873 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
874 }
875 do {
876 udelay(1);
877 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
878 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
879 } while ((value != 0) && (--max_wait_count));
880
881 if (!max_wait_count)
882 return -1;
883 /* check the MPI-State for initialization upto 100ms*/
884 max_wait_count = 100 * 1000;/* 100 msec */
885 do {
886 udelay(1);
887 gst_len_mpistate =
888 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
889 GST_GSTLEN_MPIS_OFFSET);
890 } while ((GST_MPI_STATE_INIT !=
891 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
892 if (!max_wait_count)
893 return -1;
894
895 /* check MPI Initialization error */
896 gst_len_mpistate = gst_len_mpistate >> 16;
897 if (0x0000 != gst_len_mpistate)
898 return -1;
899
900 return 0;
901 }
902
903 /**
904 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
905 * @pm8001_ha: our hba card information
906 */
907 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
908 {
909 u32 value;
910 u32 max_wait_count;
911 u32 max_wait_time;
912 int ret = 0;
913
914 /* reset / PCIe ready */
915 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
916 do {
917 udelay(1);
918 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
919 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
920
921 /* check ila status */
922 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
923 do {
924 udelay(1);
925 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
926 } while (((value & SCRATCH_PAD_ILA_READY) !=
927 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
928 if (!max_wait_count)
929 ret = -1;
930 else {
931 PM8001_MSG_DBG(pm8001_ha,
932 pm8001_printk(" ila ready status in %d millisec\n",
933 (max_wait_time - max_wait_count)));
934 }
935
936 /* check RAAE status */
937 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
938 do {
939 udelay(1);
940 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
941 } while (((value & SCRATCH_PAD_RAAE_READY) !=
942 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
943 if (!max_wait_count)
944 ret = -1;
945 else {
946 PM8001_MSG_DBG(pm8001_ha,
947 pm8001_printk(" raae ready status in %d millisec\n",
948 (max_wait_time - max_wait_count)));
949 }
950
951 /* check iop0 status */
952 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
953 do {
954 udelay(1);
955 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
956 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
957 (--max_wait_count));
958 if (!max_wait_count)
959 ret = -1;
960 else {
961 PM8001_MSG_DBG(pm8001_ha,
962 pm8001_printk(" iop0 ready status in %d millisec\n",
963 (max_wait_time - max_wait_count)));
964 }
965
966 /* check iop1 status only for 16 port controllers */
967 if ((pm8001_ha->chip_id != chip_8008) &&
968 (pm8001_ha->chip_id != chip_8009)) {
969 /* 200 milli sec */
970 max_wait_time = max_wait_count = 200 * 1000;
971 do {
972 udelay(1);
973 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
974 } while (((value & SCRATCH_PAD_IOP1_READY) !=
975 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
976 if (!max_wait_count)
977 ret = -1;
978 else {
979 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
980 "iop1 ready status in %d millisec\n",
981 (max_wait_time - max_wait_count)));
982 }
983 }
984
985 return ret;
986 }
987
988 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
989 {
990 void __iomem *base_addr;
991 u32 value;
992 u32 offset;
993 u32 pcibar;
994 u32 pcilogic;
995
996 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
997 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
998
999 PM8001_DEV_DBG(pm8001_ha,
1000 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
1001 offset, value));
1002 pcilogic = (value & 0xFC000000) >> 26;
1003 pcibar = get_pci_bar_index(pcilogic);
1004 PM8001_INIT_DBG(pm8001_ha,
1005 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
1006 pm8001_ha->main_cfg_tbl_addr = base_addr =
1007 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1008 pm8001_ha->general_stat_tbl_addr =
1009 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1010 0xFFFFFF);
1011 pm8001_ha->inbnd_q_tbl_addr =
1012 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1013 0xFFFFFF);
1014 pm8001_ha->outbnd_q_tbl_addr =
1015 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1016 0xFFFFFF);
1017 pm8001_ha->ivt_tbl_addr =
1018 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1019 0xFFFFFF);
1020 pm8001_ha->pspa_q_tbl_addr =
1021 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1022 0xFFFFFF);
1023 pm8001_ha->fatal_tbl_addr =
1024 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1025 0xFFFFFF);
1026
1027 PM8001_INIT_DBG(pm8001_ha,
1028 pm8001_printk("GST OFFSET 0x%x\n",
1029 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
1030 PM8001_INIT_DBG(pm8001_ha,
1031 pm8001_printk("INBND OFFSET 0x%x\n",
1032 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
1033 PM8001_INIT_DBG(pm8001_ha,
1034 pm8001_printk("OBND OFFSET 0x%x\n",
1035 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
1036 PM8001_INIT_DBG(pm8001_ha,
1037 pm8001_printk("IVT OFFSET 0x%x\n",
1038 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
1039 PM8001_INIT_DBG(pm8001_ha,
1040 pm8001_printk("PSPA OFFSET 0x%x\n",
1041 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
1042 PM8001_INIT_DBG(pm8001_ha,
1043 pm8001_printk("addr - main cfg %p general status %p\n",
1044 pm8001_ha->main_cfg_tbl_addr,
1045 pm8001_ha->general_stat_tbl_addr));
1046 PM8001_INIT_DBG(pm8001_ha,
1047 pm8001_printk("addr - inbnd %p obnd %p\n",
1048 pm8001_ha->inbnd_q_tbl_addr,
1049 pm8001_ha->outbnd_q_tbl_addr));
1050 PM8001_INIT_DBG(pm8001_ha,
1051 pm8001_printk("addr - pspa %p ivt %p\n",
1052 pm8001_ha->pspa_q_tbl_addr,
1053 pm8001_ha->ivt_tbl_addr));
1054 }
1055
1056 /**
1057 * pm80xx_set_thermal_config - support the thermal configuration
1058 * @pm8001_ha: our hba card information.
1059 */
1060 int
1061 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1062 {
1063 struct set_ctrl_cfg_req payload;
1064 struct inbound_queue_table *circularQ;
1065 int rc;
1066 u32 tag;
1067 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1068 u32 page_code;
1069
1070 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1071 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1072 if (rc)
1073 return -1;
1074
1075 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1076 payload.tag = cpu_to_le32(tag);
1077
1078 if (IS_SPCV_12G(pm8001_ha->pdev))
1079 page_code = THERMAL_PAGE_CODE_7H;
1080 else
1081 page_code = THERMAL_PAGE_CODE_8H;
1082
1083 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
1084 (THERMAL_ENABLE << 8) | page_code;
1085 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
1086
1087 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1088 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1089 payload.cfg_pg[0], payload.cfg_pg[1]));
1090
1091 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1092 sizeof(payload), 0);
1093 if (rc)
1094 pm8001_tag_free(pm8001_ha, tag);
1095 return rc;
1096
1097 }
1098
1099 /**
1100 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1101 * Timer configuration page
1102 * @pm8001_ha: our hba card information.
1103 */
1104 static int
1105 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1106 {
1107 struct set_ctrl_cfg_req payload;
1108 struct inbound_queue_table *circularQ;
1109 SASProtocolTimerConfig_t SASConfigPage;
1110 int rc;
1111 u32 tag;
1112 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1113
1114 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1115 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1116
1117 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1118
1119 if (rc)
1120 return -1;
1121
1122 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1123 payload.tag = cpu_to_le32(tag);
1124
1125 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
1126 SASConfigPage.MST_MSI = 3 << 15;
1127 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
1128 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
1129 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
1130 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
1131
1132 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
1133 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
1134
1135
1136 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
1137 SAS_OPNRJT_RTRY_INTVL;
1138 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
1139 | SAS_COPNRJT_RTRY_TMO;
1140 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
1141 | SAS_COPNRJT_RTRY_THR;
1142 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
1143
1144 PM8001_INIT_DBG(pm8001_ha,
1145 pm8001_printk("SASConfigPage.pageCode "
1146 "0x%08x\n", SASConfigPage.pageCode));
1147 PM8001_INIT_DBG(pm8001_ha,
1148 pm8001_printk("SASConfigPage.MST_MSI "
1149 " 0x%08x\n", SASConfigPage.MST_MSI));
1150 PM8001_INIT_DBG(pm8001_ha,
1151 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
1152 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
1153 PM8001_INIT_DBG(pm8001_ha,
1154 pm8001_printk("SASConfigPage.STP_FRM_TMO "
1155 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
1156 PM8001_INIT_DBG(pm8001_ha,
1157 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
1158 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
1159 PM8001_INIT_DBG(pm8001_ha,
1160 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
1161 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
1162 PM8001_INIT_DBG(pm8001_ha,
1163 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
1164 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1165 PM8001_INIT_DBG(pm8001_ha,
1166 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
1167 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1168 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
1169 " 0x%08x\n", SASConfigPage.MAX_AIP));
1170
1171 memcpy(&payload.cfg_pg, &SASConfigPage,
1172 sizeof(SASProtocolTimerConfig_t));
1173
1174 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1175 sizeof(payload), 0);
1176 if (rc)
1177 pm8001_tag_free(pm8001_ha, tag);
1178
1179 return rc;
1180 }
1181
1182 /**
1183 * pm80xx_get_encrypt_info - Check for encryption
1184 * @pm8001_ha: our hba card information.
1185 */
1186 static int
1187 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1188 {
1189 u32 scratch3_value;
1190 int ret = -1;
1191
1192 /* Read encryption status from SCRATCH PAD 3 */
1193 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1194
1195 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1196 SCRATCH_PAD3_ENC_READY) {
1197 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1198 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1199 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1200 SCRATCH_PAD3_SMF_ENABLED)
1201 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1202 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1203 SCRATCH_PAD3_SMA_ENABLED)
1204 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1205 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1206 SCRATCH_PAD3_SMB_ENABLED)
1207 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1208 pm8001_ha->encrypt_info.status = 0;
1209 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1210 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
1211 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1212 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1213 pm8001_ha->encrypt_info.sec_mode,
1214 pm8001_ha->encrypt_info.status));
1215 ret = 0;
1216 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1217 SCRATCH_PAD3_ENC_DISABLED) {
1218 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1219 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1220 scratch3_value));
1221 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1222 pm8001_ha->encrypt_info.cipher_mode = 0;
1223 pm8001_ha->encrypt_info.sec_mode = 0;
1224 ret = 0;
1225 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1226 SCRATCH_PAD3_ENC_DIS_ERR) {
1227 pm8001_ha->encrypt_info.status =
1228 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1229 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1230 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1231 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1232 SCRATCH_PAD3_SMF_ENABLED)
1233 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1234 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1235 SCRATCH_PAD3_SMA_ENABLED)
1236 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1237 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1238 SCRATCH_PAD3_SMB_ENABLED)
1239 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1240 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1241 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1242 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1243 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1244 pm8001_ha->encrypt_info.sec_mode,
1245 pm8001_ha->encrypt_info.status));
1246 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1247 SCRATCH_PAD3_ENC_ENA_ERR) {
1248
1249 pm8001_ha->encrypt_info.status =
1250 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1251 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1252 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1253 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1254 SCRATCH_PAD3_SMF_ENABLED)
1255 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1256 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1257 SCRATCH_PAD3_SMA_ENABLED)
1258 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1259 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1260 SCRATCH_PAD3_SMB_ENABLED)
1261 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1262
1263 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1264 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1265 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1266 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1267 pm8001_ha->encrypt_info.sec_mode,
1268 pm8001_ha->encrypt_info.status));
1269 }
1270 return ret;
1271 }
1272
1273 /**
1274 * pm80xx_encrypt_update - update flash with encryption informtion
1275 * @pm8001_ha: our hba card information.
1276 */
1277 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1278 {
1279 struct kek_mgmt_req payload;
1280 struct inbound_queue_table *circularQ;
1281 int rc;
1282 u32 tag;
1283 u32 opc = OPC_INB_KEK_MANAGEMENT;
1284
1285 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1286 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1287 if (rc)
1288 return -1;
1289
1290 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1291 payload.tag = cpu_to_le32(tag);
1292 /* Currently only one key is used. New KEK index is 1.
1293 * Current KEK index is 1. Store KEK to NVRAM is 1.
1294 */
1295 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1296 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1297
1298 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1299 "Saving Encryption info to flash. payload 0x%x\n",
1300 payload.new_curidx_ksop));
1301
1302 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1303 sizeof(payload), 0);
1304 if (rc)
1305 pm8001_tag_free(pm8001_ha, tag);
1306
1307 return rc;
1308 }
1309
1310 /**
1311 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1312 * @pm8001_ha: our hba card information
1313 */
1314 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1315 {
1316 int ret;
1317 u8 i = 0;
1318
1319 /* check the firmware status */
1320 if (-1 == check_fw_ready(pm8001_ha)) {
1321 PM8001_FAIL_DBG(pm8001_ha,
1322 pm8001_printk("Firmware is not ready!\n"));
1323 return -EBUSY;
1324 }
1325
1326 /* Initialize the controller fatal error flag */
1327 pm8001_ha->controller_fatal_error = false;
1328
1329 /* Initialize pci space address eg: mpi offset */
1330 init_pci_device_addresses(pm8001_ha);
1331 init_default_table_values(pm8001_ha);
1332 read_main_config_table(pm8001_ha);
1333 read_general_status_table(pm8001_ha);
1334 read_inbnd_queue_table(pm8001_ha);
1335 read_outbnd_queue_table(pm8001_ha);
1336 read_phy_attr_table(pm8001_ha);
1337
1338 /* update main config table ,inbound table and outbound table */
1339 update_main_config_table(pm8001_ha);
1340 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1341 update_inbnd_queue_table(pm8001_ha, i);
1342 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1343 update_outbnd_queue_table(pm8001_ha, i);
1344
1345 /* notify firmware update finished and check initialization status */
1346 if (0 == mpi_init_check(pm8001_ha)) {
1347 PM8001_INIT_DBG(pm8001_ha,
1348 pm8001_printk("MPI initialize successful!\n"));
1349 } else
1350 return -EBUSY;
1351
1352 /* send SAS protocol timer configuration page to FW */
1353 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1354
1355 /* Check for encryption */
1356 if (pm8001_ha->chip->encrypt) {
1357 PM8001_INIT_DBG(pm8001_ha,
1358 pm8001_printk("Checking for encryption\n"));
1359 ret = pm80xx_get_encrypt_info(pm8001_ha);
1360 if (ret == -1) {
1361 PM8001_INIT_DBG(pm8001_ha,
1362 pm8001_printk("Encryption error !!\n"));
1363 if (pm8001_ha->encrypt_info.status == 0x81) {
1364 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1365 "Encryption enabled with error."
1366 "Saving encryption key to flash\n"));
1367 pm80xx_encrypt_update(pm8001_ha);
1368 }
1369 }
1370 }
1371 return 0;
1372 }
1373
1374 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1375 {
1376 u32 max_wait_count;
1377 u32 value;
1378 u32 gst_len_mpistate;
1379 init_pci_device_addresses(pm8001_ha);
1380 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1381 table is stop */
1382 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1383
1384 /* wait until Inbound DoorBell Clear Register toggled */
1385 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1386 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1387 } else {
1388 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1389 }
1390 do {
1391 udelay(1);
1392 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1393 value &= SPCv_MSGU_CFG_TABLE_RESET;
1394 } while ((value != 0) && (--max_wait_count));
1395
1396 if (!max_wait_count) {
1397 PM8001_FAIL_DBG(pm8001_ha,
1398 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1399 return -1;
1400 }
1401
1402 /* check the MPI-State for termination in progress */
1403 /* wait until Inbound DoorBell Clear Register toggled */
1404 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
1405 do {
1406 udelay(1);
1407 gst_len_mpistate =
1408 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1409 GST_GSTLEN_MPIS_OFFSET);
1410 if (GST_MPI_STATE_UNINIT ==
1411 (gst_len_mpistate & GST_MPI_STATE_MASK))
1412 break;
1413 } while (--max_wait_count);
1414 if (!max_wait_count) {
1415 PM8001_FAIL_DBG(pm8001_ha,
1416 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1417 gst_len_mpistate & GST_MPI_STATE_MASK));
1418 return -1;
1419 }
1420
1421 return 0;
1422 }
1423
1424 /**
1425 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1426 * the FW register status to the originated status.
1427 * @pm8001_ha: our hba card information
1428 */
1429
1430 static int
1431 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1432 {
1433 u32 regval;
1434 u32 bootloader_state;
1435 u32 ibutton0, ibutton1;
1436
1437 /* Process MPI table uninitialization only if FW is ready */
1438 if (!pm8001_ha->controller_fatal_error) {
1439 /* Check if MPI is in ready state to reset */
1440 if (mpi_uninit_check(pm8001_ha) != 0) {
1441 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1442 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1443 "MPI state is not ready scratch1 :0x%x\n",
1444 regval));
1445 return -1;
1446 }
1447 }
1448 /* checked for reset register normal state; 0x0 */
1449 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1450 PM8001_INIT_DBG(pm8001_ha,
1451 pm8001_printk("reset register before write : 0x%x\n", regval));
1452
1453 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1454 msleep(500);
1455
1456 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1457 PM8001_INIT_DBG(pm8001_ha,
1458 pm8001_printk("reset register after write 0x%x\n", regval));
1459
1460 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1461 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1462 PM8001_MSG_DBG(pm8001_ha,
1463 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1464 regval));
1465 } else {
1466 PM8001_MSG_DBG(pm8001_ha,
1467 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1468 regval));
1469
1470 /* check bootloader is successfully executed or in HDA mode */
1471 bootloader_state =
1472 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1473 SCRATCH_PAD1_BOOTSTATE_MASK;
1474
1475 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1476 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1477 "Bootloader state - HDA mode SEEPROM\n"));
1478 } else if (bootloader_state ==
1479 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1480 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1481 "Bootloader state - HDA mode Bootstrap Pin\n"));
1482 } else if (bootloader_state ==
1483 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1484 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1485 "Bootloader state - HDA mode soft reset\n"));
1486 } else if (bootloader_state ==
1487 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1488 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1489 "Bootloader state-HDA mode critical error\n"));
1490 }
1491 return -EBUSY;
1492 }
1493
1494 /* check the firmware status after reset */
1495 if (-1 == check_fw_ready(pm8001_ha)) {
1496 PM8001_FAIL_DBG(pm8001_ha,
1497 pm8001_printk("Firmware is not ready!\n"));
1498 /* check iButton feature support for motherboard controller */
1499 if (pm8001_ha->pdev->subsystem_vendor !=
1500 PCI_VENDOR_ID_ADAPTEC2 &&
1501 pm8001_ha->pdev->subsystem_vendor !=
1502 PCI_VENDOR_ID_ATTO &&
1503 pm8001_ha->pdev->subsystem_vendor != 0) {
1504 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1505 MSGU_HOST_SCRATCH_PAD_6);
1506 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1507 MSGU_HOST_SCRATCH_PAD_7);
1508 if (!ibutton0 && !ibutton1) {
1509 PM8001_FAIL_DBG(pm8001_ha,
1510 pm8001_printk("iButton Feature is"
1511 " not Available!!!\n"));
1512 return -EBUSY;
1513 }
1514 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1515 PM8001_FAIL_DBG(pm8001_ha,
1516 pm8001_printk("CRC Check for iButton"
1517 " Feature Failed!!!\n"));
1518 return -EBUSY;
1519 }
1520 }
1521 }
1522 PM8001_INIT_DBG(pm8001_ha,
1523 pm8001_printk("SPCv soft reset Complete\n"));
1524 return 0;
1525 }
1526
1527 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1528 {
1529 u32 i;
1530
1531 PM8001_INIT_DBG(pm8001_ha,
1532 pm8001_printk("chip reset start\n"));
1533
1534 /* do SPCv chip reset. */
1535 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1536 PM8001_INIT_DBG(pm8001_ha,
1537 pm8001_printk("SPC soft reset Complete\n"));
1538
1539 /* Check this ..whether delay is required or no */
1540 /* delay 10 usec */
1541 udelay(10);
1542
1543 /* wait for 20 msec until the firmware gets reloaded */
1544 i = 20;
1545 do {
1546 mdelay(1);
1547 } while ((--i) != 0);
1548
1549 PM8001_INIT_DBG(pm8001_ha,
1550 pm8001_printk("chip reset finished\n"));
1551 }
1552
1553 /**
1554 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1555 * @pm8001_ha: our hba card information
1556 */
1557 static void
1558 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1559 {
1560 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1561 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1562 }
1563
1564 /**
1565 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1566 * @pm8001_ha: our hba card information
1567 */
1568 static void
1569 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1570 {
1571 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1572 }
1573
1574 /**
1575 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1576 * @pm8001_ha: our hba card information
1577 */
1578 static void
1579 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1580 {
1581 #ifdef PM8001_USE_MSIX
1582 u32 mask;
1583 mask = (u32)(1 << vec);
1584
1585 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1586 return;
1587 #endif
1588 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1589
1590 }
1591
1592 /**
1593 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1594 * @pm8001_ha: our hba card information
1595 */
1596 static void
1597 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1598 {
1599 #ifdef PM8001_USE_MSIX
1600 u32 mask;
1601 if (vec == 0xFF)
1602 mask = 0xFFFFFFFF;
1603 else
1604 mask = (u32)(1 << vec);
1605 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1606 return;
1607 #endif
1608 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1609 }
1610
1611 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1612 struct pm8001_device *pm8001_ha_dev)
1613 {
1614 int res;
1615 u32 ccb_tag;
1616 struct pm8001_ccb_info *ccb;
1617 struct sas_task *task = NULL;
1618 struct task_abort_req task_abort;
1619 struct inbound_queue_table *circularQ;
1620 u32 opc = OPC_INB_SATA_ABORT;
1621 int ret;
1622
1623 if (!pm8001_ha_dev) {
1624 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1625 return;
1626 }
1627
1628 task = sas_alloc_slow_task(GFP_ATOMIC);
1629
1630 if (!task) {
1631 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1632 "allocate task\n"));
1633 return;
1634 }
1635
1636 task->task_done = pm8001_task_done;
1637
1638 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1639 if (res) {
1640 sas_free_task(task);
1641 return;
1642 }
1643
1644 ccb = &pm8001_ha->ccb_info[ccb_tag];
1645 ccb->device = pm8001_ha_dev;
1646 ccb->ccb_tag = ccb_tag;
1647 ccb->task = task;
1648
1649 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1650
1651 memset(&task_abort, 0, sizeof(task_abort));
1652 task_abort.abort_all = cpu_to_le32(1);
1653 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1654 task_abort.tag = cpu_to_le32(ccb_tag);
1655
1656 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1657 sizeof(task_abort), 0);
1658 PM8001_FAIL_DBG(pm8001_ha,
1659 pm8001_printk("Executing abort task end\n"));
1660 if (ret) {
1661 sas_free_task(task);
1662 pm8001_tag_free(pm8001_ha, ccb_tag);
1663 }
1664 }
1665
1666 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1667 struct pm8001_device *pm8001_ha_dev)
1668 {
1669 struct sata_start_req sata_cmd;
1670 int res;
1671 u32 ccb_tag;
1672 struct pm8001_ccb_info *ccb;
1673 struct sas_task *task = NULL;
1674 struct host_to_dev_fis fis;
1675 struct domain_device *dev;
1676 struct inbound_queue_table *circularQ;
1677 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1678
1679 task = sas_alloc_slow_task(GFP_ATOMIC);
1680
1681 if (!task) {
1682 PM8001_FAIL_DBG(pm8001_ha,
1683 pm8001_printk("cannot allocate task !!!\n"));
1684 return;
1685 }
1686 task->task_done = pm8001_task_done;
1687
1688 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1689 if (res) {
1690 sas_free_task(task);
1691 PM8001_FAIL_DBG(pm8001_ha,
1692 pm8001_printk("cannot allocate tag !!!\n"));
1693 return;
1694 }
1695
1696 /* allocate domain device by ourselves as libsas
1697 * is not going to provide any
1698 */
1699 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1700 if (!dev) {
1701 sas_free_task(task);
1702 pm8001_tag_free(pm8001_ha, ccb_tag);
1703 PM8001_FAIL_DBG(pm8001_ha,
1704 pm8001_printk("Domain device cannot be allocated\n"));
1705 return;
1706 }
1707
1708 task->dev = dev;
1709 task->dev->lldd_dev = pm8001_ha_dev;
1710
1711 ccb = &pm8001_ha->ccb_info[ccb_tag];
1712 ccb->device = pm8001_ha_dev;
1713 ccb->ccb_tag = ccb_tag;
1714 ccb->task = task;
1715 ccb->n_elem = 0;
1716 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1717 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1718
1719 memset(&sata_cmd, 0, sizeof(sata_cmd));
1720 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1721
1722 /* construct read log FIS */
1723 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1724 fis.fis_type = 0x27;
1725 fis.flags = 0x80;
1726 fis.command = ATA_CMD_READ_LOG_EXT;
1727 fis.lbal = 0x10;
1728 fis.sector_count = 0x1;
1729
1730 sata_cmd.tag = cpu_to_le32(ccb_tag);
1731 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1732 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1733 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1734
1735 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1736 sizeof(sata_cmd), 0);
1737 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Executing read log end\n"));
1738 if (res) {
1739 sas_free_task(task);
1740 pm8001_tag_free(pm8001_ha, ccb_tag);
1741 kfree(dev);
1742 }
1743 }
1744
1745 /**
1746 * mpi_ssp_completion- process the event that FW response to the SSP request.
1747 * @pm8001_ha: our hba card information
1748 * @piomb: the message contents of this outbound message.
1749 *
1750 * When FW has completed a ssp request for example a IO request, after it has
1751 * filled the SG data with the data, it will trigger this event represent
1752 * that he has finished the job,please check the coresponding buffer.
1753 * So we will tell the caller who maybe waiting the result to tell upper layer
1754 * that the task has been finished.
1755 */
1756 static void
1757 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1758 {
1759 struct sas_task *t;
1760 struct pm8001_ccb_info *ccb;
1761 unsigned long flags;
1762 u32 status;
1763 u32 param;
1764 u32 tag;
1765 struct ssp_completion_resp *psspPayload;
1766 struct task_status_struct *ts;
1767 struct ssp_response_iu *iu;
1768 struct pm8001_device *pm8001_dev;
1769 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1770 status = le32_to_cpu(psspPayload->status);
1771 tag = le32_to_cpu(psspPayload->tag);
1772 ccb = &pm8001_ha->ccb_info[tag];
1773 if ((status == IO_ABORTED) && ccb->open_retry) {
1774 /* Being completed by another */
1775 ccb->open_retry = 0;
1776 return;
1777 }
1778 pm8001_dev = ccb->device;
1779 param = le32_to_cpu(psspPayload->param);
1780 t = ccb->task;
1781
1782 if (status && status != IO_UNDERFLOW)
1783 PM8001_FAIL_DBG(pm8001_ha,
1784 pm8001_printk("sas IO status 0x%x\n", status));
1785 if (unlikely(!t || !t->lldd_task || !t->dev))
1786 return;
1787 ts = &t->task_status;
1788
1789 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1790 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t));
1791
1792 /* Print sas address of IO failed device */
1793 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1794 (status != IO_UNDERFLOW))
1795 PM8001_FAIL_DBG(pm8001_ha,
1796 pm8001_printk("SAS Address of IO Failure Drive"
1797 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1798
1799 switch (status) {
1800 case IO_SUCCESS:
1801 PM8001_IO_DBG(pm8001_ha,
1802 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1803 param));
1804 if (param == 0) {
1805 ts->resp = SAS_TASK_COMPLETE;
1806 ts->stat = SAM_STAT_GOOD;
1807 } else {
1808 ts->resp = SAS_TASK_COMPLETE;
1809 ts->stat = SAS_PROTO_RESPONSE;
1810 ts->residual = param;
1811 iu = &psspPayload->ssp_resp_iu;
1812 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1813 }
1814 if (pm8001_dev)
1815 pm8001_dev->running_req--;
1816 break;
1817 case IO_ABORTED:
1818 PM8001_IO_DBG(pm8001_ha,
1819 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1820 ts->resp = SAS_TASK_COMPLETE;
1821 ts->stat = SAS_ABORTED_TASK;
1822 break;
1823 case IO_UNDERFLOW:
1824 /* SSP Completion with error */
1825 PM8001_IO_DBG(pm8001_ha,
1826 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1827 param));
1828 ts->resp = SAS_TASK_COMPLETE;
1829 ts->stat = SAS_DATA_UNDERRUN;
1830 ts->residual = param;
1831 if (pm8001_dev)
1832 pm8001_dev->running_req--;
1833 break;
1834 case IO_NO_DEVICE:
1835 PM8001_IO_DBG(pm8001_ha,
1836 pm8001_printk("IO_NO_DEVICE\n"));
1837 ts->resp = SAS_TASK_UNDELIVERED;
1838 ts->stat = SAS_PHY_DOWN;
1839 break;
1840 case IO_XFER_ERROR_BREAK:
1841 PM8001_IO_DBG(pm8001_ha,
1842 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1843 ts->resp = SAS_TASK_COMPLETE;
1844 ts->stat = SAS_OPEN_REJECT;
1845 /* Force the midlayer to retry */
1846 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1847 break;
1848 case IO_XFER_ERROR_PHY_NOT_READY:
1849 PM8001_IO_DBG(pm8001_ha,
1850 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1851 ts->resp = SAS_TASK_COMPLETE;
1852 ts->stat = SAS_OPEN_REJECT;
1853 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1854 break;
1855 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1856 PM8001_IO_DBG(pm8001_ha,
1857 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1858 ts->resp = SAS_TASK_COMPLETE;
1859 ts->stat = SAS_OPEN_REJECT;
1860 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1861 break;
1862 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1863 PM8001_IO_DBG(pm8001_ha,
1864 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1865 ts->resp = SAS_TASK_COMPLETE;
1866 ts->stat = SAS_OPEN_REJECT;
1867 ts->open_rej_reason = SAS_OREJ_EPROTO;
1868 break;
1869 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1870 PM8001_IO_DBG(pm8001_ha,
1871 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1872 ts->resp = SAS_TASK_COMPLETE;
1873 ts->stat = SAS_OPEN_REJECT;
1874 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1875 break;
1876 case IO_OPEN_CNX_ERROR_BREAK:
1877 PM8001_IO_DBG(pm8001_ha,
1878 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1879 ts->resp = SAS_TASK_COMPLETE;
1880 ts->stat = SAS_OPEN_REJECT;
1881 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1882 break;
1883 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1884 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1885 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1886 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1887 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1888 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1889 PM8001_IO_DBG(pm8001_ha,
1890 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1891 ts->resp = SAS_TASK_COMPLETE;
1892 ts->stat = SAS_OPEN_REJECT;
1893 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1894 if (!t->uldd_task)
1895 pm8001_handle_event(pm8001_ha,
1896 pm8001_dev,
1897 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1898 break;
1899 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1900 PM8001_IO_DBG(pm8001_ha,
1901 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1902 ts->resp = SAS_TASK_COMPLETE;
1903 ts->stat = SAS_OPEN_REJECT;
1904 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1905 break;
1906 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1907 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1908 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1909 ts->resp = SAS_TASK_COMPLETE;
1910 ts->stat = SAS_OPEN_REJECT;
1911 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1912 break;
1913 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1914 PM8001_IO_DBG(pm8001_ha,
1915 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1916 ts->resp = SAS_TASK_UNDELIVERED;
1917 ts->stat = SAS_OPEN_REJECT;
1918 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1919 break;
1920 case IO_XFER_ERROR_NAK_RECEIVED:
1921 PM8001_IO_DBG(pm8001_ha,
1922 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1923 ts->resp = SAS_TASK_COMPLETE;
1924 ts->stat = SAS_OPEN_REJECT;
1925 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1926 break;
1927 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1928 PM8001_IO_DBG(pm8001_ha,
1929 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1930 ts->resp = SAS_TASK_COMPLETE;
1931 ts->stat = SAS_NAK_R_ERR;
1932 break;
1933 case IO_XFER_ERROR_DMA:
1934 PM8001_IO_DBG(pm8001_ha,
1935 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1936 ts->resp = SAS_TASK_COMPLETE;
1937 ts->stat = SAS_OPEN_REJECT;
1938 break;
1939 case IO_XFER_OPEN_RETRY_TIMEOUT:
1940 PM8001_IO_DBG(pm8001_ha,
1941 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1942 ts->resp = SAS_TASK_COMPLETE;
1943 ts->stat = SAS_OPEN_REJECT;
1944 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1945 break;
1946 case IO_XFER_ERROR_OFFSET_MISMATCH:
1947 PM8001_IO_DBG(pm8001_ha,
1948 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1949 ts->resp = SAS_TASK_COMPLETE;
1950 ts->stat = SAS_OPEN_REJECT;
1951 break;
1952 case IO_PORT_IN_RESET:
1953 PM8001_IO_DBG(pm8001_ha,
1954 pm8001_printk("IO_PORT_IN_RESET\n"));
1955 ts->resp = SAS_TASK_COMPLETE;
1956 ts->stat = SAS_OPEN_REJECT;
1957 break;
1958 case IO_DS_NON_OPERATIONAL:
1959 PM8001_IO_DBG(pm8001_ha,
1960 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1961 ts->resp = SAS_TASK_COMPLETE;
1962 ts->stat = SAS_OPEN_REJECT;
1963 if (!t->uldd_task)
1964 pm8001_handle_event(pm8001_ha,
1965 pm8001_dev,
1966 IO_DS_NON_OPERATIONAL);
1967 break;
1968 case IO_DS_IN_RECOVERY:
1969 PM8001_IO_DBG(pm8001_ha,
1970 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1971 ts->resp = SAS_TASK_COMPLETE;
1972 ts->stat = SAS_OPEN_REJECT;
1973 break;
1974 case IO_TM_TAG_NOT_FOUND:
1975 PM8001_IO_DBG(pm8001_ha,
1976 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1977 ts->resp = SAS_TASK_COMPLETE;
1978 ts->stat = SAS_OPEN_REJECT;
1979 break;
1980 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1981 PM8001_IO_DBG(pm8001_ha,
1982 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1983 ts->resp = SAS_TASK_COMPLETE;
1984 ts->stat = SAS_OPEN_REJECT;
1985 break;
1986 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1987 PM8001_IO_DBG(pm8001_ha,
1988 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1989 ts->resp = SAS_TASK_COMPLETE;
1990 ts->stat = SAS_OPEN_REJECT;
1991 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1992 break;
1993 default:
1994 PM8001_DEVIO_DBG(pm8001_ha,
1995 pm8001_printk("Unknown status 0x%x\n", status));
1996 /* not allowed case. Therefore, return failed status */
1997 ts->resp = SAS_TASK_COMPLETE;
1998 ts->stat = SAS_OPEN_REJECT;
1999 break;
2000 }
2001 PM8001_IO_DBG(pm8001_ha,
2002 pm8001_printk("scsi_status = 0x%x\n ",
2003 psspPayload->ssp_resp_iu.status));
2004 spin_lock_irqsave(&t->task_state_lock, flags);
2005 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2006 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2007 t->task_state_flags |= SAS_TASK_STATE_DONE;
2008 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2009 spin_unlock_irqrestore(&t->task_state_lock, flags);
2010 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2011 "task 0x%p done with io_status 0x%x resp 0x%x "
2012 "stat 0x%x but aborted by upper layer!\n",
2013 t, status, ts->resp, ts->stat));
2014 if (t->slow_task)
2015 complete(&t->slow_task->completion);
2016 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2017 } else {
2018 spin_unlock_irqrestore(&t->task_state_lock, flags);
2019 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2020 mb();/* in order to force CPU ordering */
2021 t->task_done(t);
2022 }
2023 }
2024
2025 /*See the comments for mpi_ssp_completion */
2026 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2027 {
2028 struct sas_task *t;
2029 unsigned long flags;
2030 struct task_status_struct *ts;
2031 struct pm8001_ccb_info *ccb;
2032 struct pm8001_device *pm8001_dev;
2033 struct ssp_event_resp *psspPayload =
2034 (struct ssp_event_resp *)(piomb + 4);
2035 u32 event = le32_to_cpu(psspPayload->event);
2036 u32 tag = le32_to_cpu(psspPayload->tag);
2037 u32 port_id = le32_to_cpu(psspPayload->port_id);
2038
2039 ccb = &pm8001_ha->ccb_info[tag];
2040 t = ccb->task;
2041 pm8001_dev = ccb->device;
2042 if (event)
2043 PM8001_FAIL_DBG(pm8001_ha,
2044 pm8001_printk("sas IO status 0x%x\n", event));
2045 if (unlikely(!t || !t->lldd_task || !t->dev))
2046 return;
2047 ts = &t->task_status;
2048 PM8001_IOERR_DBG(pm8001_ha,
2049 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2050 port_id, tag, event));
2051 switch (event) {
2052 case IO_OVERFLOW:
2053 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2054 ts->resp = SAS_TASK_COMPLETE;
2055 ts->stat = SAS_DATA_OVERRUN;
2056 ts->residual = 0;
2057 if (pm8001_dev)
2058 pm8001_dev->running_req--;
2059 break;
2060 case IO_XFER_ERROR_BREAK:
2061 PM8001_IO_DBG(pm8001_ha,
2062 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2063 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2064 return;
2065 case IO_XFER_ERROR_PHY_NOT_READY:
2066 PM8001_IO_DBG(pm8001_ha,
2067 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2068 ts->resp = SAS_TASK_COMPLETE;
2069 ts->stat = SAS_OPEN_REJECT;
2070 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2071 break;
2072 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2073 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2074 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2075 ts->resp = SAS_TASK_COMPLETE;
2076 ts->stat = SAS_OPEN_REJECT;
2077 ts->open_rej_reason = SAS_OREJ_EPROTO;
2078 break;
2079 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2080 PM8001_IO_DBG(pm8001_ha,
2081 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2082 ts->resp = SAS_TASK_COMPLETE;
2083 ts->stat = SAS_OPEN_REJECT;
2084 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2085 break;
2086 case IO_OPEN_CNX_ERROR_BREAK:
2087 PM8001_IO_DBG(pm8001_ha,
2088 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2089 ts->resp = SAS_TASK_COMPLETE;
2090 ts->stat = SAS_OPEN_REJECT;
2091 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2092 break;
2093 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2094 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2095 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2096 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2097 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2098 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2099 PM8001_IO_DBG(pm8001_ha,
2100 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2101 ts->resp = SAS_TASK_COMPLETE;
2102 ts->stat = SAS_OPEN_REJECT;
2103 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2104 if (!t->uldd_task)
2105 pm8001_handle_event(pm8001_ha,
2106 pm8001_dev,
2107 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2108 break;
2109 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2110 PM8001_IO_DBG(pm8001_ha,
2111 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2112 ts->resp = SAS_TASK_COMPLETE;
2113 ts->stat = SAS_OPEN_REJECT;
2114 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2115 break;
2116 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2117 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2118 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2119 ts->resp = SAS_TASK_COMPLETE;
2120 ts->stat = SAS_OPEN_REJECT;
2121 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2122 break;
2123 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2124 PM8001_IO_DBG(pm8001_ha,
2125 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2126 ts->resp = SAS_TASK_COMPLETE;
2127 ts->stat = SAS_OPEN_REJECT;
2128 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2129 break;
2130 case IO_XFER_ERROR_NAK_RECEIVED:
2131 PM8001_IO_DBG(pm8001_ha,
2132 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2133 ts->resp = SAS_TASK_COMPLETE;
2134 ts->stat = SAS_OPEN_REJECT;
2135 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2136 break;
2137 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2138 PM8001_IO_DBG(pm8001_ha,
2139 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2140 ts->resp = SAS_TASK_COMPLETE;
2141 ts->stat = SAS_NAK_R_ERR;
2142 break;
2143 case IO_XFER_OPEN_RETRY_TIMEOUT:
2144 PM8001_IO_DBG(pm8001_ha,
2145 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2146 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2147 return;
2148 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2149 PM8001_IO_DBG(pm8001_ha,
2150 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2151 ts->resp = SAS_TASK_COMPLETE;
2152 ts->stat = SAS_DATA_OVERRUN;
2153 break;
2154 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2155 PM8001_IO_DBG(pm8001_ha,
2156 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2157 ts->resp = SAS_TASK_COMPLETE;
2158 ts->stat = SAS_DATA_OVERRUN;
2159 break;
2160 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2161 PM8001_IO_DBG(pm8001_ha,
2162 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2163 ts->resp = SAS_TASK_COMPLETE;
2164 ts->stat = SAS_DATA_OVERRUN;
2165 break;
2166 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2167 PM8001_IO_DBG(pm8001_ha,
2168 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2169 ts->resp = SAS_TASK_COMPLETE;
2170 ts->stat = SAS_DATA_OVERRUN;
2171 break;
2172 case IO_XFER_ERROR_OFFSET_MISMATCH:
2173 PM8001_IO_DBG(pm8001_ha,
2174 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2175 ts->resp = SAS_TASK_COMPLETE;
2176 ts->stat = SAS_DATA_OVERRUN;
2177 break;
2178 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2179 PM8001_IO_DBG(pm8001_ha,
2180 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2181 ts->resp = SAS_TASK_COMPLETE;
2182 ts->stat = SAS_DATA_OVERRUN;
2183 break;
2184 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2185 PM8001_IOERR_DBG(pm8001_ha,
2186 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2187 /* TBC: used default set values */
2188 ts->resp = SAS_TASK_COMPLETE;
2189 ts->stat = SAS_DATA_OVERRUN;
2190 break;
2191 case IO_XFER_CMD_FRAME_ISSUED:
2192 PM8001_IO_DBG(pm8001_ha,
2193 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2194 return;
2195 default:
2196 PM8001_DEVIO_DBG(pm8001_ha,
2197 pm8001_printk("Unknown status 0x%x\n", event));
2198 /* not allowed case. Therefore, return failed status */
2199 ts->resp = SAS_TASK_COMPLETE;
2200 ts->stat = SAS_DATA_OVERRUN;
2201 break;
2202 }
2203 spin_lock_irqsave(&t->task_state_lock, flags);
2204 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2205 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2206 t->task_state_flags |= SAS_TASK_STATE_DONE;
2207 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2208 spin_unlock_irqrestore(&t->task_state_lock, flags);
2209 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2210 "task 0x%p done with event 0x%x resp 0x%x "
2211 "stat 0x%x but aborted by upper layer!\n",
2212 t, event, ts->resp, ts->stat));
2213 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2214 } else {
2215 spin_unlock_irqrestore(&t->task_state_lock, flags);
2216 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2217 mb();/* in order to force CPU ordering */
2218 t->task_done(t);
2219 }
2220 }
2221
2222 /*See the comments for mpi_ssp_completion */
2223 static void
2224 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2225 {
2226 struct sas_task *t;
2227 struct pm8001_ccb_info *ccb;
2228 u32 param;
2229 u32 status;
2230 u32 tag;
2231 int i, j;
2232 u8 sata_addr_low[4];
2233 u32 temp_sata_addr_low, temp_sata_addr_hi;
2234 u8 sata_addr_hi[4];
2235 struct sata_completion_resp *psataPayload;
2236 struct task_status_struct *ts;
2237 struct ata_task_resp *resp ;
2238 u32 *sata_resp;
2239 struct pm8001_device *pm8001_dev;
2240 unsigned long flags;
2241
2242 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2243 status = le32_to_cpu(psataPayload->status);
2244 tag = le32_to_cpu(psataPayload->tag);
2245
2246 if (!tag) {
2247 PM8001_FAIL_DBG(pm8001_ha,
2248 pm8001_printk("tag null\n"));
2249 return;
2250 }
2251 ccb = &pm8001_ha->ccb_info[tag];
2252 param = le32_to_cpu(psataPayload->param);
2253 if (ccb) {
2254 t = ccb->task;
2255 pm8001_dev = ccb->device;
2256 } else {
2257 PM8001_FAIL_DBG(pm8001_ha,
2258 pm8001_printk("ccb null\n"));
2259 return;
2260 }
2261
2262 if (t) {
2263 if (t->dev && (t->dev->lldd_dev))
2264 pm8001_dev = t->dev->lldd_dev;
2265 } else {
2266 PM8001_FAIL_DBG(pm8001_ha,
2267 pm8001_printk("task null\n"));
2268 return;
2269 }
2270
2271 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2272 && unlikely(!t || !t->lldd_task || !t->dev)) {
2273 PM8001_FAIL_DBG(pm8001_ha,
2274 pm8001_printk("task or dev null\n"));
2275 return;
2276 }
2277
2278 ts = &t->task_status;
2279 if (!ts) {
2280 PM8001_FAIL_DBG(pm8001_ha,
2281 pm8001_printk("ts null\n"));
2282 return;
2283 }
2284
2285 if (unlikely(status))
2286 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk(
2287 "status:0x%x, tag:0x%x, task::0x%p\n",
2288 status, tag, t));
2289
2290 /* Print sas address of IO failed device */
2291 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2292 (status != IO_UNDERFLOW)) {
2293 if (!((t->dev->parent) &&
2294 (dev_is_expander(t->dev->parent->dev_type)))) {
2295 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2296 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2297 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2298 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2299 memcpy(&temp_sata_addr_low, sata_addr_low,
2300 sizeof(sata_addr_low));
2301 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2302 sizeof(sata_addr_hi));
2303 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2304 |((temp_sata_addr_hi << 8) &
2305 0xff0000) |
2306 ((temp_sata_addr_hi >> 8)
2307 & 0xff00) |
2308 ((temp_sata_addr_hi << 24) &
2309 0xff000000));
2310 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2311 & 0xff) |
2312 ((temp_sata_addr_low << 8)
2313 & 0xff0000) |
2314 ((temp_sata_addr_low >> 8)
2315 & 0xff00) |
2316 ((temp_sata_addr_low << 24)
2317 & 0xff000000)) +
2318 pm8001_dev->attached_phy +
2319 0x10);
2320 PM8001_FAIL_DBG(pm8001_ha,
2321 pm8001_printk("SAS Address of IO Failure Drive:"
2322 "%08x%08x", temp_sata_addr_hi,
2323 temp_sata_addr_low));
2324
2325 } else {
2326 PM8001_FAIL_DBG(pm8001_ha,
2327 pm8001_printk("SAS Address of IO Failure Drive:"
2328 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2329 }
2330 }
2331 switch (status) {
2332 case IO_SUCCESS:
2333 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2334 if (param == 0) {
2335 ts->resp = SAS_TASK_COMPLETE;
2336 ts->stat = SAM_STAT_GOOD;
2337 /* check if response is for SEND READ LOG */
2338 if (pm8001_dev &&
2339 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2340 /* set new bit for abort_all */
2341 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2342 /* clear bit for read log */
2343 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2344 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2345 /* Free the tag */
2346 pm8001_tag_free(pm8001_ha, tag);
2347 sas_free_task(t);
2348 return;
2349 }
2350 } else {
2351 u8 len;
2352 ts->resp = SAS_TASK_COMPLETE;
2353 ts->stat = SAS_PROTO_RESPONSE;
2354 ts->residual = param;
2355 PM8001_IO_DBG(pm8001_ha,
2356 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2357 param));
2358 sata_resp = &psataPayload->sata_resp[0];
2359 resp = (struct ata_task_resp *)ts->buf;
2360 if (t->ata_task.dma_xfer == 0 &&
2361 t->data_dir == DMA_FROM_DEVICE) {
2362 len = sizeof(struct pio_setup_fis);
2363 PM8001_IO_DBG(pm8001_ha,
2364 pm8001_printk("PIO read len = %d\n", len));
2365 } else if (t->ata_task.use_ncq) {
2366 len = sizeof(struct set_dev_bits_fis);
2367 PM8001_IO_DBG(pm8001_ha,
2368 pm8001_printk("FPDMA len = %d\n", len));
2369 } else {
2370 len = sizeof(struct dev_to_host_fis);
2371 PM8001_IO_DBG(pm8001_ha,
2372 pm8001_printk("other len = %d\n", len));
2373 }
2374 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2375 resp->frame_len = len;
2376 memcpy(&resp->ending_fis[0], sata_resp, len);
2377 ts->buf_valid_size = sizeof(*resp);
2378 } else
2379 PM8001_IO_DBG(pm8001_ha,
2380 pm8001_printk("response to large\n"));
2381 }
2382 if (pm8001_dev)
2383 pm8001_dev->running_req--;
2384 break;
2385 case IO_ABORTED:
2386 PM8001_IO_DBG(pm8001_ha,
2387 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2388 ts->resp = SAS_TASK_COMPLETE;
2389 ts->stat = SAS_ABORTED_TASK;
2390 if (pm8001_dev)
2391 pm8001_dev->running_req--;
2392 break;
2393 /* following cases are to do cases */
2394 case IO_UNDERFLOW:
2395 /* SATA Completion with error */
2396 PM8001_IO_DBG(pm8001_ha,
2397 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2398 ts->resp = SAS_TASK_COMPLETE;
2399 ts->stat = SAS_DATA_UNDERRUN;
2400 ts->residual = param;
2401 if (pm8001_dev)
2402 pm8001_dev->running_req--;
2403 break;
2404 case IO_NO_DEVICE:
2405 PM8001_IO_DBG(pm8001_ha,
2406 pm8001_printk("IO_NO_DEVICE\n"));
2407 ts->resp = SAS_TASK_UNDELIVERED;
2408 ts->stat = SAS_PHY_DOWN;
2409 break;
2410 case IO_XFER_ERROR_BREAK:
2411 PM8001_IO_DBG(pm8001_ha,
2412 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2413 ts->resp = SAS_TASK_COMPLETE;
2414 ts->stat = SAS_INTERRUPTED;
2415 break;
2416 case IO_XFER_ERROR_PHY_NOT_READY:
2417 PM8001_IO_DBG(pm8001_ha,
2418 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2419 ts->resp = SAS_TASK_COMPLETE;
2420 ts->stat = SAS_OPEN_REJECT;
2421 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2422 break;
2423 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2424 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2425 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2426 ts->resp = SAS_TASK_COMPLETE;
2427 ts->stat = SAS_OPEN_REJECT;
2428 ts->open_rej_reason = SAS_OREJ_EPROTO;
2429 break;
2430 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2431 PM8001_IO_DBG(pm8001_ha,
2432 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2433 ts->resp = SAS_TASK_COMPLETE;
2434 ts->stat = SAS_OPEN_REJECT;
2435 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2436 break;
2437 case IO_OPEN_CNX_ERROR_BREAK:
2438 PM8001_IO_DBG(pm8001_ha,
2439 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2440 ts->resp = SAS_TASK_COMPLETE;
2441 ts->stat = SAS_OPEN_REJECT;
2442 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2443 break;
2444 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2445 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2446 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2447 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2448 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2449 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2450 PM8001_IO_DBG(pm8001_ha,
2451 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2452 ts->resp = SAS_TASK_COMPLETE;
2453 ts->stat = SAS_DEV_NO_RESPONSE;
2454 if (!t->uldd_task) {
2455 pm8001_handle_event(pm8001_ha,
2456 pm8001_dev,
2457 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2458 ts->resp = SAS_TASK_UNDELIVERED;
2459 ts->stat = SAS_QUEUE_FULL;
2460 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2461 return;
2462 }
2463 break;
2464 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2465 PM8001_IO_DBG(pm8001_ha,
2466 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2467 ts->resp = SAS_TASK_UNDELIVERED;
2468 ts->stat = SAS_OPEN_REJECT;
2469 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2470 if (!t->uldd_task) {
2471 pm8001_handle_event(pm8001_ha,
2472 pm8001_dev,
2473 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2474 ts->resp = SAS_TASK_UNDELIVERED;
2475 ts->stat = SAS_QUEUE_FULL;
2476 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2477 return;
2478 }
2479 break;
2480 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2481 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2482 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2483 ts->resp = SAS_TASK_COMPLETE;
2484 ts->stat = SAS_OPEN_REJECT;
2485 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2486 break;
2487 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2488 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2489 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2490 ts->resp = SAS_TASK_COMPLETE;
2491 ts->stat = SAS_DEV_NO_RESPONSE;
2492 if (!t->uldd_task) {
2493 pm8001_handle_event(pm8001_ha,
2494 pm8001_dev,
2495 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2496 ts->resp = SAS_TASK_UNDELIVERED;
2497 ts->stat = SAS_QUEUE_FULL;
2498 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2499 return;
2500 }
2501 break;
2502 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2503 PM8001_IO_DBG(pm8001_ha,
2504 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2505 ts->resp = SAS_TASK_COMPLETE;
2506 ts->stat = SAS_OPEN_REJECT;
2507 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2508 break;
2509 case IO_XFER_ERROR_NAK_RECEIVED:
2510 PM8001_IO_DBG(pm8001_ha,
2511 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2512 ts->resp = SAS_TASK_COMPLETE;
2513 ts->stat = SAS_NAK_R_ERR;
2514 break;
2515 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2516 PM8001_IO_DBG(pm8001_ha,
2517 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2518 ts->resp = SAS_TASK_COMPLETE;
2519 ts->stat = SAS_NAK_R_ERR;
2520 break;
2521 case IO_XFER_ERROR_DMA:
2522 PM8001_IO_DBG(pm8001_ha,
2523 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2524 ts->resp = SAS_TASK_COMPLETE;
2525 ts->stat = SAS_ABORTED_TASK;
2526 break;
2527 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2528 PM8001_IO_DBG(pm8001_ha,
2529 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2530 ts->resp = SAS_TASK_UNDELIVERED;
2531 ts->stat = SAS_DEV_NO_RESPONSE;
2532 break;
2533 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2534 PM8001_IO_DBG(pm8001_ha,
2535 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2536 ts->resp = SAS_TASK_COMPLETE;
2537 ts->stat = SAS_DATA_UNDERRUN;
2538 break;
2539 case IO_XFER_OPEN_RETRY_TIMEOUT:
2540 PM8001_IO_DBG(pm8001_ha,
2541 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2542 ts->resp = SAS_TASK_COMPLETE;
2543 ts->stat = SAS_OPEN_TO;
2544 break;
2545 case IO_PORT_IN_RESET:
2546 PM8001_IO_DBG(pm8001_ha,
2547 pm8001_printk("IO_PORT_IN_RESET\n"));
2548 ts->resp = SAS_TASK_COMPLETE;
2549 ts->stat = SAS_DEV_NO_RESPONSE;
2550 break;
2551 case IO_DS_NON_OPERATIONAL:
2552 PM8001_IO_DBG(pm8001_ha,
2553 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2554 ts->resp = SAS_TASK_COMPLETE;
2555 ts->stat = SAS_DEV_NO_RESPONSE;
2556 if (!t->uldd_task) {
2557 pm8001_handle_event(pm8001_ha, pm8001_dev,
2558 IO_DS_NON_OPERATIONAL);
2559 ts->resp = SAS_TASK_UNDELIVERED;
2560 ts->stat = SAS_QUEUE_FULL;
2561 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2562 return;
2563 }
2564 break;
2565 case IO_DS_IN_RECOVERY:
2566 PM8001_IO_DBG(pm8001_ha,
2567 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2568 ts->resp = SAS_TASK_COMPLETE;
2569 ts->stat = SAS_DEV_NO_RESPONSE;
2570 break;
2571 case IO_DS_IN_ERROR:
2572 PM8001_IO_DBG(pm8001_ha,
2573 pm8001_printk("IO_DS_IN_ERROR\n"));
2574 ts->resp = SAS_TASK_COMPLETE;
2575 ts->stat = SAS_DEV_NO_RESPONSE;
2576 if (!t->uldd_task) {
2577 pm8001_handle_event(pm8001_ha, pm8001_dev,
2578 IO_DS_IN_ERROR);
2579 ts->resp = SAS_TASK_UNDELIVERED;
2580 ts->stat = SAS_QUEUE_FULL;
2581 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2582 return;
2583 }
2584 break;
2585 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2586 PM8001_IO_DBG(pm8001_ha,
2587 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2588 ts->resp = SAS_TASK_COMPLETE;
2589 ts->stat = SAS_OPEN_REJECT;
2590 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2591 break;
2592 default:
2593 PM8001_DEVIO_DBG(pm8001_ha,
2594 pm8001_printk("Unknown status 0x%x\n", status));
2595 /* not allowed case. Therefore, return failed status */
2596 ts->resp = SAS_TASK_COMPLETE;
2597 ts->stat = SAS_DEV_NO_RESPONSE;
2598 break;
2599 }
2600 spin_lock_irqsave(&t->task_state_lock, flags);
2601 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2602 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2603 t->task_state_flags |= SAS_TASK_STATE_DONE;
2604 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2605 spin_unlock_irqrestore(&t->task_state_lock, flags);
2606 PM8001_FAIL_DBG(pm8001_ha,
2607 pm8001_printk("task 0x%p done with io_status 0x%x"
2608 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2609 t, status, ts->resp, ts->stat));
2610 if (t->slow_task)
2611 complete(&t->slow_task->completion);
2612 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2613 } else {
2614 spin_unlock_irqrestore(&t->task_state_lock, flags);
2615 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2616 }
2617 }
2618
2619 /*See the comments for mpi_ssp_completion */
2620 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2621 {
2622 struct sas_task *t;
2623 struct task_status_struct *ts;
2624 struct pm8001_ccb_info *ccb;
2625 struct pm8001_device *pm8001_dev;
2626 struct sata_event_resp *psataPayload =
2627 (struct sata_event_resp *)(piomb + 4);
2628 u32 event = le32_to_cpu(psataPayload->event);
2629 u32 tag = le32_to_cpu(psataPayload->tag);
2630 u32 port_id = le32_to_cpu(psataPayload->port_id);
2631 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2632 unsigned long flags;
2633
2634 ccb = &pm8001_ha->ccb_info[tag];
2635
2636 if (ccb) {
2637 t = ccb->task;
2638 pm8001_dev = ccb->device;
2639 } else {
2640 PM8001_FAIL_DBG(pm8001_ha,
2641 pm8001_printk("No CCB !!!. returning\n"));
2642 return;
2643 }
2644 if (event)
2645 PM8001_FAIL_DBG(pm8001_ha,
2646 pm8001_printk("SATA EVENT 0x%x\n", event));
2647
2648 /* Check if this is NCQ error */
2649 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2650 /* find device using device id */
2651 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2652 /* send read log extension */
2653 if (pm8001_dev)
2654 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2655 return;
2656 }
2657
2658 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2659 PM8001_FAIL_DBG(pm8001_ha,
2660 pm8001_printk("task or dev null\n"));
2661 return;
2662 }
2663
2664 ts = &t->task_status;
2665 PM8001_IOERR_DBG(pm8001_ha,
2666 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2667 port_id, tag, event));
2668 switch (event) {
2669 case IO_OVERFLOW:
2670 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2671 ts->resp = SAS_TASK_COMPLETE;
2672 ts->stat = SAS_DATA_OVERRUN;
2673 ts->residual = 0;
2674 if (pm8001_dev)
2675 pm8001_dev->running_req--;
2676 break;
2677 case IO_XFER_ERROR_BREAK:
2678 PM8001_IO_DBG(pm8001_ha,
2679 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2680 ts->resp = SAS_TASK_COMPLETE;
2681 ts->stat = SAS_INTERRUPTED;
2682 break;
2683 case IO_XFER_ERROR_PHY_NOT_READY:
2684 PM8001_IO_DBG(pm8001_ha,
2685 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2686 ts->resp = SAS_TASK_COMPLETE;
2687 ts->stat = SAS_OPEN_REJECT;
2688 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2689 break;
2690 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2691 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2692 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2693 ts->resp = SAS_TASK_COMPLETE;
2694 ts->stat = SAS_OPEN_REJECT;
2695 ts->open_rej_reason = SAS_OREJ_EPROTO;
2696 break;
2697 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2698 PM8001_IO_DBG(pm8001_ha,
2699 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2700 ts->resp = SAS_TASK_COMPLETE;
2701 ts->stat = SAS_OPEN_REJECT;
2702 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2703 break;
2704 case IO_OPEN_CNX_ERROR_BREAK:
2705 PM8001_IO_DBG(pm8001_ha,
2706 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2707 ts->resp = SAS_TASK_COMPLETE;
2708 ts->stat = SAS_OPEN_REJECT;
2709 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2710 break;
2711 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2712 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2713 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2714 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2715 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2716 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2717 PM8001_FAIL_DBG(pm8001_ha,
2718 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2719 ts->resp = SAS_TASK_UNDELIVERED;
2720 ts->stat = SAS_DEV_NO_RESPONSE;
2721 if (!t->uldd_task) {
2722 pm8001_handle_event(pm8001_ha,
2723 pm8001_dev,
2724 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2725 ts->resp = SAS_TASK_COMPLETE;
2726 ts->stat = SAS_QUEUE_FULL;
2727 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2728 return;
2729 }
2730 break;
2731 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2732 PM8001_IO_DBG(pm8001_ha,
2733 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2734 ts->resp = SAS_TASK_UNDELIVERED;
2735 ts->stat = SAS_OPEN_REJECT;
2736 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2737 break;
2738 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2739 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2740 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2741 ts->resp = SAS_TASK_COMPLETE;
2742 ts->stat = SAS_OPEN_REJECT;
2743 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2744 break;
2745 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2746 PM8001_IO_DBG(pm8001_ha,
2747 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2748 ts->resp = SAS_TASK_COMPLETE;
2749 ts->stat = SAS_OPEN_REJECT;
2750 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2751 break;
2752 case IO_XFER_ERROR_NAK_RECEIVED:
2753 PM8001_IO_DBG(pm8001_ha,
2754 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2755 ts->resp = SAS_TASK_COMPLETE;
2756 ts->stat = SAS_NAK_R_ERR;
2757 break;
2758 case IO_XFER_ERROR_PEER_ABORTED:
2759 PM8001_IO_DBG(pm8001_ha,
2760 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2761 ts->resp = SAS_TASK_COMPLETE;
2762 ts->stat = SAS_NAK_R_ERR;
2763 break;
2764 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2765 PM8001_IO_DBG(pm8001_ha,
2766 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2767 ts->resp = SAS_TASK_COMPLETE;
2768 ts->stat = SAS_DATA_UNDERRUN;
2769 break;
2770 case IO_XFER_OPEN_RETRY_TIMEOUT:
2771 PM8001_IO_DBG(pm8001_ha,
2772 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2773 ts->resp = SAS_TASK_COMPLETE;
2774 ts->stat = SAS_OPEN_TO;
2775 break;
2776 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2777 PM8001_IO_DBG(pm8001_ha,
2778 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2779 ts->resp = SAS_TASK_COMPLETE;
2780 ts->stat = SAS_OPEN_TO;
2781 break;
2782 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2783 PM8001_IO_DBG(pm8001_ha,
2784 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2785 ts->resp = SAS_TASK_COMPLETE;
2786 ts->stat = SAS_OPEN_TO;
2787 break;
2788 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2789 PM8001_IO_DBG(pm8001_ha,
2790 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2791 ts->resp = SAS_TASK_COMPLETE;
2792 ts->stat = SAS_OPEN_TO;
2793 break;
2794 case IO_XFER_ERROR_OFFSET_MISMATCH:
2795 PM8001_IO_DBG(pm8001_ha,
2796 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2797 ts->resp = SAS_TASK_COMPLETE;
2798 ts->stat = SAS_OPEN_TO;
2799 break;
2800 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2801 PM8001_IO_DBG(pm8001_ha,
2802 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2803 ts->resp = SAS_TASK_COMPLETE;
2804 ts->stat = SAS_OPEN_TO;
2805 break;
2806 case IO_XFER_CMD_FRAME_ISSUED:
2807 PM8001_IO_DBG(pm8001_ha,
2808 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2809 break;
2810 case IO_XFER_PIO_SETUP_ERROR:
2811 PM8001_IO_DBG(pm8001_ha,
2812 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2813 ts->resp = SAS_TASK_COMPLETE;
2814 ts->stat = SAS_OPEN_TO;
2815 break;
2816 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2817 PM8001_FAIL_DBG(pm8001_ha,
2818 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2819 /* TBC: used default set values */
2820 ts->resp = SAS_TASK_COMPLETE;
2821 ts->stat = SAS_OPEN_TO;
2822 break;
2823 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2824 PM8001_FAIL_DBG(pm8001_ha,
2825 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2826 /* TBC: used default set values */
2827 ts->resp = SAS_TASK_COMPLETE;
2828 ts->stat = SAS_OPEN_TO;
2829 break;
2830 default:
2831 PM8001_IO_DBG(pm8001_ha,
2832 pm8001_printk("Unknown status 0x%x\n", event));
2833 /* not allowed case. Therefore, return failed status */
2834 ts->resp = SAS_TASK_COMPLETE;
2835 ts->stat = SAS_OPEN_TO;
2836 break;
2837 }
2838 spin_lock_irqsave(&t->task_state_lock, flags);
2839 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2840 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2841 t->task_state_flags |= SAS_TASK_STATE_DONE;
2842 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2843 spin_unlock_irqrestore(&t->task_state_lock, flags);
2844 PM8001_FAIL_DBG(pm8001_ha,
2845 pm8001_printk("task 0x%p done with io_status 0x%x"
2846 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2847 t, event, ts->resp, ts->stat));
2848 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2849 } else {
2850 spin_unlock_irqrestore(&t->task_state_lock, flags);
2851 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2852 }
2853 }
2854
2855 /*See the comments for mpi_ssp_completion */
2856 static void
2857 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2858 {
2859 u32 param, i;
2860 struct sas_task *t;
2861 struct pm8001_ccb_info *ccb;
2862 unsigned long flags;
2863 u32 status;
2864 u32 tag;
2865 struct smp_completion_resp *psmpPayload;
2866 struct task_status_struct *ts;
2867 struct pm8001_device *pm8001_dev;
2868 char *pdma_respaddr = NULL;
2869
2870 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2871 status = le32_to_cpu(psmpPayload->status);
2872 tag = le32_to_cpu(psmpPayload->tag);
2873
2874 ccb = &pm8001_ha->ccb_info[tag];
2875 param = le32_to_cpu(psmpPayload->param);
2876 t = ccb->task;
2877 ts = &t->task_status;
2878 pm8001_dev = ccb->device;
2879 if (status)
2880 PM8001_FAIL_DBG(pm8001_ha,
2881 pm8001_printk("smp IO status 0x%x\n", status));
2882 if (unlikely(!t || !t->lldd_task || !t->dev))
2883 return;
2884
2885 PM8001_DEV_DBG(pm8001_ha,
2886 pm8001_printk("tag::0x%x status::0x%x\n", tag, status));
2887
2888 switch (status) {
2889
2890 case IO_SUCCESS:
2891 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2892 ts->resp = SAS_TASK_COMPLETE;
2893 ts->stat = SAM_STAT_GOOD;
2894 if (pm8001_dev)
2895 pm8001_dev->running_req--;
2896 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2897 PM8001_IO_DBG(pm8001_ha,
2898 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2899 param));
2900 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2901 ((u64)sg_dma_address
2902 (&t->smp_task.smp_resp))));
2903 for (i = 0; i < param; i++) {
2904 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2905 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2906 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2907 i, *(pdma_respaddr+i),
2908 psmpPayload->_r_a[i]));
2909 }
2910 }
2911 break;
2912 case IO_ABORTED:
2913 PM8001_IO_DBG(pm8001_ha,
2914 pm8001_printk("IO_ABORTED IOMB\n"));
2915 ts->resp = SAS_TASK_COMPLETE;
2916 ts->stat = SAS_ABORTED_TASK;
2917 if (pm8001_dev)
2918 pm8001_dev->running_req--;
2919 break;
2920 case IO_OVERFLOW:
2921 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2922 ts->resp = SAS_TASK_COMPLETE;
2923 ts->stat = SAS_DATA_OVERRUN;
2924 ts->residual = 0;
2925 if (pm8001_dev)
2926 pm8001_dev->running_req--;
2927 break;
2928 case IO_NO_DEVICE:
2929 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2930 ts->resp = SAS_TASK_COMPLETE;
2931 ts->stat = SAS_PHY_DOWN;
2932 break;
2933 case IO_ERROR_HW_TIMEOUT:
2934 PM8001_IO_DBG(pm8001_ha,
2935 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2936 ts->resp = SAS_TASK_COMPLETE;
2937 ts->stat = SAM_STAT_BUSY;
2938 break;
2939 case IO_XFER_ERROR_BREAK:
2940 PM8001_IO_DBG(pm8001_ha,
2941 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2942 ts->resp = SAS_TASK_COMPLETE;
2943 ts->stat = SAM_STAT_BUSY;
2944 break;
2945 case IO_XFER_ERROR_PHY_NOT_READY:
2946 PM8001_IO_DBG(pm8001_ha,
2947 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2948 ts->resp = SAS_TASK_COMPLETE;
2949 ts->stat = SAM_STAT_BUSY;
2950 break;
2951 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2952 PM8001_IO_DBG(pm8001_ha,
2953 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2954 ts->resp = SAS_TASK_COMPLETE;
2955 ts->stat = SAS_OPEN_REJECT;
2956 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2957 break;
2958 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2959 PM8001_IO_DBG(pm8001_ha,
2960 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2961 ts->resp = SAS_TASK_COMPLETE;
2962 ts->stat = SAS_OPEN_REJECT;
2963 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2964 break;
2965 case IO_OPEN_CNX_ERROR_BREAK:
2966 PM8001_IO_DBG(pm8001_ha,
2967 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2968 ts->resp = SAS_TASK_COMPLETE;
2969 ts->stat = SAS_OPEN_REJECT;
2970 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2971 break;
2972 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2973 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2974 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2975 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2976 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2977 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2978 PM8001_IO_DBG(pm8001_ha,
2979 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2980 ts->resp = SAS_TASK_COMPLETE;
2981 ts->stat = SAS_OPEN_REJECT;
2982 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2983 pm8001_handle_event(pm8001_ha,
2984 pm8001_dev,
2985 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2986 break;
2987 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2988 PM8001_IO_DBG(pm8001_ha,
2989 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2990 ts->resp = SAS_TASK_COMPLETE;
2991 ts->stat = SAS_OPEN_REJECT;
2992 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2993 break;
2994 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2995 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2996 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2997 ts->resp = SAS_TASK_COMPLETE;
2998 ts->stat = SAS_OPEN_REJECT;
2999 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3000 break;
3001 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3002 PM8001_IO_DBG(pm8001_ha,
3003 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3004 ts->resp = SAS_TASK_COMPLETE;
3005 ts->stat = SAS_OPEN_REJECT;
3006 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3007 break;
3008 case IO_XFER_ERROR_RX_FRAME:
3009 PM8001_IO_DBG(pm8001_ha,
3010 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3011 ts->resp = SAS_TASK_COMPLETE;
3012 ts->stat = SAS_DEV_NO_RESPONSE;
3013 break;
3014 case IO_XFER_OPEN_RETRY_TIMEOUT:
3015 PM8001_IO_DBG(pm8001_ha,
3016 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3017 ts->resp = SAS_TASK_COMPLETE;
3018 ts->stat = SAS_OPEN_REJECT;
3019 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3020 break;
3021 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3022 PM8001_IO_DBG(pm8001_ha,
3023 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3024 ts->resp = SAS_TASK_COMPLETE;
3025 ts->stat = SAS_QUEUE_FULL;
3026 break;
3027 case IO_PORT_IN_RESET:
3028 PM8001_IO_DBG(pm8001_ha,
3029 pm8001_printk("IO_PORT_IN_RESET\n"));
3030 ts->resp = SAS_TASK_COMPLETE;
3031 ts->stat = SAS_OPEN_REJECT;
3032 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3033 break;
3034 case IO_DS_NON_OPERATIONAL:
3035 PM8001_IO_DBG(pm8001_ha,
3036 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3037 ts->resp = SAS_TASK_COMPLETE;
3038 ts->stat = SAS_DEV_NO_RESPONSE;
3039 break;
3040 case IO_DS_IN_RECOVERY:
3041 PM8001_IO_DBG(pm8001_ha,
3042 pm8001_printk("IO_DS_IN_RECOVERY\n"));
3043 ts->resp = SAS_TASK_COMPLETE;
3044 ts->stat = SAS_OPEN_REJECT;
3045 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3046 break;
3047 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3048 PM8001_IO_DBG(pm8001_ha,
3049 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3050 ts->resp = SAS_TASK_COMPLETE;
3051 ts->stat = SAS_OPEN_REJECT;
3052 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3053 break;
3054 default:
3055 PM8001_DEVIO_DBG(pm8001_ha,
3056 pm8001_printk("Unknown status 0x%x\n", status));
3057 ts->resp = SAS_TASK_COMPLETE;
3058 ts->stat = SAS_DEV_NO_RESPONSE;
3059 /* not allowed case. Therefore, return failed status */
3060 break;
3061 }
3062 spin_lock_irqsave(&t->task_state_lock, flags);
3063 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3064 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3065 t->task_state_flags |= SAS_TASK_STATE_DONE;
3066 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3067 spin_unlock_irqrestore(&t->task_state_lock, flags);
3068 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
3069 "task 0x%p done with io_status 0x%x resp 0x%x"
3070 "stat 0x%x but aborted by upper layer!\n",
3071 t, status, ts->resp, ts->stat));
3072 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3073 } else {
3074 spin_unlock_irqrestore(&t->task_state_lock, flags);
3075 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3076 mb();/* in order to force CPU ordering */
3077 t->task_done(t);
3078 }
3079 }
3080
3081 /**
3082 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3083 * @pm8001_ha: our hba card information
3084 * @Qnum: the outbound queue message number.
3085 * @SEA: source of event to ack
3086 * @port_id: port id.
3087 * @phyId: phy id.
3088 * @param0: parameter 0.
3089 * @param1: parameter 1.
3090 */
3091 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3092 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3093 {
3094 struct hw_event_ack_req payload;
3095 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3096
3097 struct inbound_queue_table *circularQ;
3098
3099 memset((u8 *)&payload, 0, sizeof(payload));
3100 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3101 payload.tag = cpu_to_le32(1);
3102 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3103 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3104 payload.param0 = cpu_to_le32(param0);
3105 payload.param1 = cpu_to_le32(param1);
3106 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3107 sizeof(payload), 0);
3108 }
3109
3110 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3111 u32 phyId, u32 phy_op);
3112
3113 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3114 void *piomb)
3115 {
3116 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3117 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3118 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3119 u32 lr_status_evt_portid =
3120 le32_to_cpu(pPayload->lr_status_evt_portid);
3121 u8 deviceType = pPayload->sas_identify.dev_type;
3122 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3123 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3124 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3125 struct pm8001_port *port = &pm8001_ha->port[port_id];
3126
3127 if (deviceType == SAS_END_DEVICE) {
3128 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3129 PHY_NOTIFY_ENABLE_SPINUP);
3130 }
3131
3132 port->wide_port_phymap |= (1U << phy_id);
3133 pm8001_get_lrate_mode(phy, link_rate);
3134 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3135 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3136 phy->phy_attached = 1;
3137 }
3138
3139 /**
3140 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3141 * @pm8001_ha: our hba card information
3142 * @piomb: IO message buffer
3143 */
3144 static void
3145 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3146 {
3147 struct hw_event_resp *pPayload =
3148 (struct hw_event_resp *)(piomb + 4);
3149 u32 lr_status_evt_portid =
3150 le32_to_cpu(pPayload->lr_status_evt_portid);
3151 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3152
3153 u8 link_rate =
3154 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3155 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3156 u8 phy_id =
3157 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3158 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3159
3160 struct pm8001_port *port = &pm8001_ha->port[port_id];
3161 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3162 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3163 unsigned long flags;
3164 u8 deviceType = pPayload->sas_identify.dev_type;
3165 port->port_state = portstate;
3166 port->wide_port_phymap |= (1U << phy_id);
3167 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3168 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3169 "portid:%d; phyid:%d; linkrate:%d; "
3170 "portstate:%x; devicetype:%x\n",
3171 port_id, phy_id, link_rate, portstate, deviceType));
3172
3173 switch (deviceType) {
3174 case SAS_PHY_UNUSED:
3175 PM8001_MSG_DBG(pm8001_ha,
3176 pm8001_printk("device type no device.\n"));
3177 break;
3178 case SAS_END_DEVICE:
3179 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3180 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3181 PHY_NOTIFY_ENABLE_SPINUP);
3182 port->port_attached = 1;
3183 pm8001_get_lrate_mode(phy, link_rate);
3184 break;
3185 case SAS_EDGE_EXPANDER_DEVICE:
3186 PM8001_MSG_DBG(pm8001_ha,
3187 pm8001_printk("expander device.\n"));
3188 port->port_attached = 1;
3189 pm8001_get_lrate_mode(phy, link_rate);
3190 break;
3191 case SAS_FANOUT_EXPANDER_DEVICE:
3192 PM8001_MSG_DBG(pm8001_ha,
3193 pm8001_printk("fanout expander device.\n"));
3194 port->port_attached = 1;
3195 pm8001_get_lrate_mode(phy, link_rate);
3196 break;
3197 default:
3198 PM8001_DEVIO_DBG(pm8001_ha,
3199 pm8001_printk("unknown device type(%x)\n", deviceType));
3200 break;
3201 }
3202 phy->phy_type |= PORT_TYPE_SAS;
3203 phy->identify.device_type = deviceType;
3204 phy->phy_attached = 1;
3205 if (phy->identify.device_type == SAS_END_DEVICE)
3206 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3207 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3208 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3209 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3210 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3211 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3212 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3213 sizeof(struct sas_identify_frame)-4);
3214 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3215 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3216 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3217 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3218 msleep(200);/*delay a moment to wait disk to spinup*/
3219 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3220 }
3221
3222 /**
3223 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3224 * @pm8001_ha: our hba card information
3225 * @piomb: IO message buffer
3226 */
3227 static void
3228 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3229 {
3230 struct hw_event_resp *pPayload =
3231 (struct hw_event_resp *)(piomb + 4);
3232 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3233 u32 lr_status_evt_portid =
3234 le32_to_cpu(pPayload->lr_status_evt_portid);
3235 u8 link_rate =
3236 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3237 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3238 u8 phy_id =
3239 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3240
3241 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3242
3243 struct pm8001_port *port = &pm8001_ha->port[port_id];
3244 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3245 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3246 unsigned long flags;
3247 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
3248 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3249 port_id, phy_id, link_rate, portstate));
3250
3251 port->port_state = portstate;
3252 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3253 port->port_attached = 1;
3254 pm8001_get_lrate_mode(phy, link_rate);
3255 phy->phy_type |= PORT_TYPE_SATA;
3256 phy->phy_attached = 1;
3257 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3258 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3259 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3260 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3261 sizeof(struct dev_to_host_fis));
3262 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3263 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3264 phy->identify.device_type = SAS_SATA_DEV;
3265 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3266 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3267 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3268 }
3269
3270 /**
3271 * hw_event_phy_down -we should notify the libsas the phy is down.
3272 * @pm8001_ha: our hba card information
3273 * @piomb: IO message buffer
3274 */
3275 static void
3276 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3277 {
3278 struct hw_event_resp *pPayload =
3279 (struct hw_event_resp *)(piomb + 4);
3280
3281 u32 lr_status_evt_portid =
3282 le32_to_cpu(pPayload->lr_status_evt_portid);
3283 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3284 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3285 u8 phy_id =
3286 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3287 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3288
3289 struct pm8001_port *port = &pm8001_ha->port[port_id];
3290 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3291 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3292 port->port_state = portstate;
3293 phy->identify.device_type = 0;
3294 phy->phy_attached = 0;
3295 switch (portstate) {
3296 case PORT_VALID:
3297 break;
3298 case PORT_INVALID:
3299 PM8001_MSG_DBG(pm8001_ha,
3300 pm8001_printk(" PortInvalid portID %d\n", port_id));
3301 PM8001_MSG_DBG(pm8001_ha,
3302 pm8001_printk(" Last phy Down and port invalid\n"));
3303 if (port_sata) {
3304 phy->phy_type = 0;
3305 port->port_attached = 0;
3306 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3307 port_id, phy_id, 0, 0);
3308 }
3309 sas_phy_disconnected(&phy->sas_phy);
3310 break;
3311 case PORT_IN_RESET:
3312 PM8001_MSG_DBG(pm8001_ha,
3313 pm8001_printk(" Port In Reset portID %d\n", port_id));
3314 break;
3315 case PORT_NOT_ESTABLISHED:
3316 PM8001_MSG_DBG(pm8001_ha,
3317 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3318 port->port_attached = 0;
3319 break;
3320 case PORT_LOSTCOMM:
3321 PM8001_MSG_DBG(pm8001_ha,
3322 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3323 PM8001_MSG_DBG(pm8001_ha,
3324 pm8001_printk(" Last phy Down and port invalid\n"));
3325 if (port_sata) {
3326 port->port_attached = 0;
3327 phy->phy_type = 0;
3328 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3329 port_id, phy_id, 0, 0);
3330 }
3331 sas_phy_disconnected(&phy->sas_phy);
3332 break;
3333 default:
3334 port->port_attached = 0;
3335 PM8001_DEVIO_DBG(pm8001_ha,
3336 pm8001_printk(" Phy Down and(default) = 0x%x\n",
3337 portstate));
3338 break;
3339
3340 }
3341 if (port_sata && (portstate != PORT_IN_RESET)) {
3342 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3343
3344 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3345 }
3346 }
3347
3348 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3349 {
3350 struct phy_start_resp *pPayload =
3351 (struct phy_start_resp *)(piomb + 4);
3352 u32 status =
3353 le32_to_cpu(pPayload->status);
3354 u32 phy_id =
3355 le32_to_cpu(pPayload->phyid);
3356 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3357
3358 PM8001_INIT_DBG(pm8001_ha,
3359 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3360 status, phy_id));
3361 if (status == 0) {
3362 phy->phy_state = PHY_LINK_DOWN;
3363 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3364 phy->enable_completion != NULL) {
3365 complete(phy->enable_completion);
3366 phy->enable_completion = NULL;
3367 }
3368 }
3369 return 0;
3370
3371 }
3372
3373 /**
3374 * mpi_thermal_hw_event -The hw event has come.
3375 * @pm8001_ha: our hba card information
3376 * @piomb: IO message buffer
3377 */
3378 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3379 {
3380 struct thermal_hw_event *pPayload =
3381 (struct thermal_hw_event *)(piomb + 4);
3382
3383 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3384 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3385
3386 if (thermal_event & 0x40) {
3387 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3388 "Thermal Event: Local high temperature violated!\n"));
3389 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3390 "Thermal Event: Measured local high temperature %d\n",
3391 ((rht_lht & 0xFF00) >> 8)));
3392 }
3393 if (thermal_event & 0x10) {
3394 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3395 "Thermal Event: Remote high temperature violated!\n"));
3396 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3397 "Thermal Event: Measured remote high temperature %d\n",
3398 ((rht_lht & 0xFF000000) >> 24)));
3399 }
3400 return 0;
3401 }
3402
3403 /**
3404 * mpi_hw_event -The hw event has come.
3405 * @pm8001_ha: our hba card information
3406 * @piomb: IO message buffer
3407 */
3408 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3409 {
3410 unsigned long flags, i;
3411 struct hw_event_resp *pPayload =
3412 (struct hw_event_resp *)(piomb + 4);
3413 u32 lr_status_evt_portid =
3414 le32_to_cpu(pPayload->lr_status_evt_portid);
3415 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3416 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3417 u8 phy_id =
3418 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3419 u16 eventType =
3420 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3421 u8 status =
3422 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3423 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3424 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3425 struct pm8001_port *port = &pm8001_ha->port[port_id];
3426 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3427 PM8001_DEV_DBG(pm8001_ha,
3428 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3429 port_id, phy_id, eventType, status));
3430
3431 switch (eventType) {
3432
3433 case HW_EVENT_SAS_PHY_UP:
3434 PM8001_MSG_DBG(pm8001_ha,
3435 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3436 hw_event_sas_phy_up(pm8001_ha, piomb);
3437 break;
3438 case HW_EVENT_SATA_PHY_UP:
3439 PM8001_MSG_DBG(pm8001_ha,
3440 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3441 hw_event_sata_phy_up(pm8001_ha, piomb);
3442 break;
3443 case HW_EVENT_SATA_SPINUP_HOLD:
3444 PM8001_MSG_DBG(pm8001_ha,
3445 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3446 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3447 break;
3448 case HW_EVENT_PHY_DOWN:
3449 PM8001_MSG_DBG(pm8001_ha,
3450 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3451 hw_event_phy_down(pm8001_ha, piomb);
3452 if (pm8001_ha->reset_in_progress) {
3453 PM8001_MSG_DBG(pm8001_ha,
3454 pm8001_printk("Reset in progress\n"));
3455 return 0;
3456 }
3457 phy->phy_attached = 0;
3458 phy->phy_state = PHY_LINK_DISABLE;
3459 break;
3460 case HW_EVENT_PORT_INVALID:
3461 PM8001_MSG_DBG(pm8001_ha,
3462 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3463 sas_phy_disconnected(sas_phy);
3464 phy->phy_attached = 0;
3465 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3466 break;
3467 /* the broadcast change primitive received, tell the LIBSAS this event
3468 to revalidate the sas domain*/
3469 case HW_EVENT_BROADCAST_CHANGE:
3470 PM8001_MSG_DBG(pm8001_ha,
3471 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3472 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3473 port_id, phy_id, 1, 0);
3474 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3475 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3476 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3477 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3478 break;
3479 case HW_EVENT_PHY_ERROR:
3480 PM8001_MSG_DBG(pm8001_ha,
3481 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3482 sas_phy_disconnected(&phy->sas_phy);
3483 phy->phy_attached = 0;
3484 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3485 break;
3486 case HW_EVENT_BROADCAST_EXP:
3487 PM8001_MSG_DBG(pm8001_ha,
3488 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3489 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3490 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3491 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3492 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3493 break;
3494 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3495 PM8001_MSG_DBG(pm8001_ha,
3496 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3497 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3498 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3499 break;
3500 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3501 PM8001_MSG_DBG(pm8001_ha,
3502 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3503 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3504 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3505 port_id, phy_id, 0, 0);
3506 break;
3507 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3508 PM8001_MSG_DBG(pm8001_ha,
3509 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3510 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3511 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3512 port_id, phy_id, 0, 0);
3513 break;
3514 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3515 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3516 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3517 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3518 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3519 port_id, phy_id, 0, 0);
3520 break;
3521 case HW_EVENT_MALFUNCTION:
3522 PM8001_MSG_DBG(pm8001_ha,
3523 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3524 break;
3525 case HW_EVENT_BROADCAST_SES:
3526 PM8001_MSG_DBG(pm8001_ha,
3527 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3528 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3529 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3530 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3531 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3532 break;
3533 case HW_EVENT_INBOUND_CRC_ERROR:
3534 PM8001_MSG_DBG(pm8001_ha,
3535 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3536 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3537 HW_EVENT_INBOUND_CRC_ERROR,
3538 port_id, phy_id, 0, 0);
3539 break;
3540 case HW_EVENT_HARD_RESET_RECEIVED:
3541 PM8001_MSG_DBG(pm8001_ha,
3542 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3543 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3544 break;
3545 case HW_EVENT_ID_FRAME_TIMEOUT:
3546 PM8001_MSG_DBG(pm8001_ha,
3547 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3548 sas_phy_disconnected(sas_phy);
3549 phy->phy_attached = 0;
3550 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3551 break;
3552 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3553 PM8001_MSG_DBG(pm8001_ha,
3554 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3555 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3556 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3557 port_id, phy_id, 0, 0);
3558 sas_phy_disconnected(sas_phy);
3559 phy->phy_attached = 0;
3560 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3561 break;
3562 case HW_EVENT_PORT_RESET_TIMER_TMO:
3563 PM8001_MSG_DBG(pm8001_ha,
3564 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3565 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3566 port_id, phy_id, 0, 0);
3567 sas_phy_disconnected(sas_phy);
3568 phy->phy_attached = 0;
3569 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3570 if (pm8001_ha->phy[phy_id].reset_completion) {
3571 pm8001_ha->phy[phy_id].port_reset_status =
3572 PORT_RESET_TMO;
3573 complete(pm8001_ha->phy[phy_id].reset_completion);
3574 pm8001_ha->phy[phy_id].reset_completion = NULL;
3575 }
3576 break;
3577 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3578 PM8001_MSG_DBG(pm8001_ha,
3579 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3580 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3581 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3582 port_id, phy_id, 0, 0);
3583 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3584 if (port->wide_port_phymap & (1 << i)) {
3585 phy = &pm8001_ha->phy[i];
3586 sas_ha->notify_phy_event(&phy->sas_phy,
3587 PHYE_LOSS_OF_SIGNAL);
3588 port->wide_port_phymap &= ~(1 << i);
3589 }
3590 }
3591 break;
3592 case HW_EVENT_PORT_RECOVER:
3593 PM8001_MSG_DBG(pm8001_ha,
3594 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3595 hw_event_port_recover(pm8001_ha, piomb);
3596 break;
3597 case HW_EVENT_PORT_RESET_COMPLETE:
3598 PM8001_MSG_DBG(pm8001_ha,
3599 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3600 if (pm8001_ha->phy[phy_id].reset_completion) {
3601 pm8001_ha->phy[phy_id].port_reset_status =
3602 PORT_RESET_SUCCESS;
3603 complete(pm8001_ha->phy[phy_id].reset_completion);
3604 pm8001_ha->phy[phy_id].reset_completion = NULL;
3605 }
3606 break;
3607 case EVENT_BROADCAST_ASYNCH_EVENT:
3608 PM8001_MSG_DBG(pm8001_ha,
3609 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3610 break;
3611 default:
3612 PM8001_DEVIO_DBG(pm8001_ha,
3613 pm8001_printk("Unknown event type 0x%x\n", eventType));
3614 break;
3615 }
3616 return 0;
3617 }
3618
3619 /**
3620 * mpi_phy_stop_resp - SPCv specific
3621 * @pm8001_ha: our hba card information
3622 * @piomb: IO message buffer
3623 */
3624 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3625 {
3626 struct phy_stop_resp *pPayload =
3627 (struct phy_stop_resp *)(piomb + 4);
3628 u32 status =
3629 le32_to_cpu(pPayload->status);
3630 u32 phyid =
3631 le32_to_cpu(pPayload->phyid) & 0xFF;
3632 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3633 PM8001_MSG_DBG(pm8001_ha,
3634 pm8001_printk("phy:0x%x status:0x%x\n",
3635 phyid, status));
3636 if (status == PHY_STOP_SUCCESS ||
3637 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3638 phy->phy_state = PHY_LINK_DISABLE;
3639 return 0;
3640 }
3641
3642 /**
3643 * mpi_set_controller_config_resp - SPCv specific
3644 * @pm8001_ha: our hba card information
3645 * @piomb: IO message buffer
3646 */
3647 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3648 void *piomb)
3649 {
3650 struct set_ctrl_cfg_resp *pPayload =
3651 (struct set_ctrl_cfg_resp *)(piomb + 4);
3652 u32 status = le32_to_cpu(pPayload->status);
3653 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3654
3655 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3656 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3657 status, err_qlfr_pgcd));
3658
3659 return 0;
3660 }
3661
3662 /**
3663 * mpi_get_controller_config_resp - SPCv specific
3664 * @pm8001_ha: our hba card information
3665 * @piomb: IO message buffer
3666 */
3667 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3668 void *piomb)
3669 {
3670 PM8001_MSG_DBG(pm8001_ha,
3671 pm8001_printk(" pm80xx_addition_functionality\n"));
3672
3673 return 0;
3674 }
3675
3676 /**
3677 * mpi_get_phy_profile_resp - SPCv specific
3678 * @pm8001_ha: our hba card information
3679 * @piomb: IO message buffer
3680 */
3681 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3682 void *piomb)
3683 {
3684 PM8001_MSG_DBG(pm8001_ha,
3685 pm8001_printk(" pm80xx_addition_functionality\n"));
3686
3687 return 0;
3688 }
3689
3690 /**
3691 * mpi_flash_op_ext_resp - SPCv specific
3692 * @pm8001_ha: our hba card information
3693 * @piomb: IO message buffer
3694 */
3695 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3696 {
3697 PM8001_MSG_DBG(pm8001_ha,
3698 pm8001_printk(" pm80xx_addition_functionality\n"));
3699
3700 return 0;
3701 }
3702
3703 /**
3704 * mpi_set_phy_profile_resp - SPCv specific
3705 * @pm8001_ha: our hba card information
3706 * @piomb: IO message buffer
3707 */
3708 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3709 void *piomb)
3710 {
3711 u8 page_code;
3712 struct set_phy_profile_resp *pPayload =
3713 (struct set_phy_profile_resp *)(piomb + 4);
3714 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3715 u32 status = le32_to_cpu(pPayload->status);
3716
3717 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3718 if (status) {
3719 /* status is FAILED */
3720 PM8001_FAIL_DBG(pm8001_ha,
3721 pm8001_printk("PhyProfile command failed with status "
3722 "0x%08X \n", status));
3723 return -1;
3724 } else {
3725 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3726 PM8001_FAIL_DBG(pm8001_ha,
3727 pm8001_printk("Invalid page code 0x%X\n",
3728 page_code));
3729 return -1;
3730 }
3731 }
3732 return 0;
3733 }
3734
3735 /**
3736 * mpi_kek_management_resp - SPCv specific
3737 * @pm8001_ha: our hba card information
3738 * @piomb: IO message buffer
3739 */
3740 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3741 void *piomb)
3742 {
3743 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3744
3745 u32 status = le32_to_cpu(pPayload->status);
3746 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3747 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3748
3749 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3750 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3751 status, kidx_new_curr_ksop, err_qlfr));
3752
3753 return 0;
3754 }
3755
3756 /**
3757 * mpi_dek_management_resp - SPCv specific
3758 * @pm8001_ha: our hba card information
3759 * @piomb: IO message buffer
3760 */
3761 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3762 void *piomb)
3763 {
3764 PM8001_MSG_DBG(pm8001_ha,
3765 pm8001_printk(" pm80xx_addition_functionality\n"));
3766
3767 return 0;
3768 }
3769
3770 /**
3771 * ssp_coalesced_comp_resp - SPCv specific
3772 * @pm8001_ha: our hba card information
3773 * @piomb: IO message buffer
3774 */
3775 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3776 void *piomb)
3777 {
3778 PM8001_MSG_DBG(pm8001_ha,
3779 pm8001_printk(" pm80xx_addition_functionality\n"));
3780
3781 return 0;
3782 }
3783
3784 /**
3785 * process_one_iomb - process one outbound Queue memory block
3786 * @pm8001_ha: our hba card information
3787 * @piomb: IO message buffer
3788 */
3789 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3790 {
3791 __le32 pHeader = *(__le32 *)piomb;
3792 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3793
3794 switch (opc) {
3795 case OPC_OUB_ECHO:
3796 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3797 break;
3798 case OPC_OUB_HW_EVENT:
3799 PM8001_MSG_DBG(pm8001_ha,
3800 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3801 mpi_hw_event(pm8001_ha, piomb);
3802 break;
3803 case OPC_OUB_THERM_HW_EVENT:
3804 PM8001_MSG_DBG(pm8001_ha,
3805 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3806 mpi_thermal_hw_event(pm8001_ha, piomb);
3807 break;
3808 case OPC_OUB_SSP_COMP:
3809 PM8001_MSG_DBG(pm8001_ha,
3810 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3811 mpi_ssp_completion(pm8001_ha, piomb);
3812 break;
3813 case OPC_OUB_SMP_COMP:
3814 PM8001_MSG_DBG(pm8001_ha,
3815 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3816 mpi_smp_completion(pm8001_ha, piomb);
3817 break;
3818 case OPC_OUB_LOCAL_PHY_CNTRL:
3819 PM8001_MSG_DBG(pm8001_ha,
3820 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3821 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3822 break;
3823 case OPC_OUB_DEV_REGIST:
3824 PM8001_MSG_DBG(pm8001_ha,
3825 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3826 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3827 break;
3828 case OPC_OUB_DEREG_DEV:
3829 PM8001_MSG_DBG(pm8001_ha,
3830 pm8001_printk("unregister the device\n"));
3831 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3832 break;
3833 case OPC_OUB_GET_DEV_HANDLE:
3834 PM8001_MSG_DBG(pm8001_ha,
3835 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3836 break;
3837 case OPC_OUB_SATA_COMP:
3838 PM8001_MSG_DBG(pm8001_ha,
3839 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3840 mpi_sata_completion(pm8001_ha, piomb);
3841 break;
3842 case OPC_OUB_SATA_EVENT:
3843 PM8001_MSG_DBG(pm8001_ha,
3844 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3845 mpi_sata_event(pm8001_ha, piomb);
3846 break;
3847 case OPC_OUB_SSP_EVENT:
3848 PM8001_MSG_DBG(pm8001_ha,
3849 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3850 mpi_ssp_event(pm8001_ha, piomb);
3851 break;
3852 case OPC_OUB_DEV_HANDLE_ARRIV:
3853 PM8001_MSG_DBG(pm8001_ha,
3854 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3855 /*This is for target*/
3856 break;
3857 case OPC_OUB_SSP_RECV_EVENT:
3858 PM8001_MSG_DBG(pm8001_ha,
3859 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3860 /*This is for target*/
3861 break;
3862 case OPC_OUB_FW_FLASH_UPDATE:
3863 PM8001_MSG_DBG(pm8001_ha,
3864 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3865 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3866 break;
3867 case OPC_OUB_GPIO_RESPONSE:
3868 PM8001_MSG_DBG(pm8001_ha,
3869 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3870 break;
3871 case OPC_OUB_GPIO_EVENT:
3872 PM8001_MSG_DBG(pm8001_ha,
3873 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3874 break;
3875 case OPC_OUB_GENERAL_EVENT:
3876 PM8001_MSG_DBG(pm8001_ha,
3877 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3878 pm8001_mpi_general_event(pm8001_ha, piomb);
3879 break;
3880 case OPC_OUB_SSP_ABORT_RSP:
3881 PM8001_MSG_DBG(pm8001_ha,
3882 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3883 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3884 break;
3885 case OPC_OUB_SATA_ABORT_RSP:
3886 PM8001_MSG_DBG(pm8001_ha,
3887 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3888 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3889 break;
3890 case OPC_OUB_SAS_DIAG_MODE_START_END:
3891 PM8001_MSG_DBG(pm8001_ha,
3892 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3893 break;
3894 case OPC_OUB_SAS_DIAG_EXECUTE:
3895 PM8001_MSG_DBG(pm8001_ha,
3896 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3897 break;
3898 case OPC_OUB_GET_TIME_STAMP:
3899 PM8001_MSG_DBG(pm8001_ha,
3900 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3901 break;
3902 case OPC_OUB_SAS_HW_EVENT_ACK:
3903 PM8001_MSG_DBG(pm8001_ha,
3904 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3905 break;
3906 case OPC_OUB_PORT_CONTROL:
3907 PM8001_MSG_DBG(pm8001_ha,
3908 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3909 break;
3910 case OPC_OUB_SMP_ABORT_RSP:
3911 PM8001_MSG_DBG(pm8001_ha,
3912 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3913 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3914 break;
3915 case OPC_OUB_GET_NVMD_DATA:
3916 PM8001_MSG_DBG(pm8001_ha,
3917 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3918 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3919 break;
3920 case OPC_OUB_SET_NVMD_DATA:
3921 PM8001_MSG_DBG(pm8001_ha,
3922 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3923 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3924 break;
3925 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3926 PM8001_MSG_DBG(pm8001_ha,
3927 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3928 break;
3929 case OPC_OUB_SET_DEVICE_STATE:
3930 PM8001_MSG_DBG(pm8001_ha,
3931 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3932 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3933 break;
3934 case OPC_OUB_GET_DEVICE_STATE:
3935 PM8001_MSG_DBG(pm8001_ha,
3936 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3937 break;
3938 case OPC_OUB_SET_DEV_INFO:
3939 PM8001_MSG_DBG(pm8001_ha,
3940 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3941 break;
3942 /* spcv specifc commands */
3943 case OPC_OUB_PHY_START_RESP:
3944 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3945 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3946 mpi_phy_start_resp(pm8001_ha, piomb);
3947 break;
3948 case OPC_OUB_PHY_STOP_RESP:
3949 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3950 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3951 mpi_phy_stop_resp(pm8001_ha, piomb);
3952 break;
3953 case OPC_OUB_SET_CONTROLLER_CONFIG:
3954 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3955 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3956 mpi_set_controller_config_resp(pm8001_ha, piomb);
3957 break;
3958 case OPC_OUB_GET_CONTROLLER_CONFIG:
3959 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3960 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3961 mpi_get_controller_config_resp(pm8001_ha, piomb);
3962 break;
3963 case OPC_OUB_GET_PHY_PROFILE:
3964 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3965 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3966 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3967 break;
3968 case OPC_OUB_FLASH_OP_EXT:
3969 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3970 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3971 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3972 break;
3973 case OPC_OUB_SET_PHY_PROFILE:
3974 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3975 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3976 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3977 break;
3978 case OPC_OUB_KEK_MANAGEMENT_RESP:
3979 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3980 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3981 mpi_kek_management_resp(pm8001_ha, piomb);
3982 break;
3983 case OPC_OUB_DEK_MANAGEMENT_RESP:
3984 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3985 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3986 mpi_dek_management_resp(pm8001_ha, piomb);
3987 break;
3988 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3989 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3990 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3991 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3992 break;
3993 default:
3994 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
3995 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3996 break;
3997 }
3998 }
3999
4000 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4001 {
4002 PM8001_FAIL_DBG(pm8001_ha,
4003 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
4004 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
4005 PM8001_FAIL_DBG(pm8001_ha,
4006 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
4007 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
4008 PM8001_FAIL_DBG(pm8001_ha,
4009 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
4010 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
4011 PM8001_FAIL_DBG(pm8001_ha,
4012 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
4013 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
4014 PM8001_FAIL_DBG(pm8001_ha,
4015 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4016 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
4017 PM8001_FAIL_DBG(pm8001_ha,
4018 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4019 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
4020 PM8001_FAIL_DBG(pm8001_ha,
4021 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4022 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
4023 PM8001_FAIL_DBG(pm8001_ha,
4024 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4025 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
4026 PM8001_FAIL_DBG(pm8001_ha,
4027 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4028 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
4029 PM8001_FAIL_DBG(pm8001_ha,
4030 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4031 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
4032 PM8001_FAIL_DBG(pm8001_ha,
4033 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4034 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
4035 PM8001_FAIL_DBG(pm8001_ha,
4036 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4037 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
4038 }
4039
4040 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4041 {
4042 struct outbound_queue_table *circularQ;
4043 void *pMsg1 = NULL;
4044 u8 uninitialized_var(bc);
4045 u32 ret = MPI_IO_STATUS_FAIL;
4046 unsigned long flags;
4047 u32 regval;
4048
4049 if (vec == (pm8001_ha->number_of_intr - 1)) {
4050 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4051 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
4052 SCRATCH_PAD_MIPSALL_READY) {
4053 pm8001_ha->controller_fatal_error = true;
4054 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
4055 "Firmware Fatal error! Regval:0x%x\n", regval));
4056 print_scratchpad_registers(pm8001_ha);
4057 return ret;
4058 }
4059 }
4060 spin_lock_irqsave(&pm8001_ha->lock, flags);
4061 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4062 do {
4063 /* spurious interrupt during setup if kexec-ing and
4064 * driver doing a doorbell access w/ the pre-kexec oq
4065 * interrupt setup.
4066 */
4067 if (!circularQ->pi_virt)
4068 break;
4069 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4070 if (MPI_IO_STATUS_SUCCESS == ret) {
4071 /* process the outbound message */
4072 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4073 /* free the message from the outbound circular buffer */
4074 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4075 circularQ, bc);
4076 }
4077 if (MPI_IO_STATUS_BUSY == ret) {
4078 /* Update the producer index from SPC */
4079 circularQ->producer_index =
4080 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4081 if (le32_to_cpu(circularQ->producer_index) ==
4082 circularQ->consumer_idx)
4083 /* OQ is empty */
4084 break;
4085 }
4086 } while (1);
4087 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4088 return ret;
4089 }
4090
4091 /* DMA_... to our direction translation. */
4092 static const u8 data_dir_flags[] = {
4093 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4094 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4095 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4096 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4097 };
4098
4099 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4100 struct smp_req *psmp_cmd, int mode, int length)
4101 {
4102 psmp_cmd->tag = hTag;
4103 psmp_cmd->device_id = cpu_to_le32(deviceID);
4104 if (mode == SMP_DIRECT) {
4105 length = length - 4; /* subtract crc */
4106 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4107 } else {
4108 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4109 }
4110 }
4111
4112 /**
4113 * pm8001_chip_smp_req - send a SMP task to FW
4114 * @pm8001_ha: our hba card information.
4115 * @ccb: the ccb information this request used.
4116 */
4117 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4118 struct pm8001_ccb_info *ccb)
4119 {
4120 int elem, rc;
4121 struct sas_task *task = ccb->task;
4122 struct domain_device *dev = task->dev;
4123 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4124 struct scatterlist *sg_req, *sg_resp;
4125 u32 req_len, resp_len;
4126 struct smp_req smp_cmd;
4127 u32 opc;
4128 struct inbound_queue_table *circularQ;
4129 char *preq_dma_addr = NULL;
4130 __le64 tmp_addr;
4131 u32 i, length;
4132
4133 memset(&smp_cmd, 0, sizeof(smp_cmd));
4134 /*
4135 * DMA-map SMP request, response buffers
4136 */
4137 sg_req = &task->smp_task.smp_req;
4138 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4139 if (!elem)
4140 return -ENOMEM;
4141 req_len = sg_dma_len(sg_req);
4142
4143 sg_resp = &task->smp_task.smp_resp;
4144 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4145 if (!elem) {
4146 rc = -ENOMEM;
4147 goto err_out;
4148 }
4149 resp_len = sg_dma_len(sg_resp);
4150 /* must be in dwords */
4151 if ((req_len & 0x3) || (resp_len & 0x3)) {
4152 rc = -EINVAL;
4153 goto err_out_2;
4154 }
4155
4156 opc = OPC_INB_SMP_REQUEST;
4157 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4158 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4159
4160 length = sg_req->length;
4161 PM8001_IO_DBG(pm8001_ha,
4162 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
4163 if (!(length - 8))
4164 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4165 else
4166 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4167
4168
4169 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4170 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
4171
4172 /* INDIRECT MODE command settings. Use DMA */
4173 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4174 PM8001_IO_DBG(pm8001_ha,
4175 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
4176 /* for SPCv indirect mode. Place the top 4 bytes of
4177 * SMP Request header here. */
4178 for (i = 0; i < 4; i++)
4179 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
4180 /* exclude top 4 bytes for SMP req header */
4181 smp_cmd.long_smp_req.long_req_addr =
4182 cpu_to_le64((u64)sg_dma_address
4183 (&task->smp_task.smp_req) + 4);
4184 /* exclude 4 bytes for SMP req header and CRC */
4185 smp_cmd.long_smp_req.long_req_size =
4186 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4187 smp_cmd.long_smp_req.long_resp_addr =
4188 cpu_to_le64((u64)sg_dma_address
4189 (&task->smp_task.smp_resp));
4190 smp_cmd.long_smp_req.long_resp_size =
4191 cpu_to_le32((u32)sg_dma_len
4192 (&task->smp_task.smp_resp)-4);
4193 } else { /* DIRECT MODE */
4194 smp_cmd.long_smp_req.long_req_addr =
4195 cpu_to_le64((u64)sg_dma_address
4196 (&task->smp_task.smp_req));
4197 smp_cmd.long_smp_req.long_req_size =
4198 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4199 smp_cmd.long_smp_req.long_resp_addr =
4200 cpu_to_le64((u64)sg_dma_address
4201 (&task->smp_task.smp_resp));
4202 smp_cmd.long_smp_req.long_resp_size =
4203 cpu_to_le32
4204 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4205 }
4206 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4207 PM8001_IO_DBG(pm8001_ha,
4208 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
4209 for (i = 0; i < length; i++)
4210 if (i < 16) {
4211 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
4212 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4213 "Byte[%d]:%x (DMA data:%x)\n",
4214 i, smp_cmd.smp_req16[i],
4215 *(preq_dma_addr)));
4216 } else {
4217 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
4218 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4219 "Byte[%d]:%x (DMA data:%x)\n",
4220 i, smp_cmd.smp_req[i],
4221 *(preq_dma_addr)));
4222 }
4223 }
4224
4225 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4226 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4227 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
4228 sizeof(smp_cmd), 0);
4229 if (rc)
4230 goto err_out_2;
4231 return 0;
4232
4233 err_out_2:
4234 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4235 DMA_FROM_DEVICE);
4236 err_out:
4237 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4238 DMA_TO_DEVICE);
4239 return rc;
4240 }
4241
4242 static int check_enc_sas_cmd(struct sas_task *task)
4243 {
4244 u8 cmd = task->ssp_task.cmd->cmnd[0];
4245
4246 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4247 return 1;
4248 else
4249 return 0;
4250 }
4251
4252 static int check_enc_sat_cmd(struct sas_task *task)
4253 {
4254 int ret = 0;
4255 switch (task->ata_task.fis.command) {
4256 case ATA_CMD_FPDMA_READ:
4257 case ATA_CMD_READ_EXT:
4258 case ATA_CMD_READ:
4259 case ATA_CMD_FPDMA_WRITE:
4260 case ATA_CMD_WRITE_EXT:
4261 case ATA_CMD_WRITE:
4262 case ATA_CMD_PIO_READ:
4263 case ATA_CMD_PIO_READ_EXT:
4264 case ATA_CMD_PIO_WRITE:
4265 case ATA_CMD_PIO_WRITE_EXT:
4266 ret = 1;
4267 break;
4268 default:
4269 ret = 0;
4270 break;
4271 }
4272 return ret;
4273 }
4274
4275 /**
4276 * pm80xx_chip_ssp_io_req - send a SSP task to FW
4277 * @pm8001_ha: our hba card information.
4278 * @ccb: the ccb information this request used.
4279 */
4280 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4281 struct pm8001_ccb_info *ccb)
4282 {
4283 struct sas_task *task = ccb->task;
4284 struct domain_device *dev = task->dev;
4285 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4286 struct ssp_ini_io_start_req ssp_cmd;
4287 u32 tag = ccb->ccb_tag;
4288 int ret;
4289 u64 phys_addr, start_addr, end_addr;
4290 u32 end_addr_high, end_addr_low;
4291 struct inbound_queue_table *circularQ;
4292 u32 q_index;
4293 u32 opc = OPC_INB_SSPINIIOSTART;
4294 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4295 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4296 /* data address domain added for spcv; set to 0 by host,
4297 * used internally by controller
4298 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4299 */
4300 ssp_cmd.dad_dir_m_tlr =
4301 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4302 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4303 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4304 ssp_cmd.tag = cpu_to_le32(tag);
4305 if (task->ssp_task.enable_first_burst)
4306 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4307 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4308 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4309 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4310 task->ssp_task.cmd->cmd_len);
4311 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4312 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4313
4314 /* Check if encryption is set */
4315 if (pm8001_ha->chip->encrypt &&
4316 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4317 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4318 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4319 task->ssp_task.cmd->cmnd[0]));
4320 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4321 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4322 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4323 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4324
4325 /* fill in PRD (scatter/gather) table, if any */
4326 if (task->num_scatter > 1) {
4327 pm8001_chip_make_sg(task->scatter,
4328 ccb->n_elem, ccb->buf_prd);
4329 phys_addr = ccb->ccb_dma_handle +
4330 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4331 ssp_cmd.enc_addr_low =
4332 cpu_to_le32(lower_32_bits(phys_addr));
4333 ssp_cmd.enc_addr_high =
4334 cpu_to_le32(upper_32_bits(phys_addr));
4335 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4336 } else if (task->num_scatter == 1) {
4337 u64 dma_addr = sg_dma_address(task->scatter);
4338 ssp_cmd.enc_addr_low =
4339 cpu_to_le32(lower_32_bits(dma_addr));
4340 ssp_cmd.enc_addr_high =
4341 cpu_to_le32(upper_32_bits(dma_addr));
4342 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4343 ssp_cmd.enc_esgl = 0;
4344 /* Check 4G Boundary */
4345 start_addr = cpu_to_le64(dma_addr);
4346 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4347 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4348 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4349 if (end_addr_high != ssp_cmd.enc_addr_high) {
4350 PM8001_FAIL_DBG(pm8001_ha,
4351 pm8001_printk("The sg list address "
4352 "start_addr=0x%016llx data_len=0x%x "
4353 "end_addr_high=0x%08x end_addr_low="
4354 "0x%08x has crossed 4G boundary\n",
4355 start_addr, ssp_cmd.enc_len,
4356 end_addr_high, end_addr_low));
4357 pm8001_chip_make_sg(task->scatter, 1,
4358 ccb->buf_prd);
4359 phys_addr = ccb->ccb_dma_handle +
4360 offsetof(struct pm8001_ccb_info,
4361 buf_prd[0]);
4362 ssp_cmd.enc_addr_low =
4363 cpu_to_le32(lower_32_bits(phys_addr));
4364 ssp_cmd.enc_addr_high =
4365 cpu_to_le32(upper_32_bits(phys_addr));
4366 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4367 }
4368 } else if (task->num_scatter == 0) {
4369 ssp_cmd.enc_addr_low = 0;
4370 ssp_cmd.enc_addr_high = 0;
4371 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4372 ssp_cmd.enc_esgl = 0;
4373 }
4374 /* XTS mode. All other fields are 0 */
4375 ssp_cmd.key_cmode = 0x6 << 4;
4376 /* set tweak values. Should be the start lba */
4377 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4378 (task->ssp_task.cmd->cmnd[3] << 16) |
4379 (task->ssp_task.cmd->cmnd[4] << 8) |
4380 (task->ssp_task.cmd->cmnd[5]));
4381 } else {
4382 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4383 "Sending Normal SAS command 0x%x inb q %x\n",
4384 task->ssp_task.cmd->cmnd[0], q_index));
4385 /* fill in PRD (scatter/gather) table, if any */
4386 if (task->num_scatter > 1) {
4387 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4388 ccb->buf_prd);
4389 phys_addr = ccb->ccb_dma_handle +
4390 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4391 ssp_cmd.addr_low =
4392 cpu_to_le32(lower_32_bits(phys_addr));
4393 ssp_cmd.addr_high =
4394 cpu_to_le32(upper_32_bits(phys_addr));
4395 ssp_cmd.esgl = cpu_to_le32(1<<31);
4396 } else if (task->num_scatter == 1) {
4397 u64 dma_addr = sg_dma_address(task->scatter);
4398 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4399 ssp_cmd.addr_high =
4400 cpu_to_le32(upper_32_bits(dma_addr));
4401 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4402 ssp_cmd.esgl = 0;
4403 /* Check 4G Boundary */
4404 start_addr = cpu_to_le64(dma_addr);
4405 end_addr = (start_addr + ssp_cmd.len) - 1;
4406 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4407 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4408 if (end_addr_high != ssp_cmd.addr_high) {
4409 PM8001_FAIL_DBG(pm8001_ha,
4410 pm8001_printk("The sg list address "
4411 "start_addr=0x%016llx data_len=0x%x "
4412 "end_addr_high=0x%08x end_addr_low="
4413 "0x%08x has crossed 4G boundary\n",
4414 start_addr, ssp_cmd.len,
4415 end_addr_high, end_addr_low));
4416 pm8001_chip_make_sg(task->scatter, 1,
4417 ccb->buf_prd);
4418 phys_addr = ccb->ccb_dma_handle +
4419 offsetof(struct pm8001_ccb_info,
4420 buf_prd[0]);
4421 ssp_cmd.addr_low =
4422 cpu_to_le32(lower_32_bits(phys_addr));
4423 ssp_cmd.addr_high =
4424 cpu_to_le32(upper_32_bits(phys_addr));
4425 ssp_cmd.esgl = cpu_to_le32(1<<31);
4426 }
4427 } else if (task->num_scatter == 0) {
4428 ssp_cmd.addr_low = 0;
4429 ssp_cmd.addr_high = 0;
4430 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4431 ssp_cmd.esgl = 0;
4432 }
4433 }
4434 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4435 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4436 &ssp_cmd, sizeof(ssp_cmd), q_index);
4437 return ret;
4438 }
4439
4440 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4441 struct pm8001_ccb_info *ccb)
4442 {
4443 struct sas_task *task = ccb->task;
4444 struct domain_device *dev = task->dev;
4445 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4446 u32 tag = ccb->ccb_tag;
4447 int ret;
4448 u32 q_index;
4449 struct sata_start_req sata_cmd;
4450 u32 hdr_tag, ncg_tag = 0;
4451 u64 phys_addr, start_addr, end_addr;
4452 u32 end_addr_high, end_addr_low;
4453 u32 ATAP = 0x0;
4454 u32 dir;
4455 struct inbound_queue_table *circularQ;
4456 unsigned long flags;
4457 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4458 memset(&sata_cmd, 0, sizeof(sata_cmd));
4459 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4460 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4461
4462 if (task->data_dir == DMA_NONE) {
4463 ATAP = 0x04; /* no data*/
4464 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4465 } else if (likely(!task->ata_task.device_control_reg_update)) {
4466 if (task->ata_task.dma_xfer) {
4467 ATAP = 0x06; /* DMA */
4468 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4469 } else {
4470 ATAP = 0x05; /* PIO*/
4471 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4472 }
4473 if (task->ata_task.use_ncq &&
4474 dev->sata_dev.class != ATA_DEV_ATAPI) {
4475 ATAP = 0x07; /* FPDMA */
4476 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4477 }
4478 }
4479 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4480 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4481 ncg_tag = hdr_tag;
4482 }
4483 dir = data_dir_flags[task->data_dir] << 8;
4484 sata_cmd.tag = cpu_to_le32(tag);
4485 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4486 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4487
4488 sata_cmd.sata_fis = task->ata_task.fis;
4489 if (likely(!task->ata_task.device_control_reg_update))
4490 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4491 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4492
4493 /* Check if encryption is set */
4494 if (pm8001_ha->chip->encrypt &&
4495 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4496 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4497 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4498 sata_cmd.sata_fis.command));
4499 opc = OPC_INB_SATA_DIF_ENC_IO;
4500
4501 /* set encryption bit */
4502 sata_cmd.ncqtag_atap_dir_m_dad =
4503 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4504 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4505 /* dad (bit 0-1) is 0 */
4506 /* fill in PRD (scatter/gather) table, if any */
4507 if (task->num_scatter > 1) {
4508 pm8001_chip_make_sg(task->scatter,
4509 ccb->n_elem, ccb->buf_prd);
4510 phys_addr = ccb->ccb_dma_handle +
4511 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4512 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4513 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4514 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4515 } else if (task->num_scatter == 1) {
4516 u64 dma_addr = sg_dma_address(task->scatter);
4517 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4518 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4519 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4520 sata_cmd.enc_esgl = 0;
4521 /* Check 4G Boundary */
4522 start_addr = cpu_to_le64(dma_addr);
4523 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4524 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4525 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4526 if (end_addr_high != sata_cmd.enc_addr_high) {
4527 PM8001_FAIL_DBG(pm8001_ha,
4528 pm8001_printk("The sg list address "
4529 "start_addr=0x%016llx data_len=0x%x "
4530 "end_addr_high=0x%08x end_addr_low"
4531 "=0x%08x has crossed 4G boundary\n",
4532 start_addr, sata_cmd.enc_len,
4533 end_addr_high, end_addr_low));
4534 pm8001_chip_make_sg(task->scatter, 1,
4535 ccb->buf_prd);
4536 phys_addr = ccb->ccb_dma_handle +
4537 offsetof(struct pm8001_ccb_info,
4538 buf_prd[0]);
4539 sata_cmd.enc_addr_low =
4540 lower_32_bits(phys_addr);
4541 sata_cmd.enc_addr_high =
4542 upper_32_bits(phys_addr);
4543 sata_cmd.enc_esgl =
4544 cpu_to_le32(1 << 31);
4545 }
4546 } else if (task->num_scatter == 0) {
4547 sata_cmd.enc_addr_low = 0;
4548 sata_cmd.enc_addr_high = 0;
4549 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4550 sata_cmd.enc_esgl = 0;
4551 }
4552 /* XTS mode. All other fields are 0 */
4553 sata_cmd.key_index_mode = 0x6 << 4;
4554 /* set tweak values. Should be the start lba */
4555 sata_cmd.twk_val0 =
4556 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4557 (sata_cmd.sata_fis.lbah << 16) |
4558 (sata_cmd.sata_fis.lbam << 8) |
4559 (sata_cmd.sata_fis.lbal));
4560 sata_cmd.twk_val1 =
4561 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4562 (sata_cmd.sata_fis.lbam_exp));
4563 } else {
4564 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4565 "Sending Normal SATA command 0x%x inb %x\n",
4566 sata_cmd.sata_fis.command, q_index));
4567 /* dad (bit 0-1) is 0 */
4568 sata_cmd.ncqtag_atap_dir_m_dad =
4569 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4570 ((ATAP & 0x3f) << 10) | dir);
4571
4572 /* fill in PRD (scatter/gather) table, if any */
4573 if (task->num_scatter > 1) {
4574 pm8001_chip_make_sg(task->scatter,
4575 ccb->n_elem, ccb->buf_prd);
4576 phys_addr = ccb->ccb_dma_handle +
4577 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4578 sata_cmd.addr_low = lower_32_bits(phys_addr);
4579 sata_cmd.addr_high = upper_32_bits(phys_addr);
4580 sata_cmd.esgl = cpu_to_le32(1 << 31);
4581 } else if (task->num_scatter == 1) {
4582 u64 dma_addr = sg_dma_address(task->scatter);
4583 sata_cmd.addr_low = lower_32_bits(dma_addr);
4584 sata_cmd.addr_high = upper_32_bits(dma_addr);
4585 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4586 sata_cmd.esgl = 0;
4587 /* Check 4G Boundary */
4588 start_addr = cpu_to_le64(dma_addr);
4589 end_addr = (start_addr + sata_cmd.len) - 1;
4590 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4591 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4592 if (end_addr_high != sata_cmd.addr_high) {
4593 PM8001_FAIL_DBG(pm8001_ha,
4594 pm8001_printk("The sg list address "
4595 "start_addr=0x%016llx data_len=0x%x"
4596 "end_addr_high=0x%08x end_addr_low="
4597 "0x%08x has crossed 4G boundary\n",
4598 start_addr, sata_cmd.len,
4599 end_addr_high, end_addr_low));
4600 pm8001_chip_make_sg(task->scatter, 1,
4601 ccb->buf_prd);
4602 phys_addr = ccb->ccb_dma_handle +
4603 offsetof(struct pm8001_ccb_info,
4604 buf_prd[0]);
4605 sata_cmd.addr_low =
4606 lower_32_bits(phys_addr);
4607 sata_cmd.addr_high =
4608 upper_32_bits(phys_addr);
4609 sata_cmd.esgl = cpu_to_le32(1 << 31);
4610 }
4611 } else if (task->num_scatter == 0) {
4612 sata_cmd.addr_low = 0;
4613 sata_cmd.addr_high = 0;
4614 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4615 sata_cmd.esgl = 0;
4616 }
4617 /* scsi cdb */
4618 sata_cmd.atapi_scsi_cdb[0] =
4619 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4620 (task->ata_task.atapi_packet[1] << 8) |
4621 (task->ata_task.atapi_packet[2] << 16) |
4622 (task->ata_task.atapi_packet[3] << 24)));
4623 sata_cmd.atapi_scsi_cdb[1] =
4624 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4625 (task->ata_task.atapi_packet[5] << 8) |
4626 (task->ata_task.atapi_packet[6] << 16) |
4627 (task->ata_task.atapi_packet[7] << 24)));
4628 sata_cmd.atapi_scsi_cdb[2] =
4629 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4630 (task->ata_task.atapi_packet[9] << 8) |
4631 (task->ata_task.atapi_packet[10] << 16) |
4632 (task->ata_task.atapi_packet[11] << 24)));
4633 sata_cmd.atapi_scsi_cdb[3] =
4634 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4635 (task->ata_task.atapi_packet[13] << 8) |
4636 (task->ata_task.atapi_packet[14] << 16) |
4637 (task->ata_task.atapi_packet[15] << 24)));
4638 }
4639
4640 /* Check for read log for failed drive and return */
4641 if (sata_cmd.sata_fis.command == 0x2f) {
4642 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4643 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4644 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4645 struct task_status_struct *ts;
4646
4647 pm8001_ha_dev->id &= 0xDFFFFFFF;
4648 ts = &task->task_status;
4649
4650 spin_lock_irqsave(&task->task_state_lock, flags);
4651 ts->resp = SAS_TASK_COMPLETE;
4652 ts->stat = SAM_STAT_GOOD;
4653 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4654 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4655 task->task_state_flags |= SAS_TASK_STATE_DONE;
4656 if (unlikely((task->task_state_flags &
4657 SAS_TASK_STATE_ABORTED))) {
4658 spin_unlock_irqrestore(&task->task_state_lock,
4659 flags);
4660 PM8001_FAIL_DBG(pm8001_ha,
4661 pm8001_printk("task 0x%p resp 0x%x "
4662 " stat 0x%x but aborted by upper layer "
4663 "\n", task, ts->resp, ts->stat));
4664 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4665 return 0;
4666 } else {
4667 spin_unlock_irqrestore(&task->task_state_lock,
4668 flags);
4669 pm8001_ccb_task_free_done(pm8001_ha, task,
4670 ccb, tag);
4671 return 0;
4672 }
4673 }
4674 }
4675 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4676 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4677 &sata_cmd, sizeof(sata_cmd), q_index);
4678 return ret;
4679 }
4680
4681 /**
4682 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4683 * @pm8001_ha: our hba card information.
4684 * @num: the inbound queue number
4685 * @phy_id: the phy id which we wanted to start up.
4686 */
4687 static int
4688 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4689 {
4690 struct phy_start_req payload;
4691 struct inbound_queue_table *circularQ;
4692 int ret;
4693 u32 tag = 0x01;
4694 u32 opcode = OPC_INB_PHYSTART;
4695 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4696 memset(&payload, 0, sizeof(payload));
4697 payload.tag = cpu_to_le32(tag);
4698
4699 PM8001_INIT_DBG(pm8001_ha,
4700 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4701
4702 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4703 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4704 /* SSC Disable and SAS Analog ST configuration */
4705 /**
4706 payload.ase_sh_lm_slr_phyid =
4707 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4708 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4709 phy_id);
4710 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4711 **/
4712
4713 payload.sas_identify.dev_type = SAS_END_DEVICE;
4714 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4715 memcpy(payload.sas_identify.sas_addr,
4716 &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4717 payload.sas_identify.phy_id = phy_id;
4718 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4719 sizeof(payload), 0);
4720 return ret;
4721 }
4722
4723 /**
4724 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4725 * @pm8001_ha: our hba card information.
4726 * @num: the inbound queue number
4727 * @phy_id: the phy id which we wanted to start up.
4728 */
4729 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4730 u8 phy_id)
4731 {
4732 struct phy_stop_req payload;
4733 struct inbound_queue_table *circularQ;
4734 int ret;
4735 u32 tag = 0x01;
4736 u32 opcode = OPC_INB_PHYSTOP;
4737 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4738 memset(&payload, 0, sizeof(payload));
4739 payload.tag = cpu_to_le32(tag);
4740 payload.phy_id = cpu_to_le32(phy_id);
4741 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4742 sizeof(payload), 0);
4743 return ret;
4744 }
4745
4746 /**
4747 * see comments on pm8001_mpi_reg_resp.
4748 */
4749 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4750 struct pm8001_device *pm8001_dev, u32 flag)
4751 {
4752 struct reg_dev_req payload;
4753 u32 opc;
4754 u32 stp_sspsmp_sata = 0x4;
4755 struct inbound_queue_table *circularQ;
4756 u32 linkrate, phy_id;
4757 int rc, tag = 0xdeadbeef;
4758 struct pm8001_ccb_info *ccb;
4759 u8 retryFlag = 0x1;
4760 u16 firstBurstSize = 0;
4761 u16 ITNT = 2000;
4762 struct domain_device *dev = pm8001_dev->sas_device;
4763 struct domain_device *parent_dev = dev->parent;
4764 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4765
4766 memset(&payload, 0, sizeof(payload));
4767 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4768 if (rc)
4769 return rc;
4770 ccb = &pm8001_ha->ccb_info[tag];
4771 ccb->device = pm8001_dev;
4772 ccb->ccb_tag = tag;
4773 payload.tag = cpu_to_le32(tag);
4774
4775 if (flag == 1) {
4776 stp_sspsmp_sata = 0x02; /*direct attached sata */
4777 } else {
4778 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4779 stp_sspsmp_sata = 0x00; /* stp*/
4780 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4781 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4782 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4783 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4784 }
4785 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4786 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4787 else
4788 phy_id = pm8001_dev->attached_phy;
4789
4790 opc = OPC_INB_REG_DEV;
4791
4792 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4793 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4794
4795 payload.phyid_portid =
4796 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4797 ((phy_id & 0xFF) << 8));
4798
4799 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4800 ((linkrate & 0x0F) << 24) |
4801 ((stp_sspsmp_sata & 0x03) << 28));
4802 payload.firstburstsize_ITNexustimeout =
4803 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4804
4805 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4806 SAS_ADDR_SIZE);
4807
4808 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4809 sizeof(payload), 0);
4810 if (rc)
4811 pm8001_tag_free(pm8001_ha, tag);
4812
4813 return rc;
4814 }
4815
4816 /**
4817 * pm80xx_chip_phy_ctl_req - support the local phy operation
4818 * @pm8001_ha: our hba card information.
4819 * @num: the inbound queue number
4820 * @phy_id: the phy id which we wanted to operate
4821 * @phy_op:
4822 */
4823 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4824 u32 phyId, u32 phy_op)
4825 {
4826 u32 tag;
4827 int rc;
4828 struct local_phy_ctl_req payload;
4829 struct inbound_queue_table *circularQ;
4830 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4831 memset(&payload, 0, sizeof(payload));
4832 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4833 if (rc)
4834 return rc;
4835 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4836 payload.tag = cpu_to_le32(tag);
4837 payload.phyop_phyid =
4838 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4839 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4840 sizeof(payload), 0);
4841 }
4842
4843 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4844 {
4845 #ifdef PM8001_USE_MSIX
4846 return 1;
4847 #else
4848 u32 value;
4849
4850 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4851 if (value)
4852 return 1;
4853 return 0;
4854 #endif
4855 }
4856
4857 /**
4858 * pm8001_chip_isr - PM8001 isr handler.
4859 * @pm8001_ha: our hba card information.
4860 * @irq: irq number.
4861 * @stat: stat.
4862 */
4863 static irqreturn_t
4864 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4865 {
4866 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4867 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
4868 "irq vec %d, ODMR:0x%x\n",
4869 vec, pm8001_cr32(pm8001_ha, 0, 0x30)));
4870 process_oq(pm8001_ha, vec);
4871 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4872 return IRQ_HANDLED;
4873 }
4874
4875 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4876 u32 operation, u32 phyid, u32 length, u32 *buf)
4877 {
4878 u32 tag , i, j = 0;
4879 int rc;
4880 struct set_phy_profile_req payload;
4881 struct inbound_queue_table *circularQ;
4882 u32 opc = OPC_INB_SET_PHY_PROFILE;
4883
4884 memset(&payload, 0, sizeof(payload));
4885 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4886 if (rc)
4887 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4888 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4889 payload.tag = cpu_to_le32(tag);
4890 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4891 PM8001_INIT_DBG(pm8001_ha,
4892 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4893 payload.ppc_phyid, length));
4894 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4895 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4896 j++;
4897 }
4898 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4899 sizeof(payload), 0);
4900 if (rc)
4901 pm8001_tag_free(pm8001_ha, tag);
4902 }
4903
4904 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4905 u32 length, u8 *buf)
4906 {
4907 u32 i;
4908
4909 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4910 mpi_set_phy_profile_req(pm8001_ha,
4911 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4912 length = length + PHY_DWORD_LENGTH;
4913 }
4914 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4915 }
4916
4917 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4918 u32 phy, u32 length, u32 *buf)
4919 {
4920 u32 tag, opc;
4921 int rc, i;
4922 struct set_phy_profile_req payload;
4923 struct inbound_queue_table *circularQ;
4924
4925 memset(&payload, 0, sizeof(payload));
4926
4927 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4928 if (rc)
4929 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
4930
4931 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4932 opc = OPC_INB_SET_PHY_PROFILE;
4933
4934 payload.tag = cpu_to_le32(tag);
4935 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4936 | (phy & 0xFF));
4937
4938 for (i = 0; i < length; i++)
4939 payload.reserved[i] = cpu_to_le32(*(buf + i));
4940
4941 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4942 sizeof(payload), 0);
4943 if (rc)
4944 pm8001_tag_free(pm8001_ha, tag);
4945
4946 PM8001_INIT_DBG(pm8001_ha,
4947 pm8001_printk("PHY %d settings applied", phy));
4948 }
4949 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4950 .name = "pmc80xx",
4951 .chip_init = pm80xx_chip_init,
4952 .chip_soft_rst = pm80xx_chip_soft_rst,
4953 .chip_rst = pm80xx_hw_chip_rst,
4954 .chip_iounmap = pm8001_chip_iounmap,
4955 .isr = pm80xx_chip_isr,
4956 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
4957 .isr_process_oq = process_oq,
4958 .interrupt_enable = pm80xx_chip_interrupt_enable,
4959 .interrupt_disable = pm80xx_chip_interrupt_disable,
4960 .make_prd = pm8001_chip_make_sg,
4961 .smp_req = pm80xx_chip_smp_req,
4962 .ssp_io_req = pm80xx_chip_ssp_io_req,
4963 .sata_req = pm80xx_chip_sata_req,
4964 .phy_start_req = pm80xx_chip_phy_start_req,
4965 .phy_stop_req = pm80xx_chip_phy_stop_req,
4966 .reg_dev_req = pm80xx_chip_reg_dev_req,
4967 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4968 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4969 .task_abort = pm8001_chip_abort_task,
4970 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4971 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4972 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4973 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4974 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4975 };
Linux with added FPC-III support