drivers/scsi/ufs/ufs-qcom.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #ifndef UFS_QCOM_H_
   6 #define UFS_QCOM_H_
   7
   8 #include <linux/reset-controller.h>
   9 #include <linux/reset.h>
  10
  11 #define MAX_UFS_QCOM_HOSTS      1
  12 #define MAX_U32                 (~(u32)0)
  13 #define MPHY_TX_FSM_STATE       0x41
  14 #define TX_FSM_HIBERN8          0x1
  15 #define HBRN8_POLL_TOUT_MS      100
  16 #define DEFAULT_CLK_RATE_HZ     1000000
  17 #define BUS_VECTOR_NAME_LEN     32
  18
  19 #define UFS_HW_VER_MAJOR_SHFT   (28)
  20 #define UFS_HW_VER_MAJOR_MASK   (0x000F << UFS_HW_VER_MAJOR_SHFT)
  21 #define UFS_HW_VER_MINOR_SHFT   (16)
  22 #define UFS_HW_VER_MINOR_MASK   (0x0FFF << UFS_HW_VER_MINOR_SHFT)
  23 #define UFS_HW_VER_STEP_SHFT    (0)
  24 #define UFS_HW_VER_STEP_MASK    (0xFFFF << UFS_HW_VER_STEP_SHFT)
  25
  26 /* vendor specific pre-defined parameters */
  27 #define SLOW 1
  28 #define FAST 2
  29
  30 #define UFS_QCOM_LIMIT_NUM_LANES_RX     2
  31 #define UFS_QCOM_LIMIT_NUM_LANES_TX     2
  32 #define UFS_QCOM_LIMIT_HSGEAR_RX        UFS_HS_G3
  33 #define UFS_QCOM_LIMIT_HSGEAR_TX        UFS_HS_G3
  34 #define UFS_QCOM_LIMIT_PWMGEAR_RX       UFS_PWM_G4
  35 #define UFS_QCOM_LIMIT_PWMGEAR_TX       UFS_PWM_G4
  36 #define UFS_QCOM_LIMIT_RX_PWR_PWM       SLOW_MODE
  37 #define UFS_QCOM_LIMIT_TX_PWR_PWM       SLOW_MODE
  38 #define UFS_QCOM_LIMIT_RX_PWR_HS        FAST_MODE
  39 #define UFS_QCOM_LIMIT_TX_PWR_HS        FAST_MODE
  40 #define UFS_QCOM_LIMIT_HS_RATE          PA_HS_MODE_B
  41 #define UFS_QCOM_LIMIT_DESIRED_MODE     FAST
  42
  43 /* QCOM UFS host controller vendor specific registers */
  44 enum {
  45         REG_UFS_SYS1CLK_1US                 = 0xC0,
  46         REG_UFS_TX_SYMBOL_CLK_NS_US         = 0xC4,
  47         REG_UFS_LOCAL_PORT_ID_REG           = 0xC8,
  48         REG_UFS_PA_ERR_CODE                 = 0xCC,
  49         REG_UFS_RETRY_TIMER_REG             = 0xD0,
  50         REG_UFS_PA_LINK_STARTUP_TIMER       = 0xD8,
  51         REG_UFS_CFG1                        = 0xDC,
  52         REG_UFS_CFG2                        = 0xE0,
  53         REG_UFS_HW_VERSION                  = 0xE4,
  54
  55         UFS_TEST_BUS                            = 0xE8,
  56         UFS_TEST_BUS_CTRL_0                     = 0xEC,
  57         UFS_TEST_BUS_CTRL_1                     = 0xF0,
  58         UFS_TEST_BUS_CTRL_2                     = 0xF4,
  59         UFS_UNIPRO_CFG                          = 0xF8,
  60
  61         /*
  62          * QCOM UFS host controller vendor specific registers
  63          * added in HW Version 3.0.0
  64          */
  65         UFS_AH8_CFG                             = 0xFC,
  66 };
  67
  68 /* QCOM UFS host controller vendor specific debug registers */
  69 enum {
  70         UFS_DBG_RD_REG_UAWM                     = 0x100,
  71         UFS_DBG_RD_REG_UARM                     = 0x200,
  72         UFS_DBG_RD_REG_TXUC                     = 0x300,
  73         UFS_DBG_RD_REG_RXUC                     = 0x400,
  74         UFS_DBG_RD_REG_DFC                      = 0x500,
  75         UFS_DBG_RD_REG_TRLUT                    = 0x600,
  76         UFS_DBG_RD_REG_TMRLUT                   = 0x700,
  77         UFS_UFS_DBG_RD_REG_OCSC                 = 0x800,
  78
  79         UFS_UFS_DBG_RD_DESC_RAM                 = 0x1500,
  80         UFS_UFS_DBG_RD_PRDT_RAM                 = 0x1700,
  81         UFS_UFS_DBG_RD_RESP_RAM                 = 0x1800,
  82         UFS_UFS_DBG_RD_EDTL_RAM                 = 0x1900,
  83 };
  84
  85 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x)      (0x000 + x)
  86 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)      (0x400 + x)
  87
  88 /* bit definitions for REG_UFS_CFG1 register */
  89 #define QUNIPRO_SEL             0x1
  90 #define UTP_DBG_RAMS_EN         0x20000
  91 #define TEST_BUS_EN             BIT(18)
  92 #define TEST_BUS_SEL            GENMASK(22, 19)
  93 #define UFS_REG_TEST_BUS_EN     BIT(30)
  94
  95 /* bit definitions for REG_UFS_CFG2 register */
  96 #define UAWM_HW_CGC_EN          (1 << 0)
  97 #define UARM_HW_CGC_EN          (1 << 1)
  98 #define TXUC_HW_CGC_EN          (1 << 2)
  99 #define RXUC_HW_CGC_EN          (1 << 3)
 100 #define DFC_HW_CGC_EN           (1 << 4)
 101 #define TRLUT_HW_CGC_EN         (1 << 5)
 102 #define TMRLUT_HW_CGC_EN        (1 << 6)
 103 #define OCSC_HW_CGC_EN          (1 << 7)
 104
 105 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
 106 #define TEST_BUS_SUB_SEL_MASK   0x1F  /* All XXX_SEL fields are 5 bits wide */
 107
 108 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
 109                                  TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
 110                                  DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
 111                                  TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
 112
 113 /* bit offset */
 114 enum {
 115         OFFSET_UFS_PHY_SOFT_RESET           = 1,
 116         OFFSET_CLK_NS_REG                   = 10,
 117 };
 118
 119 /* bit masks */
 120 enum {
 121         MASK_UFS_PHY_SOFT_RESET             = 0x2,
 122         MASK_TX_SYMBOL_CLK_1US_REG          = 0x3FF,
 123         MASK_CLK_NS_REG                     = 0xFFFC00,
 124 };
 125
 126 /* QCOM UFS debug print bit mask */
 127 #define UFS_QCOM_DBG_PRINT_REGS_EN      BIT(0)
 128 #define UFS_QCOM_DBG_PRINT_ICE_REGS_EN  BIT(1)
 129 #define UFS_QCOM_DBG_PRINT_TEST_BUS_EN  BIT(2)
 130
 131 #define UFS_QCOM_DBG_PRINT_ALL  \
 132         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
 133          UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
 134
 135 /* QUniPro Vendor specific attributes */
 136 #define PA_VS_CONFIG_REG1       0x9000
 137 #define DME_VS_CORE_CLK_CTRL    0xD002
 138 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
 139 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT                BIT(8)
 140 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK       0xFF
 141
 142 static inline void
 143 ufs_qcom_get_controller_revision(struct ufs_hba *hba,
 144                                  u8 *major, u16 *minor, u16 *step)
 145 {
 146         u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
 147
 148         *major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
 149         *minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
 150         *step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
 151 };
 152
 153 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
 154 {
 155         ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
 156                         1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
 157
 158         /*
 159          * Make sure assertion of ufs phy reset is written to
 160          * register before returning
 161          */
 162         mb();
 163 }
 164
 165 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
 166 {
 167         ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
 168                         0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
 169
 170         /*
 171          * Make sure de-assertion of ufs phy reset is written to
 172          * register before returning
 173          */
 174         mb();
 175 }
 176
 177 struct ufs_qcom_bus_vote {
 178         uint32_t client_handle;
 179         uint32_t curr_vote;
 180         int min_bw_vote;
 181         int max_bw_vote;
 182         int saved_vote;
 183         bool is_max_bw_needed;
 184         struct device_attribute max_bus_bw;
 185 };
 186
 187 /* Host controller hardware version: major.minor.step */
 188 struct ufs_hw_version {
 189         u16 step;
 190         u16 minor;
 191         u8 major;
 192 };
 193
 194 struct ufs_qcom_testbus {
 195         u8 select_major;
 196         u8 select_minor;
 197 };
 198
 199 struct gpio_desc;
 200
 201 struct ufs_qcom_host {
 202         /*
 203          * Set this capability if host controller supports the QUniPro mode
 204          * and if driver wants the Host controller to operate in QUniPro mode.
 205          * Note: By default this capability will be kept enabled if host
 206          * controller supports the QUniPro mode.
 207          */
 208         #define UFS_QCOM_CAP_QUNIPRO    0x1
 209
 210         /*
 211          * Set this capability if host controller can retain the secure
 212          * configuration even after UFS controller core power collapse.
 213          */
 214         #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE  0x2
 215         u32 caps;
 216
 217         struct phy *generic_phy;
 218         struct ufs_hba *hba;
 219         struct ufs_qcom_bus_vote bus_vote;
 220         struct ufs_pa_layer_attr dev_req_params;
 221         struct clk *rx_l0_sync_clk;
 222         struct clk *tx_l0_sync_clk;
 223         struct clk *rx_l1_sync_clk;
 224         struct clk *tx_l1_sync_clk;
 225         bool is_lane_clks_enabled;
 226
 227         void __iomem *dev_ref_clk_ctrl_mmio;
 228         bool is_dev_ref_clk_enabled;
 229         struct ufs_hw_version hw_ver;
 230
 231         u32 dev_ref_clk_en_mask;
 232
 233         /* Bitmask for enabling debug prints */
 234         u32 dbg_print_en;
 235         struct ufs_qcom_testbus testbus;
 236
 237         /* Reset control of HCI */
 238         struct reset_control *core_reset;
 239         struct reset_controller_dev rcdev;
 240
 241         struct gpio_desc *device_reset;
 242 };
 243
 244 static inline u32
 245 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
 246 {
 247         if (host->hw_ver.major <= 0x02)
 248                 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
 249
 250         return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
 251 };
 252
 253 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
 254 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
 255 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
 256
 257 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
 258
 259 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
 260 {
 261         if (host->caps & UFS_QCOM_CAP_QUNIPRO)
 262                 return true;
 263         else
 264                 return false;
 265 }
 266
 267 #endif /* UFS_QCOM_H_ */