1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * UFS Host driver for Synopsys Designware Core
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
7 * Authors: Joao Pinto <jpinto@synopsys.com>
13 /* DWC HC UFSHCI specific Registers */
14 enum dwc_specific_registers
{
15 DWC_UFS_REG_HCLKDIV
= 0xFC,
18 /* Clock Divider Values: Hex equivalent of frequency in MHz */
20 DWC_UFS_REG_HCLKDIV_DIV_62_5
= 0x3e,
21 DWC_UFS_REG_HCLKDIV_DIV_125
= 0x7d,
22 DWC_UFS_REG_HCLKDIV_DIV_200
= 0xc8,
33 #endif /* End of Header */