1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
5 * Authors: Shlomi Gridish <gridish@freescale.com>
6 * Li Yang <leoli@freescale.com>
9 * QE UCC Fast API Set - UCC Fast specific routines implementations.
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/slab.h>
14 #include <linux/stddef.h>
15 #include <linux/interrupt.h>
16 #include <linux/err.h>
17 #include <linux/export.h>
20 #include <soc/fsl/qe/immap_qe.h>
21 #include <soc/fsl/qe/qe.h>
23 #include <soc/fsl/qe/ucc.h>
24 #include <soc/fsl/qe/ucc_fast.h>
26 void ucc_fast_dump_regs(struct ucc_fast_private
* uccf
)
28 printk(KERN_INFO
"UCC%u Fast registers:\n", uccf
->uf_info
->ucc_num
);
29 printk(KERN_INFO
"Base address: 0x%p\n", uccf
->uf_regs
);
31 printk(KERN_INFO
"gumr : addr=0x%p, val=0x%08x\n",
32 &uccf
->uf_regs
->gumr
, in_be32(&uccf
->uf_regs
->gumr
));
33 printk(KERN_INFO
"upsmr : addr=0x%p, val=0x%08x\n",
34 &uccf
->uf_regs
->upsmr
, in_be32(&uccf
->uf_regs
->upsmr
));
35 printk(KERN_INFO
"utodr : addr=0x%p, val=0x%04x\n",
36 &uccf
->uf_regs
->utodr
, in_be16(&uccf
->uf_regs
->utodr
));
37 printk(KERN_INFO
"udsr : addr=0x%p, val=0x%04x\n",
38 &uccf
->uf_regs
->udsr
, in_be16(&uccf
->uf_regs
->udsr
));
39 printk(KERN_INFO
"ucce : addr=0x%p, val=0x%08x\n",
40 &uccf
->uf_regs
->ucce
, in_be32(&uccf
->uf_regs
->ucce
));
41 printk(KERN_INFO
"uccm : addr=0x%p, val=0x%08x\n",
42 &uccf
->uf_regs
->uccm
, in_be32(&uccf
->uf_regs
->uccm
));
43 printk(KERN_INFO
"uccs : addr=0x%p, val=0x%02x\n",
44 &uccf
->uf_regs
->uccs
, in_8(&uccf
->uf_regs
->uccs
));
45 printk(KERN_INFO
"urfb : addr=0x%p, val=0x%08x\n",
46 &uccf
->uf_regs
->urfb
, in_be32(&uccf
->uf_regs
->urfb
));
47 printk(KERN_INFO
"urfs : addr=0x%p, val=0x%04x\n",
48 &uccf
->uf_regs
->urfs
, in_be16(&uccf
->uf_regs
->urfs
));
49 printk(KERN_INFO
"urfet : addr=0x%p, val=0x%04x\n",
50 &uccf
->uf_regs
->urfet
, in_be16(&uccf
->uf_regs
->urfet
));
51 printk(KERN_INFO
"urfset: addr=0x%p, val=0x%04x\n",
52 &uccf
->uf_regs
->urfset
, in_be16(&uccf
->uf_regs
->urfset
));
53 printk(KERN_INFO
"utfb : addr=0x%p, val=0x%08x\n",
54 &uccf
->uf_regs
->utfb
, in_be32(&uccf
->uf_regs
->utfb
));
55 printk(KERN_INFO
"utfs : addr=0x%p, val=0x%04x\n",
56 &uccf
->uf_regs
->utfs
, in_be16(&uccf
->uf_regs
->utfs
));
57 printk(KERN_INFO
"utfet : addr=0x%p, val=0x%04x\n",
58 &uccf
->uf_regs
->utfet
, in_be16(&uccf
->uf_regs
->utfet
));
59 printk(KERN_INFO
"utftt : addr=0x%p, val=0x%04x\n",
60 &uccf
->uf_regs
->utftt
, in_be16(&uccf
->uf_regs
->utftt
));
61 printk(KERN_INFO
"utpt : addr=0x%p, val=0x%04x\n",
62 &uccf
->uf_regs
->utpt
, in_be16(&uccf
->uf_regs
->utpt
));
63 printk(KERN_INFO
"urtry : addr=0x%p, val=0x%08x\n",
64 &uccf
->uf_regs
->urtry
, in_be32(&uccf
->uf_regs
->urtry
));
65 printk(KERN_INFO
"guemr : addr=0x%p, val=0x%02x\n",
66 &uccf
->uf_regs
->guemr
, in_8(&uccf
->uf_regs
->guemr
));
68 EXPORT_SYMBOL(ucc_fast_dump_regs
);
70 u32
ucc_fast_get_qe_cr_subblock(int uccf_num
)
73 case 0: return QE_CR_SUBBLOCK_UCCFAST1
;
74 case 1: return QE_CR_SUBBLOCK_UCCFAST2
;
75 case 2: return QE_CR_SUBBLOCK_UCCFAST3
;
76 case 3: return QE_CR_SUBBLOCK_UCCFAST4
;
77 case 4: return QE_CR_SUBBLOCK_UCCFAST5
;
78 case 5: return QE_CR_SUBBLOCK_UCCFAST6
;
79 case 6: return QE_CR_SUBBLOCK_UCCFAST7
;
80 case 7: return QE_CR_SUBBLOCK_UCCFAST8
;
81 default: return QE_CR_SUBBLOCK_INVALID
;
84 EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock
);
86 void ucc_fast_transmit_on_demand(struct ucc_fast_private
* uccf
)
88 out_be16(&uccf
->uf_regs
->utodr
, UCC_FAST_TOD
);
90 EXPORT_SYMBOL(ucc_fast_transmit_on_demand
);
92 void ucc_fast_enable(struct ucc_fast_private
* uccf
, enum comm_dir mode
)
94 struct ucc_fast __iomem
*uf_regs
;
97 uf_regs
= uccf
->uf_regs
;
99 /* Enable reception and/or transmission on this UCC. */
100 gumr
= in_be32(&uf_regs
->gumr
);
101 if (mode
& COMM_DIR_TX
) {
102 gumr
|= UCC_FAST_GUMR_ENT
;
103 uccf
->enabled_tx
= 1;
105 if (mode
& COMM_DIR_RX
) {
106 gumr
|= UCC_FAST_GUMR_ENR
;
107 uccf
->enabled_rx
= 1;
109 out_be32(&uf_regs
->gumr
, gumr
);
111 EXPORT_SYMBOL(ucc_fast_enable
);
113 void ucc_fast_disable(struct ucc_fast_private
* uccf
, enum comm_dir mode
)
115 struct ucc_fast __iomem
*uf_regs
;
118 uf_regs
= uccf
->uf_regs
;
120 /* Disable reception and/or transmission on this UCC. */
121 gumr
= in_be32(&uf_regs
->gumr
);
122 if (mode
& COMM_DIR_TX
) {
123 gumr
&= ~UCC_FAST_GUMR_ENT
;
124 uccf
->enabled_tx
= 0;
126 if (mode
& COMM_DIR_RX
) {
127 gumr
&= ~UCC_FAST_GUMR_ENR
;
128 uccf
->enabled_rx
= 0;
130 out_be32(&uf_regs
->gumr
, gumr
);
132 EXPORT_SYMBOL(ucc_fast_disable
);
134 int ucc_fast_init(struct ucc_fast_info
* uf_info
, struct ucc_fast_private
** uccf_ret
)
136 struct ucc_fast_private
*uccf
;
137 struct ucc_fast __iomem
*uf_regs
;
144 /* check if the UCC port number is in range. */
145 if ((uf_info
->ucc_num
< 0) || (uf_info
->ucc_num
> UCC_MAX_NUM
- 1)) {
146 printk(KERN_ERR
"%s: illegal UCC number\n", __func__
);
150 /* Check that 'max_rx_buf_length' is properly aligned (4). */
151 if (uf_info
->max_rx_buf_length
& (UCC_FAST_MRBLR_ALIGNMENT
- 1)) {
152 printk(KERN_ERR
"%s: max_rx_buf_length not aligned\n",
157 /* Validate Virtual Fifo register values */
158 if (uf_info
->urfs
< UCC_FAST_URFS_MIN_VAL
) {
159 printk(KERN_ERR
"%s: urfs is too small\n", __func__
);
163 if (uf_info
->urfs
& (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT
- 1)) {
164 printk(KERN_ERR
"%s: urfs is not aligned\n", __func__
);
168 if (uf_info
->urfet
& (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT
- 1)) {
169 printk(KERN_ERR
"%s: urfet is not aligned.\n", __func__
);
173 if (uf_info
->urfset
& (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT
- 1)) {
174 printk(KERN_ERR
"%s: urfset is not aligned\n", __func__
);
178 if (uf_info
->utfs
& (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT
- 1)) {
179 printk(KERN_ERR
"%s: utfs is not aligned\n", __func__
);
183 if (uf_info
->utfet
& (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT
- 1)) {
184 printk(KERN_ERR
"%s: utfet is not aligned\n", __func__
);
188 if (uf_info
->utftt
& (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT
- 1)) {
189 printk(KERN_ERR
"%s: utftt is not aligned\n", __func__
);
193 uccf
= kzalloc(sizeof(struct ucc_fast_private
), GFP_KERNEL
);
195 printk(KERN_ERR
"%s: Cannot allocate private data\n",
200 /* Fill fast UCC structure */
201 uccf
->uf_info
= uf_info
;
202 /* Set the PHY base address */
203 uccf
->uf_regs
= ioremap(uf_info
->regs
, sizeof(struct ucc_fast
));
204 if (uccf
->uf_regs
== NULL
) {
205 printk(KERN_ERR
"%s: Cannot map UCC registers\n", __func__
);
210 uccf
->enabled_tx
= 0;
211 uccf
->enabled_rx
= 0;
212 uccf
->stopped_tx
= 0;
213 uccf
->stopped_rx
= 0;
214 uf_regs
= uccf
->uf_regs
;
215 uccf
->p_ucce
= &uf_regs
->ucce
;
216 uccf
->p_uccm
= &uf_regs
->uccm
;
217 #ifdef CONFIG_UGETH_TX_ON_DEMAND
218 uccf
->p_utodr
= &uf_regs
->utodr
;
223 uccf
->rx_discarded
= 0;
224 #endif /* STATISTICS */
226 /* Set UCC to fast type */
227 ret
= ucc_set_type(uf_info
->ucc_num
, UCC_SPEED_TYPE_FAST
);
229 printk(KERN_ERR
"%s: cannot set UCC type\n", __func__
);
234 uccf
->mrblr
= uf_info
->max_rx_buf_length
;
237 /* For more details see the hardware spec. */
238 gumr
= uf_info
->ttx_trx
;
240 gumr
|= UCC_FAST_GUMR_TCI
;
242 gumr
|= UCC_FAST_GUMR_CDP
;
244 gumr
|= UCC_FAST_GUMR_CTSP
;
246 gumr
|= UCC_FAST_GUMR_CDS
;
248 gumr
|= UCC_FAST_GUMR_CTSS
;
250 gumr
|= UCC_FAST_GUMR_TXSY
;
252 gumr
|= UCC_FAST_GUMR_RSYN
;
253 gumr
|= uf_info
->synl
;
255 gumr
|= UCC_FAST_GUMR_RTSM
;
256 gumr
|= uf_info
->renc
;
258 gumr
|= UCC_FAST_GUMR_REVD
;
259 gumr
|= uf_info
->tenc
;
260 gumr
|= uf_info
->tcrc
;
261 gumr
|= uf_info
->mode
;
262 out_be32(&uf_regs
->gumr
, gumr
);
264 /* Allocate memory for Tx Virtual Fifo */
265 uccf
->ucc_fast_tx_virtual_fifo_base_offset
=
266 qe_muram_alloc(uf_info
->utfs
, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT
);
267 if (IS_ERR_VALUE(uccf
->ucc_fast_tx_virtual_fifo_base_offset
)) {
268 printk(KERN_ERR
"%s: cannot allocate MURAM for TX FIFO\n",
270 uccf
->ucc_fast_tx_virtual_fifo_base_offset
= 0;
275 /* Allocate memory for Rx Virtual Fifo */
276 uccf
->ucc_fast_rx_virtual_fifo_base_offset
=
277 qe_muram_alloc(uf_info
->urfs
+
278 UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR
,
279 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT
);
280 if (IS_ERR_VALUE(uccf
->ucc_fast_rx_virtual_fifo_base_offset
)) {
281 printk(KERN_ERR
"%s: cannot allocate MURAM for RX FIFO\n",
283 uccf
->ucc_fast_rx_virtual_fifo_base_offset
= 0;
288 /* Set Virtual Fifo registers */
289 out_be16(&uf_regs
->urfs
, uf_info
->urfs
);
290 out_be16(&uf_regs
->urfet
, uf_info
->urfet
);
291 out_be16(&uf_regs
->urfset
, uf_info
->urfset
);
292 out_be16(&uf_regs
->utfs
, uf_info
->utfs
);
293 out_be16(&uf_regs
->utfet
, uf_info
->utfet
);
294 out_be16(&uf_regs
->utftt
, uf_info
->utftt
);
295 /* utfb, urfb are offsets from MURAM base */
296 out_be32(&uf_regs
->utfb
, uccf
->ucc_fast_tx_virtual_fifo_base_offset
);
297 out_be32(&uf_regs
->urfb
, uccf
->ucc_fast_rx_virtual_fifo_base_offset
);
301 ucc_set_qe_mux_grant(uf_info
->ucc_num
, uf_info
->grant_support
);
302 /* Breakpoint Support */
303 ucc_set_qe_mux_bkpt(uf_info
->ucc_num
, uf_info
->brkpt_support
);
304 /* Set Tsa or NMSI mode. */
305 ucc_set_qe_mux_tsa(uf_info
->ucc_num
, uf_info
->tsa
);
306 /* If NMSI (not Tsa), set Tx and Rx clock. */
308 /* Rx clock routing */
309 if ((uf_info
->rx_clock
!= QE_CLK_NONE
) &&
310 ucc_set_qe_mux_rxtx(uf_info
->ucc_num
, uf_info
->rx_clock
,
312 printk(KERN_ERR
"%s: illegal value for RX clock\n",
317 /* Tx clock routing */
318 if ((uf_info
->tx_clock
!= QE_CLK_NONE
) &&
319 ucc_set_qe_mux_rxtx(uf_info
->ucc_num
, uf_info
->tx_clock
,
321 printk(KERN_ERR
"%s: illegal value for TX clock\n",
327 /* tdm Rx clock routing */
328 if ((uf_info
->rx_clock
!= QE_CLK_NONE
) &&
329 ucc_set_tdm_rxtx_clk(uf_info
->tdm_num
, uf_info
->rx_clock
,
331 pr_err("%s: illegal value for RX clock", __func__
);
336 /* tdm Tx clock routing */
337 if ((uf_info
->tx_clock
!= QE_CLK_NONE
) &&
338 ucc_set_tdm_rxtx_clk(uf_info
->tdm_num
, uf_info
->tx_clock
,
340 pr_err("%s: illegal value for TX clock", __func__
);
345 /* tdm Rx sync clock routing */
346 if ((uf_info
->rx_sync
!= QE_CLK_NONE
) &&
347 ucc_set_tdm_rxtx_sync(uf_info
->tdm_num
, uf_info
->rx_sync
,
349 pr_err("%s: illegal value for RX clock", __func__
);
354 /* tdm Tx sync clock routing */
355 if ((uf_info
->tx_sync
!= QE_CLK_NONE
) &&
356 ucc_set_tdm_rxtx_sync(uf_info
->tdm_num
, uf_info
->tx_sync
,
358 pr_err("%s: illegal value for TX clock", __func__
);
364 /* Set interrupt mask register at UCC level. */
365 out_be32(&uf_regs
->uccm
, uf_info
->uccm_mask
);
367 /* First, clear anything pending at UCC level,
368 * otherwise, old garbage may come through
369 * as soon as the dam is opened. */
371 /* Writing '1' clears */
372 out_be32(&uf_regs
->ucce
, 0xffffffff);
377 EXPORT_SYMBOL(ucc_fast_init
);
379 void ucc_fast_free(struct ucc_fast_private
* uccf
)
384 if (uccf
->ucc_fast_tx_virtual_fifo_base_offset
)
385 qe_muram_free(uccf
->ucc_fast_tx_virtual_fifo_base_offset
);
387 if (uccf
->ucc_fast_rx_virtual_fifo_base_offset
)
388 qe_muram_free(uccf
->ucc_fast_rx_virtual_fifo_base_offset
);
391 iounmap(uccf
->uf_regs
);
395 EXPORT_SYMBOL(ucc_fast_free
);