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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / soc / mediatek / mtk-pmic-wrap.c
blobc725315cf6a85c3ce2a8efb2680fdb7421042ee4
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Flora Fu, MediaTek
5 */
6 #include <linux/clk.h>
7 #include <linux/interrupt.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/reset.h>
15
16 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
17 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
18 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
19 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
20 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
21 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38
22 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
23 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
24 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
25
26 /* macro for wrapper status */
27 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
28 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
29 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
30 #define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
31 #define PWRAP_STATE_INIT_DONE0 (1 << 21)
32
33 /* macro for WACS FSM */
34 #define PWRAP_WACS_FSM_IDLE 0x00
35 #define PWRAP_WACS_FSM_REQ 0x02
36 #define PWRAP_WACS_FSM_WFDLE 0x04
37 #define PWRAP_WACS_FSM_WFVLDCLR 0x06
38 #define PWRAP_WACS_INIT_DONE 0x01
39 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01
40 #define PWRAP_WACS_SYNC_BUSY 0x00
41
42 /* macro for device wrapper default value */
43 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5
44 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
45
46 /* macro for manual command */
47 #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
48 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
49 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
50 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
51 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
52 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
53 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
54 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
55
56 /* macro for Watch Dog Timer Source */
57 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
58 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
59 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
60 #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
61 #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
62 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
63 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
64
65 /* Group of bits used for shown slave capability */
66 #define PWRAP_SLV_CAP_SPI BIT(0)
67 #define PWRAP_SLV_CAP_DUALIO BIT(1)
68 #define PWRAP_SLV_CAP_SECURITY BIT(2)
69 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
70
71 /* Group of bits used for shown pwrap capability */
72 #define PWRAP_CAP_BRIDGE BIT(0)
73 #define PWRAP_CAP_RESET BIT(1)
74 #define PWRAP_CAP_DCM BIT(2)
75 #define PWRAP_CAP_INT1_EN BIT(3)
76 #define PWRAP_CAP_WDT_SRC1 BIT(4)
77
78 /* defines for slave device wrapper registers */
79 enum dew_regs {
80 PWRAP_DEW_BASE,
81 PWRAP_DEW_DIO_EN,
82 PWRAP_DEW_READ_TEST,
83 PWRAP_DEW_WRITE_TEST,
84 PWRAP_DEW_CRC_EN,
85 PWRAP_DEW_CRC_VAL,
86 PWRAP_DEW_MON_GRP_SEL,
87 PWRAP_DEW_CIPHER_KEY_SEL,
88 PWRAP_DEW_CIPHER_IV_SEL,
89 PWRAP_DEW_CIPHER_RDY,
90 PWRAP_DEW_CIPHER_MODE,
91 PWRAP_DEW_CIPHER_SWRST,
92
93 /* MT6323 only regs */
94 PWRAP_DEW_CIPHER_EN,
95 PWRAP_DEW_RDDMY_NO,
96
97 /* MT6358 only regs */
98 PWRAP_SMT_CON1,
99 PWRAP_DRV_CON1,
100 PWRAP_FILTER_CON0,
101 PWRAP_GPIO_PULLEN0_CLR,
102 PWRAP_RG_SPI_CON0,
103 PWRAP_RG_SPI_RECORD0,
104 PWRAP_RG_SPI_CON2,
105 PWRAP_RG_SPI_CON3,
106 PWRAP_RG_SPI_CON4,
107 PWRAP_RG_SPI_CON5,
108 PWRAP_RG_SPI_CON6,
109 PWRAP_RG_SPI_CON7,
110 PWRAP_RG_SPI_CON8,
111 PWRAP_RG_SPI_CON13,
112 PWRAP_SPISLV_KEY,
113
114 /* MT6397 only regs */
115 PWRAP_DEW_EVENT_OUT_EN,
116 PWRAP_DEW_EVENT_SRC_EN,
117 PWRAP_DEW_EVENT_SRC,
118 PWRAP_DEW_EVENT_FLAG,
119 PWRAP_DEW_MON_FLAG_SEL,
120 PWRAP_DEW_EVENT_TEST,
121 PWRAP_DEW_CIPHER_LOAD,
122 PWRAP_DEW_CIPHER_START,
123 };
124
125 static const u32 mt6323_regs[] = {
126 [PWRAP_DEW_BASE] = 0x0000,
127 [PWRAP_DEW_DIO_EN] = 0x018a,
128 [PWRAP_DEW_READ_TEST] = 0x018c,
129 [PWRAP_DEW_WRITE_TEST] = 0x018e,
130 [PWRAP_DEW_CRC_EN] = 0x0192,
131 [PWRAP_DEW_CRC_VAL] = 0x0194,
132 [PWRAP_DEW_MON_GRP_SEL] = 0x0196,
133 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
134 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
135 [PWRAP_DEW_CIPHER_EN] = 0x019c,
136 [PWRAP_DEW_CIPHER_RDY] = 0x019e,
137 [PWRAP_DEW_CIPHER_MODE] = 0x01a0,
138 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
139 [PWRAP_DEW_RDDMY_NO] = 0x01a4,
140 };
141
142 static const u32 mt6351_regs[] = {
143 [PWRAP_DEW_DIO_EN] = 0x02F2,
144 [PWRAP_DEW_READ_TEST] = 0x02F4,
145 [PWRAP_DEW_WRITE_TEST] = 0x02F6,
146 [PWRAP_DEW_CRC_EN] = 0x02FA,
147 [PWRAP_DEW_CRC_VAL] = 0x02FC,
148 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300,
149 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,
150 [PWRAP_DEW_CIPHER_EN] = 0x0304,
151 [PWRAP_DEW_CIPHER_RDY] = 0x0306,
152 [PWRAP_DEW_CIPHER_MODE] = 0x0308,
153 [PWRAP_DEW_CIPHER_SWRST] = 0x030A,
154 [PWRAP_DEW_RDDMY_NO] = 0x030C,
155 };
156
157 static const u32 mt6357_regs[] = {
158 [PWRAP_DEW_DIO_EN] = 0x040A,
159 [PWRAP_DEW_READ_TEST] = 0x040C,
160 [PWRAP_DEW_WRITE_TEST] = 0x040E,
161 [PWRAP_DEW_CRC_EN] = 0x0412,
162 [PWRAP_DEW_CRC_VAL] = 0x0414,
163 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
164 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A,
165 [PWRAP_DEW_CIPHER_EN] = 0x041C,
166 [PWRAP_DEW_CIPHER_RDY] = 0x041E,
167 [PWRAP_DEW_CIPHER_MODE] = 0x0420,
168 [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
169 [PWRAP_DEW_RDDMY_NO] = 0x0424,
170 };
171
172 static const u32 mt6358_regs[] = {
173 [PWRAP_SMT_CON1] = 0x0030,
174 [PWRAP_DRV_CON1] = 0x0038,
175 [PWRAP_FILTER_CON0] = 0x0040,
176 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
177 [PWRAP_RG_SPI_CON0] = 0x0408,
178 [PWRAP_RG_SPI_RECORD0] = 0x040a,
179 [PWRAP_DEW_DIO_EN] = 0x040c,
180 [PWRAP_DEW_READ_TEST] = 0x040e,
181 [PWRAP_DEW_WRITE_TEST] = 0x0410,
182 [PWRAP_DEW_CRC_EN] = 0x0414,
183 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a,
184 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,
185 [PWRAP_DEW_CIPHER_EN] = 0x041e,
186 [PWRAP_DEW_CIPHER_RDY] = 0x0420,
187 [PWRAP_DEW_CIPHER_MODE] = 0x0422,
188 [PWRAP_DEW_CIPHER_SWRST] = 0x0424,
189 [PWRAP_RG_SPI_CON2] = 0x0432,
190 [PWRAP_RG_SPI_CON3] = 0x0434,
191 [PWRAP_RG_SPI_CON4] = 0x0436,
192 [PWRAP_RG_SPI_CON5] = 0x0438,
193 [PWRAP_RG_SPI_CON6] = 0x043a,
194 [PWRAP_RG_SPI_CON7] = 0x043c,
195 [PWRAP_RG_SPI_CON8] = 0x043e,
196 [PWRAP_RG_SPI_CON13] = 0x0448,
197 [PWRAP_SPISLV_KEY] = 0x044a,
198 };
199
200 static const u32 mt6397_regs[] = {
201 [PWRAP_DEW_BASE] = 0xbc00,
202 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
203 [PWRAP_DEW_DIO_EN] = 0xbc02,
204 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
205 [PWRAP_DEW_EVENT_SRC] = 0xbc06,
206 [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
207 [PWRAP_DEW_READ_TEST] = 0xbc0a,
208 [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
209 [PWRAP_DEW_CRC_EN] = 0xbc0e,
210 [PWRAP_DEW_CRC_VAL] = 0xbc10,
211 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
212 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
213 [PWRAP_DEW_EVENT_TEST] = 0xbc16,
214 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
215 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
216 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
217 [PWRAP_DEW_CIPHER_START] = 0xbc1e,
218 [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
219 [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
220 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
221 };
222
223 enum pwrap_regs {
224 PWRAP_MUX_SEL,
225 PWRAP_WRAP_EN,
226 PWRAP_DIO_EN,
227 PWRAP_SIDLY,
228 PWRAP_CSHEXT_WRITE,
229 PWRAP_CSHEXT_READ,
230 PWRAP_CSLEXT_START,
231 PWRAP_CSLEXT_END,
232 PWRAP_STAUPD_PRD,
233 PWRAP_STAUPD_GRPEN,
234 PWRAP_STAUPD_MAN_TRIG,
235 PWRAP_STAUPD_STA,
236 PWRAP_WRAP_STA,
237 PWRAP_HARB_INIT,
238 PWRAP_HARB_HPRIO,
239 PWRAP_HIPRIO_ARB_EN,
240 PWRAP_HARB_STA0,
241 PWRAP_HARB_STA1,
242 PWRAP_MAN_EN,
243 PWRAP_MAN_CMD,
244 PWRAP_MAN_RDATA,
245 PWRAP_MAN_VLDCLR,
246 PWRAP_WACS0_EN,
247 PWRAP_INIT_DONE0,
248 PWRAP_WACS0_CMD,
249 PWRAP_WACS0_RDATA,
250 PWRAP_WACS0_VLDCLR,
251 PWRAP_WACS1_EN,
252 PWRAP_INIT_DONE1,
253 PWRAP_WACS1_CMD,
254 PWRAP_WACS1_RDATA,
255 PWRAP_WACS1_VLDCLR,
256 PWRAP_WACS2_EN,
257 PWRAP_INIT_DONE2,
258 PWRAP_WACS2_CMD,
259 PWRAP_WACS2_RDATA,
260 PWRAP_WACS2_VLDCLR,
261 PWRAP_INT_EN,
262 PWRAP_INT_FLG_RAW,
263 PWRAP_INT_FLG,
264 PWRAP_INT_CLR,
265 PWRAP_SIG_ADR,
266 PWRAP_SIG_MODE,
267 PWRAP_SIG_VALUE,
268 PWRAP_SIG_ERRVAL,
269 PWRAP_CRC_EN,
270 PWRAP_TIMER_EN,
271 PWRAP_TIMER_STA,
272 PWRAP_WDT_UNIT,
273 PWRAP_WDT_SRC_EN,
274 PWRAP_WDT_FLG,
275 PWRAP_DEBUG_INT_SEL,
276 PWRAP_CIPHER_KEY_SEL,
277 PWRAP_CIPHER_IV_SEL,
278 PWRAP_CIPHER_RDY,
279 PWRAP_CIPHER_MODE,
280 PWRAP_CIPHER_SWRST,
281 PWRAP_DCM_EN,
282 PWRAP_DCM_DBC_PRD,
283 PWRAP_EINT_STA0_ADR,
284 PWRAP_EINT_STA1_ADR,
285
286 /* MT2701 only regs */
287 PWRAP_ADC_CMD_ADDR,
288 PWRAP_PWRAP_ADC_CMD,
289 PWRAP_ADC_RDY_ADDR,
290 PWRAP_ADC_RDATA_ADDR1,
291 PWRAP_ADC_RDATA_ADDR2,
292
293 /* MT7622 only regs */
294 PWRAP_STA,
295 PWRAP_CLR,
296 PWRAP_DVFS_ADR8,
297 PWRAP_DVFS_WDATA8,
298 PWRAP_DVFS_ADR9,
299 PWRAP_DVFS_WDATA9,
300 PWRAP_DVFS_ADR10,
301 PWRAP_DVFS_WDATA10,
302 PWRAP_DVFS_ADR11,
303 PWRAP_DVFS_WDATA11,
304 PWRAP_DVFS_ADR12,
305 PWRAP_DVFS_WDATA12,
306 PWRAP_DVFS_ADR13,
307 PWRAP_DVFS_WDATA13,
308 PWRAP_DVFS_ADR14,
309 PWRAP_DVFS_WDATA14,
310 PWRAP_DVFS_ADR15,
311 PWRAP_DVFS_WDATA15,
312 PWRAP_EXT_CK,
313 PWRAP_ADC_RDATA_ADDR,
314 PWRAP_GPS_STA,
315 PWRAP_SW_RST,
316 PWRAP_DVFS_STEP_CTRL0,
317 PWRAP_DVFS_STEP_CTRL1,
318 PWRAP_DVFS_STEP_CTRL2,
319 PWRAP_SPI2_CTRL,
320
321 /* MT8135 only regs */
322 PWRAP_CSHEXT,
323 PWRAP_EVENT_IN_EN,
324 PWRAP_EVENT_DST_EN,
325 PWRAP_RRARB_INIT,
326 PWRAP_RRARB_EN,
327 PWRAP_RRARB_STA0,
328 PWRAP_RRARB_STA1,
329 PWRAP_EVENT_STA,
330 PWRAP_EVENT_STACLR,
331 PWRAP_CIPHER_LOAD,
332 PWRAP_CIPHER_START,
333
334 /* MT8173 only regs */
335 PWRAP_RDDMY,
336 PWRAP_SI_CK_CON,
337 PWRAP_DVFS_ADR0,
338 PWRAP_DVFS_WDATA0,
339 PWRAP_DVFS_ADR1,
340 PWRAP_DVFS_WDATA1,
341 PWRAP_DVFS_ADR2,
342 PWRAP_DVFS_WDATA2,
343 PWRAP_DVFS_ADR3,
344 PWRAP_DVFS_WDATA3,
345 PWRAP_DVFS_ADR4,
346 PWRAP_DVFS_WDATA4,
347 PWRAP_DVFS_ADR5,
348 PWRAP_DVFS_WDATA5,
349 PWRAP_DVFS_ADR6,
350 PWRAP_DVFS_WDATA6,
351 PWRAP_DVFS_ADR7,
352 PWRAP_DVFS_WDATA7,
353 PWRAP_SPMINF_STA,
354 PWRAP_CIPHER_EN,
355
356 /* MT8183 only regs */
357 PWRAP_SI_SAMPLE_CTRL,
358 PWRAP_CSLEXT_WRITE,
359 PWRAP_CSLEXT_READ,
360 PWRAP_EXT_CK_WRITE,
361 PWRAP_STAUPD_CTRL,
362 PWRAP_WACS_P2P_EN,
363 PWRAP_INIT_DONE_P2P,
364 PWRAP_WACS_MD32_EN,
365 PWRAP_INIT_DONE_MD32,
366 PWRAP_INT1_EN,
367 PWRAP_INT1_FLG,
368 PWRAP_INT1_CLR,
369 PWRAP_WDT_SRC_EN_1,
370 PWRAP_INT_GPS_AUXADC_CMD_ADDR,
371 PWRAP_INT_GPS_AUXADC_CMD,
372 PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
373 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
374 PWRAP_GPSINF_0_STA,
375 PWRAP_GPSINF_1_STA,
376
377 /* MT8516 only regs */
378 PWRAP_OP_TYPE,
379 PWRAP_MSB_FIRST,
380 };
381
382 static int mt2701_regs[] = {
383 [PWRAP_MUX_SEL] = 0x0,
384 [PWRAP_WRAP_EN] = 0x4,
385 [PWRAP_DIO_EN] = 0x8,
386 [PWRAP_SIDLY] = 0xc,
387 [PWRAP_RDDMY] = 0x18,
388 [PWRAP_SI_CK_CON] = 0x1c,
389 [PWRAP_CSHEXT_WRITE] = 0x20,
390 [PWRAP_CSHEXT_READ] = 0x24,
391 [PWRAP_CSLEXT_START] = 0x28,
392 [PWRAP_CSLEXT_END] = 0x2c,
393 [PWRAP_STAUPD_PRD] = 0x30,
394 [PWRAP_STAUPD_GRPEN] = 0x34,
395 [PWRAP_STAUPD_MAN_TRIG] = 0x38,
396 [PWRAP_STAUPD_STA] = 0x3c,
397 [PWRAP_WRAP_STA] = 0x44,
398 [PWRAP_HARB_INIT] = 0x48,
399 [PWRAP_HARB_HPRIO] = 0x4c,
400 [PWRAP_HIPRIO_ARB_EN] = 0x50,
401 [PWRAP_HARB_STA0] = 0x54,
402 [PWRAP_HARB_STA1] = 0x58,
403 [PWRAP_MAN_EN] = 0x5c,
404 [PWRAP_MAN_CMD] = 0x60,
405 [PWRAP_MAN_RDATA] = 0x64,
406 [PWRAP_MAN_VLDCLR] = 0x68,
407 [PWRAP_WACS0_EN] = 0x6c,
408 [PWRAP_INIT_DONE0] = 0x70,
409 [PWRAP_WACS0_CMD] = 0x74,
410 [PWRAP_WACS0_RDATA] = 0x78,
411 [PWRAP_WACS0_VLDCLR] = 0x7c,
412 [PWRAP_WACS1_EN] = 0x80,
413 [PWRAP_INIT_DONE1] = 0x84,
414 [PWRAP_WACS1_CMD] = 0x88,
415 [PWRAP_WACS1_RDATA] = 0x8c,
416 [PWRAP_WACS1_VLDCLR] = 0x90,
417 [PWRAP_WACS2_EN] = 0x94,
418 [PWRAP_INIT_DONE2] = 0x98,
419 [PWRAP_WACS2_CMD] = 0x9c,
420 [PWRAP_WACS2_RDATA] = 0xa0,
421 [PWRAP_WACS2_VLDCLR] = 0xa4,
422 [PWRAP_INT_EN] = 0xa8,
423 [PWRAP_INT_FLG_RAW] = 0xac,
424 [PWRAP_INT_FLG] = 0xb0,
425 [PWRAP_INT_CLR] = 0xb4,
426 [PWRAP_SIG_ADR] = 0xb8,
427 [PWRAP_SIG_MODE] = 0xbc,
428 [PWRAP_SIG_VALUE] = 0xc0,
429 [PWRAP_SIG_ERRVAL] = 0xc4,
430 [PWRAP_CRC_EN] = 0xc8,
431 [PWRAP_TIMER_EN] = 0xcc,
432 [PWRAP_TIMER_STA] = 0xd0,
433 [PWRAP_WDT_UNIT] = 0xd4,
434 [PWRAP_WDT_SRC_EN] = 0xd8,
435 [PWRAP_WDT_FLG] = 0xdc,
436 [PWRAP_DEBUG_INT_SEL] = 0xe0,
437 [PWRAP_DVFS_ADR0] = 0xe4,
438 [PWRAP_DVFS_WDATA0] = 0xe8,
439 [PWRAP_DVFS_ADR1] = 0xec,
440 [PWRAP_DVFS_WDATA1] = 0xf0,
441 [PWRAP_DVFS_ADR2] = 0xf4,
442 [PWRAP_DVFS_WDATA2] = 0xf8,
443 [PWRAP_DVFS_ADR3] = 0xfc,
444 [PWRAP_DVFS_WDATA3] = 0x100,
445 [PWRAP_DVFS_ADR4] = 0x104,
446 [PWRAP_DVFS_WDATA4] = 0x108,
447 [PWRAP_DVFS_ADR5] = 0x10c,
448 [PWRAP_DVFS_WDATA5] = 0x110,
449 [PWRAP_DVFS_ADR6] = 0x114,
450 [PWRAP_DVFS_WDATA6] = 0x118,
451 [PWRAP_DVFS_ADR7] = 0x11c,
452 [PWRAP_DVFS_WDATA7] = 0x120,
453 [PWRAP_CIPHER_KEY_SEL] = 0x124,
454 [PWRAP_CIPHER_IV_SEL] = 0x128,
455 [PWRAP_CIPHER_EN] = 0x12c,
456 [PWRAP_CIPHER_RDY] = 0x130,
457 [PWRAP_CIPHER_MODE] = 0x134,
458 [PWRAP_CIPHER_SWRST] = 0x138,
459 [PWRAP_DCM_EN] = 0x13c,
460 [PWRAP_DCM_DBC_PRD] = 0x140,
461 [PWRAP_ADC_CMD_ADDR] = 0x144,
462 [PWRAP_PWRAP_ADC_CMD] = 0x148,
463 [PWRAP_ADC_RDY_ADDR] = 0x14c,
464 [PWRAP_ADC_RDATA_ADDR1] = 0x150,
465 [PWRAP_ADC_RDATA_ADDR2] = 0x154,
466 };
467
468 static int mt6765_regs[] = {
469 [PWRAP_MUX_SEL] = 0x0,
470 [PWRAP_WRAP_EN] = 0x4,
471 [PWRAP_DIO_EN] = 0x8,
472 [PWRAP_RDDMY] = 0x20,
473 [PWRAP_CSHEXT_WRITE] = 0x24,
474 [PWRAP_CSHEXT_READ] = 0x28,
475 [PWRAP_CSLEXT_START] = 0x2C,
476 [PWRAP_CSLEXT_END] = 0x30,
477 [PWRAP_STAUPD_PRD] = 0x3C,
478 [PWRAP_HARB_HPRIO] = 0x68,
479 [PWRAP_HIPRIO_ARB_EN] = 0x6C,
480 [PWRAP_MAN_EN] = 0x7C,
481 [PWRAP_MAN_CMD] = 0x80,
482 [PWRAP_WACS0_EN] = 0x8C,
483 [PWRAP_WACS1_EN] = 0x94,
484 [PWRAP_WACS2_EN] = 0x9C,
485 [PWRAP_INIT_DONE2] = 0xA0,
486 [PWRAP_WACS2_CMD] = 0xC20,
487 [PWRAP_WACS2_RDATA] = 0xC24,
488 [PWRAP_WACS2_VLDCLR] = 0xC28,
489 [PWRAP_INT_EN] = 0xB4,
490 [PWRAP_INT_FLG_RAW] = 0xB8,
491 [PWRAP_INT_FLG] = 0xBC,
492 [PWRAP_INT_CLR] = 0xC0,
493 [PWRAP_TIMER_EN] = 0xE8,
494 [PWRAP_WDT_UNIT] = 0xF0,
495 [PWRAP_WDT_SRC_EN] = 0xF4,
496 [PWRAP_DCM_EN] = 0x1DC,
497 [PWRAP_DCM_DBC_PRD] = 0x1E0,
498 };
499
500 static int mt6797_regs[] = {
501 [PWRAP_MUX_SEL] = 0x0,
502 [PWRAP_WRAP_EN] = 0x4,
503 [PWRAP_DIO_EN] = 0x8,
504 [PWRAP_SIDLY] = 0xC,
505 [PWRAP_RDDMY] = 0x10,
506 [PWRAP_CSHEXT_WRITE] = 0x18,
507 [PWRAP_CSHEXT_READ] = 0x1C,
508 [PWRAP_CSLEXT_START] = 0x20,
509 [PWRAP_CSLEXT_END] = 0x24,
510 [PWRAP_STAUPD_PRD] = 0x28,
511 [PWRAP_HARB_HPRIO] = 0x50,
512 [PWRAP_HIPRIO_ARB_EN] = 0x54,
513 [PWRAP_MAN_EN] = 0x60,
514 [PWRAP_MAN_CMD] = 0x64,
515 [PWRAP_WACS0_EN] = 0x70,
516 [PWRAP_WACS1_EN] = 0x84,
517 [PWRAP_WACS2_EN] = 0x98,
518 [PWRAP_INIT_DONE2] = 0x9C,
519 [PWRAP_WACS2_CMD] = 0xA0,
520 [PWRAP_WACS2_RDATA] = 0xA4,
521 [PWRAP_WACS2_VLDCLR] = 0xA8,
522 [PWRAP_INT_EN] = 0xC0,
523 [PWRAP_INT_FLG_RAW] = 0xC4,
524 [PWRAP_INT_FLG] = 0xC8,
525 [PWRAP_INT_CLR] = 0xCC,
526 [PWRAP_TIMER_EN] = 0xF4,
527 [PWRAP_WDT_UNIT] = 0xFC,
528 [PWRAP_WDT_SRC_EN] = 0x100,
529 [PWRAP_DCM_EN] = 0x1CC,
530 [PWRAP_DCM_DBC_PRD] = 0x1D4,
531 };
532
533 static int mt7622_regs[] = {
534 [PWRAP_MUX_SEL] = 0x0,
535 [PWRAP_WRAP_EN] = 0x4,
536 [PWRAP_DIO_EN] = 0x8,
537 [PWRAP_SIDLY] = 0xC,
538 [PWRAP_RDDMY] = 0x10,
539 [PWRAP_SI_CK_CON] = 0x14,
540 [PWRAP_CSHEXT_WRITE] = 0x18,
541 [PWRAP_CSHEXT_READ] = 0x1C,
542 [PWRAP_CSLEXT_START] = 0x20,
543 [PWRAP_CSLEXT_END] = 0x24,
544 [PWRAP_STAUPD_PRD] = 0x28,
545 [PWRAP_STAUPD_GRPEN] = 0x2C,
546 [PWRAP_EINT_STA0_ADR] = 0x30,
547 [PWRAP_EINT_STA1_ADR] = 0x34,
548 [PWRAP_STA] = 0x38,
549 [PWRAP_CLR] = 0x3C,
550 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
551 [PWRAP_STAUPD_STA] = 0x44,
552 [PWRAP_WRAP_STA] = 0x48,
553 [PWRAP_HARB_INIT] = 0x4C,
554 [PWRAP_HARB_HPRIO] = 0x50,
555 [PWRAP_HIPRIO_ARB_EN] = 0x54,
556 [PWRAP_HARB_STA0] = 0x58,
557 [PWRAP_HARB_STA1] = 0x5C,
558 [PWRAP_MAN_EN] = 0x60,
559 [PWRAP_MAN_CMD] = 0x64,
560 [PWRAP_MAN_RDATA] = 0x68,
561 [PWRAP_MAN_VLDCLR] = 0x6C,
562 [PWRAP_WACS0_EN] = 0x70,
563 [PWRAP_INIT_DONE0] = 0x74,
564 [PWRAP_WACS0_CMD] = 0x78,
565 [PWRAP_WACS0_RDATA] = 0x7C,
566 [PWRAP_WACS0_VLDCLR] = 0x80,
567 [PWRAP_WACS1_EN] = 0x84,
568 [PWRAP_INIT_DONE1] = 0x88,
569 [PWRAP_WACS1_CMD] = 0x8C,
570 [PWRAP_WACS1_RDATA] = 0x90,
571 [PWRAP_WACS1_VLDCLR] = 0x94,
572 [PWRAP_WACS2_EN] = 0x98,
573 [PWRAP_INIT_DONE2] = 0x9C,
574 [PWRAP_WACS2_CMD] = 0xA0,
575 [PWRAP_WACS2_RDATA] = 0xA4,
576 [PWRAP_WACS2_VLDCLR] = 0xA8,
577 [PWRAP_INT_EN] = 0xAC,
578 [PWRAP_INT_FLG_RAW] = 0xB0,
579 [PWRAP_INT_FLG] = 0xB4,
580 [PWRAP_INT_CLR] = 0xB8,
581 [PWRAP_SIG_ADR] = 0xBC,
582 [PWRAP_SIG_MODE] = 0xC0,
583 [PWRAP_SIG_VALUE] = 0xC4,
584 [PWRAP_SIG_ERRVAL] = 0xC8,
585 [PWRAP_CRC_EN] = 0xCC,
586 [PWRAP_TIMER_EN] = 0xD0,
587 [PWRAP_TIMER_STA] = 0xD4,
588 [PWRAP_WDT_UNIT] = 0xD8,
589 [PWRAP_WDT_SRC_EN] = 0xDC,
590 [PWRAP_WDT_FLG] = 0xE0,
591 [PWRAP_DEBUG_INT_SEL] = 0xE4,
592 [PWRAP_DVFS_ADR0] = 0xE8,
593 [PWRAP_DVFS_WDATA0] = 0xEC,
594 [PWRAP_DVFS_ADR1] = 0xF0,
595 [PWRAP_DVFS_WDATA1] = 0xF4,
596 [PWRAP_DVFS_ADR2] = 0xF8,
597 [PWRAP_DVFS_WDATA2] = 0xFC,
598 [PWRAP_DVFS_ADR3] = 0x100,
599 [PWRAP_DVFS_WDATA3] = 0x104,
600 [PWRAP_DVFS_ADR4] = 0x108,
601 [PWRAP_DVFS_WDATA4] = 0x10C,
602 [PWRAP_DVFS_ADR5] = 0x110,
603 [PWRAP_DVFS_WDATA5] = 0x114,
604 [PWRAP_DVFS_ADR6] = 0x118,
605 [PWRAP_DVFS_WDATA6] = 0x11C,
606 [PWRAP_DVFS_ADR7] = 0x120,
607 [PWRAP_DVFS_WDATA7] = 0x124,
608 [PWRAP_DVFS_ADR8] = 0x128,
609 [PWRAP_DVFS_WDATA8] = 0x12C,
610 [PWRAP_DVFS_ADR9] = 0x130,
611 [PWRAP_DVFS_WDATA9] = 0x134,
612 [PWRAP_DVFS_ADR10] = 0x138,
613 [PWRAP_DVFS_WDATA10] = 0x13C,
614 [PWRAP_DVFS_ADR11] = 0x140,
615 [PWRAP_DVFS_WDATA11] = 0x144,
616 [PWRAP_DVFS_ADR12] = 0x148,
617 [PWRAP_DVFS_WDATA12] = 0x14C,
618 [PWRAP_DVFS_ADR13] = 0x150,
619 [PWRAP_DVFS_WDATA13] = 0x154,
620 [PWRAP_DVFS_ADR14] = 0x158,
621 [PWRAP_DVFS_WDATA14] = 0x15C,
622 [PWRAP_DVFS_ADR15] = 0x160,
623 [PWRAP_DVFS_WDATA15] = 0x164,
624 [PWRAP_SPMINF_STA] = 0x168,
625 [PWRAP_CIPHER_KEY_SEL] = 0x16C,
626 [PWRAP_CIPHER_IV_SEL] = 0x170,
627 [PWRAP_CIPHER_EN] = 0x174,
628 [PWRAP_CIPHER_RDY] = 0x178,
629 [PWRAP_CIPHER_MODE] = 0x17C,
630 [PWRAP_CIPHER_SWRST] = 0x180,
631 [PWRAP_DCM_EN] = 0x184,
632 [PWRAP_DCM_DBC_PRD] = 0x188,
633 [PWRAP_EXT_CK] = 0x18C,
634 [PWRAP_ADC_CMD_ADDR] = 0x190,
635 [PWRAP_PWRAP_ADC_CMD] = 0x194,
636 [PWRAP_ADC_RDATA_ADDR] = 0x198,
637 [PWRAP_GPS_STA] = 0x19C,
638 [PWRAP_SW_RST] = 0x1A0,
639 [PWRAP_DVFS_STEP_CTRL0] = 0x238,
640 [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
641 [PWRAP_DVFS_STEP_CTRL2] = 0x240,
642 [PWRAP_SPI2_CTRL] = 0x244,
643 };
644
645 static int mt8135_regs[] = {
646 [PWRAP_MUX_SEL] = 0x0,
647 [PWRAP_WRAP_EN] = 0x4,
648 [PWRAP_DIO_EN] = 0x8,
649 [PWRAP_SIDLY] = 0xc,
650 [PWRAP_CSHEXT] = 0x10,
651 [PWRAP_CSHEXT_WRITE] = 0x14,
652 [PWRAP_CSHEXT_READ] = 0x18,
653 [PWRAP_CSLEXT_START] = 0x1c,
654 [PWRAP_CSLEXT_END] = 0x20,
655 [PWRAP_STAUPD_PRD] = 0x24,
656 [PWRAP_STAUPD_GRPEN] = 0x28,
657 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
658 [PWRAP_STAUPD_STA] = 0x30,
659 [PWRAP_EVENT_IN_EN] = 0x34,
660 [PWRAP_EVENT_DST_EN] = 0x38,
661 [PWRAP_WRAP_STA] = 0x3c,
662 [PWRAP_RRARB_INIT] = 0x40,
663 [PWRAP_RRARB_EN] = 0x44,
664 [PWRAP_RRARB_STA0] = 0x48,
665 [PWRAP_RRARB_STA1] = 0x4c,
666 [PWRAP_HARB_INIT] = 0x50,
667 [PWRAP_HARB_HPRIO] = 0x54,
668 [PWRAP_HIPRIO_ARB_EN] = 0x58,
669 [PWRAP_HARB_STA0] = 0x5c,
670 [PWRAP_HARB_STA1] = 0x60,
671 [PWRAP_MAN_EN] = 0x64,
672 [PWRAP_MAN_CMD] = 0x68,
673 [PWRAP_MAN_RDATA] = 0x6c,
674 [PWRAP_MAN_VLDCLR] = 0x70,
675 [PWRAP_WACS0_EN] = 0x74,
676 [PWRAP_INIT_DONE0] = 0x78,
677 [PWRAP_WACS0_CMD] = 0x7c,
678 [PWRAP_WACS0_RDATA] = 0x80,
679 [PWRAP_WACS0_VLDCLR] = 0x84,
680 [PWRAP_WACS1_EN] = 0x88,
681 [PWRAP_INIT_DONE1] = 0x8c,
682 [PWRAP_WACS1_CMD] = 0x90,
683 [PWRAP_WACS1_RDATA] = 0x94,
684 [PWRAP_WACS1_VLDCLR] = 0x98,
685 [PWRAP_WACS2_EN] = 0x9c,
686 [PWRAP_INIT_DONE2] = 0xa0,
687 [PWRAP_WACS2_CMD] = 0xa4,
688 [PWRAP_WACS2_RDATA] = 0xa8,
689 [PWRAP_WACS2_VLDCLR] = 0xac,
690 [PWRAP_INT_EN] = 0xb0,
691 [PWRAP_INT_FLG_RAW] = 0xb4,
692 [PWRAP_INT_FLG] = 0xb8,
693 [PWRAP_INT_CLR] = 0xbc,
694 [PWRAP_SIG_ADR] = 0xc0,
695 [PWRAP_SIG_MODE] = 0xc4,
696 [PWRAP_SIG_VALUE] = 0xc8,
697 [PWRAP_SIG_ERRVAL] = 0xcc,
698 [PWRAP_CRC_EN] = 0xd0,
699 [PWRAP_EVENT_STA] = 0xd4,
700 [PWRAP_EVENT_STACLR] = 0xd8,
701 [PWRAP_TIMER_EN] = 0xdc,
702 [PWRAP_TIMER_STA] = 0xe0,
703 [PWRAP_WDT_UNIT] = 0xe4,
704 [PWRAP_WDT_SRC_EN] = 0xe8,
705 [PWRAP_WDT_FLG] = 0xec,
706 [PWRAP_DEBUG_INT_SEL] = 0xf0,
707 [PWRAP_CIPHER_KEY_SEL] = 0x134,
708 [PWRAP_CIPHER_IV_SEL] = 0x138,
709 [PWRAP_CIPHER_LOAD] = 0x13c,
710 [PWRAP_CIPHER_START] = 0x140,
711 [PWRAP_CIPHER_RDY] = 0x144,
712 [PWRAP_CIPHER_MODE] = 0x148,
713 [PWRAP_CIPHER_SWRST] = 0x14c,
714 [PWRAP_DCM_EN] = 0x15c,
715 [PWRAP_DCM_DBC_PRD] = 0x160,
716 };
717
718 static int mt8173_regs[] = {
719 [PWRAP_MUX_SEL] = 0x0,
720 [PWRAP_WRAP_EN] = 0x4,
721 [PWRAP_DIO_EN] = 0x8,
722 [PWRAP_SIDLY] = 0xc,
723 [PWRAP_RDDMY] = 0x10,
724 [PWRAP_SI_CK_CON] = 0x14,
725 [PWRAP_CSHEXT_WRITE] = 0x18,
726 [PWRAP_CSHEXT_READ] = 0x1c,
727 [PWRAP_CSLEXT_START] = 0x20,
728 [PWRAP_CSLEXT_END] = 0x24,
729 [PWRAP_STAUPD_PRD] = 0x28,
730 [PWRAP_STAUPD_GRPEN] = 0x2c,
731 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
732 [PWRAP_STAUPD_STA] = 0x44,
733 [PWRAP_WRAP_STA] = 0x48,
734 [PWRAP_HARB_INIT] = 0x4c,
735 [PWRAP_HARB_HPRIO] = 0x50,
736 [PWRAP_HIPRIO_ARB_EN] = 0x54,
737 [PWRAP_HARB_STA0] = 0x58,
738 [PWRAP_HARB_STA1] = 0x5c,
739 [PWRAP_MAN_EN] = 0x60,
740 [PWRAP_MAN_CMD] = 0x64,
741 [PWRAP_MAN_RDATA] = 0x68,
742 [PWRAP_MAN_VLDCLR] = 0x6c,
743 [PWRAP_WACS0_EN] = 0x70,
744 [PWRAP_INIT_DONE0] = 0x74,
745 [PWRAP_WACS0_CMD] = 0x78,
746 [PWRAP_WACS0_RDATA] = 0x7c,
747 [PWRAP_WACS0_VLDCLR] = 0x80,
748 [PWRAP_WACS1_EN] = 0x84,
749 [PWRAP_INIT_DONE1] = 0x88,
750 [PWRAP_WACS1_CMD] = 0x8c,
751 [PWRAP_WACS1_RDATA] = 0x90,
752 [PWRAP_WACS1_VLDCLR] = 0x94,
753 [PWRAP_WACS2_EN] = 0x98,
754 [PWRAP_INIT_DONE2] = 0x9c,
755 [PWRAP_WACS2_CMD] = 0xa0,
756 [PWRAP_WACS2_RDATA] = 0xa4,
757 [PWRAP_WACS2_VLDCLR] = 0xa8,
758 [PWRAP_INT_EN] = 0xac,
759 [PWRAP_INT_FLG_RAW] = 0xb0,
760 [PWRAP_INT_FLG] = 0xb4,
761 [PWRAP_INT_CLR] = 0xb8,
762 [PWRAP_SIG_ADR] = 0xbc,
763 [PWRAP_SIG_MODE] = 0xc0,
764 [PWRAP_SIG_VALUE] = 0xc4,
765 [PWRAP_SIG_ERRVAL] = 0xc8,
766 [PWRAP_CRC_EN] = 0xcc,
767 [PWRAP_TIMER_EN] = 0xd0,
768 [PWRAP_TIMER_STA] = 0xd4,
769 [PWRAP_WDT_UNIT] = 0xd8,
770 [PWRAP_WDT_SRC_EN] = 0xdc,
771 [PWRAP_WDT_FLG] = 0xe0,
772 [PWRAP_DEBUG_INT_SEL] = 0xe4,
773 [PWRAP_DVFS_ADR0] = 0xe8,
774 [PWRAP_DVFS_WDATA0] = 0xec,
775 [PWRAP_DVFS_ADR1] = 0xf0,
776 [PWRAP_DVFS_WDATA1] = 0xf4,
777 [PWRAP_DVFS_ADR2] = 0xf8,
778 [PWRAP_DVFS_WDATA2] = 0xfc,
779 [PWRAP_DVFS_ADR3] = 0x100,
780 [PWRAP_DVFS_WDATA3] = 0x104,
781 [PWRAP_DVFS_ADR4] = 0x108,
782 [PWRAP_DVFS_WDATA4] = 0x10c,
783 [PWRAP_DVFS_ADR5] = 0x110,
784 [PWRAP_DVFS_WDATA5] = 0x114,
785 [PWRAP_DVFS_ADR6] = 0x118,
786 [PWRAP_DVFS_WDATA6] = 0x11c,
787 [PWRAP_DVFS_ADR7] = 0x120,
788 [PWRAP_DVFS_WDATA7] = 0x124,
789 [PWRAP_SPMINF_STA] = 0x128,
790 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
791 [PWRAP_CIPHER_IV_SEL] = 0x130,
792 [PWRAP_CIPHER_EN] = 0x134,
793 [PWRAP_CIPHER_RDY] = 0x138,
794 [PWRAP_CIPHER_MODE] = 0x13c,
795 [PWRAP_CIPHER_SWRST] = 0x140,
796 [PWRAP_DCM_EN] = 0x144,
797 [PWRAP_DCM_DBC_PRD] = 0x148,
798 };
799
800 static int mt8183_regs[] = {
801 [PWRAP_MUX_SEL] = 0x0,
802 [PWRAP_WRAP_EN] = 0x4,
803 [PWRAP_DIO_EN] = 0x8,
804 [PWRAP_SI_SAMPLE_CTRL] = 0xC,
805 [PWRAP_RDDMY] = 0x14,
806 [PWRAP_CSHEXT_WRITE] = 0x18,
807 [PWRAP_CSHEXT_READ] = 0x1C,
808 [PWRAP_CSLEXT_WRITE] = 0x20,
809 [PWRAP_CSLEXT_READ] = 0x24,
810 [PWRAP_EXT_CK_WRITE] = 0x28,
811 [PWRAP_STAUPD_CTRL] = 0x30,
812 [PWRAP_STAUPD_GRPEN] = 0x34,
813 [PWRAP_EINT_STA0_ADR] = 0x38,
814 [PWRAP_HARB_HPRIO] = 0x5C,
815 [PWRAP_HIPRIO_ARB_EN] = 0x60,
816 [PWRAP_MAN_EN] = 0x70,
817 [PWRAP_MAN_CMD] = 0x74,
818 [PWRAP_WACS0_EN] = 0x80,
819 [PWRAP_INIT_DONE0] = 0x84,
820 [PWRAP_WACS1_EN] = 0x88,
821 [PWRAP_INIT_DONE1] = 0x8C,
822 [PWRAP_WACS2_EN] = 0x90,
823 [PWRAP_INIT_DONE2] = 0x94,
824 [PWRAP_WACS_P2P_EN] = 0xA0,
825 [PWRAP_INIT_DONE_P2P] = 0xA4,
826 [PWRAP_WACS_MD32_EN] = 0xA8,
827 [PWRAP_INIT_DONE_MD32] = 0xAC,
828 [PWRAP_INT_EN] = 0xB0,
829 [PWRAP_INT_FLG] = 0xB8,
830 [PWRAP_INT_CLR] = 0xBC,
831 [PWRAP_INT1_EN] = 0xC0,
832 [PWRAP_INT1_FLG] = 0xC8,
833 [PWRAP_INT1_CLR] = 0xCC,
834 [PWRAP_SIG_ADR] = 0xD0,
835 [PWRAP_CRC_EN] = 0xE0,
836 [PWRAP_TIMER_EN] = 0xE4,
837 [PWRAP_WDT_UNIT] = 0xEC,
838 [PWRAP_WDT_SRC_EN] = 0xF0,
839 [PWRAP_WDT_SRC_EN_1] = 0xF4,
840 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC,
841 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0,
842 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,
843 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,
844 [PWRAP_GPSINF_0_STA] = 0x1EC,
845 [PWRAP_GPSINF_1_STA] = 0x1F0,
846 [PWRAP_WACS2_CMD] = 0xC20,
847 [PWRAP_WACS2_RDATA] = 0xC24,
848 [PWRAP_WACS2_VLDCLR] = 0xC28,
849 };
850
851 static int mt8516_regs[] = {
852 [PWRAP_MUX_SEL] = 0x0,
853 [PWRAP_WRAP_EN] = 0x4,
854 [PWRAP_DIO_EN] = 0x8,
855 [PWRAP_SIDLY] = 0xc,
856 [PWRAP_RDDMY] = 0x10,
857 [PWRAP_SI_CK_CON] = 0x14,
858 [PWRAP_CSHEXT_WRITE] = 0x18,
859 [PWRAP_CSHEXT_READ] = 0x1c,
860 [PWRAP_CSLEXT_START] = 0x20,
861 [PWRAP_CSLEXT_END] = 0x24,
862 [PWRAP_STAUPD_PRD] = 0x28,
863 [PWRAP_STAUPD_GRPEN] = 0x2c,
864 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
865 [PWRAP_STAUPD_STA] = 0x44,
866 [PWRAP_WRAP_STA] = 0x48,
867 [PWRAP_HARB_INIT] = 0x4c,
868 [PWRAP_HARB_HPRIO] = 0x50,
869 [PWRAP_HIPRIO_ARB_EN] = 0x54,
870 [PWRAP_HARB_STA0] = 0x58,
871 [PWRAP_HARB_STA1] = 0x5c,
872 [PWRAP_MAN_EN] = 0x60,
873 [PWRAP_MAN_CMD] = 0x64,
874 [PWRAP_MAN_RDATA] = 0x68,
875 [PWRAP_MAN_VLDCLR] = 0x6c,
876 [PWRAP_WACS0_EN] = 0x70,
877 [PWRAP_INIT_DONE0] = 0x74,
878 [PWRAP_WACS0_CMD] = 0x78,
879 [PWRAP_WACS0_RDATA] = 0x7c,
880 [PWRAP_WACS0_VLDCLR] = 0x80,
881 [PWRAP_WACS1_EN] = 0x84,
882 [PWRAP_INIT_DONE1] = 0x88,
883 [PWRAP_WACS1_CMD] = 0x8c,
884 [PWRAP_WACS1_RDATA] = 0x90,
885 [PWRAP_WACS1_VLDCLR] = 0x94,
886 [PWRAP_WACS2_EN] = 0x98,
887 [PWRAP_INIT_DONE2] = 0x9c,
888 [PWRAP_WACS2_CMD] = 0xa0,
889 [PWRAP_WACS2_RDATA] = 0xa4,
890 [PWRAP_WACS2_VLDCLR] = 0xa8,
891 [PWRAP_INT_EN] = 0xac,
892 [PWRAP_INT_FLG_RAW] = 0xb0,
893 [PWRAP_INT_FLG] = 0xb4,
894 [PWRAP_INT_CLR] = 0xb8,
895 [PWRAP_SIG_ADR] = 0xbc,
896 [PWRAP_SIG_MODE] = 0xc0,
897 [PWRAP_SIG_VALUE] = 0xc4,
898 [PWRAP_SIG_ERRVAL] = 0xc8,
899 [PWRAP_CRC_EN] = 0xcc,
900 [PWRAP_TIMER_EN] = 0xd0,
901 [PWRAP_TIMER_STA] = 0xd4,
902 [PWRAP_WDT_UNIT] = 0xd8,
903 [PWRAP_WDT_SRC_EN] = 0xdc,
904 [PWRAP_WDT_FLG] = 0xe0,
905 [PWRAP_DEBUG_INT_SEL] = 0xe4,
906 [PWRAP_DVFS_ADR0] = 0xe8,
907 [PWRAP_DVFS_WDATA0] = 0xec,
908 [PWRAP_DVFS_ADR1] = 0xf0,
909 [PWRAP_DVFS_WDATA1] = 0xf4,
910 [PWRAP_DVFS_ADR2] = 0xf8,
911 [PWRAP_DVFS_WDATA2] = 0xfc,
912 [PWRAP_DVFS_ADR3] = 0x100,
913 [PWRAP_DVFS_WDATA3] = 0x104,
914 [PWRAP_DVFS_ADR4] = 0x108,
915 [PWRAP_DVFS_WDATA4] = 0x10c,
916 [PWRAP_DVFS_ADR5] = 0x110,
917 [PWRAP_DVFS_WDATA5] = 0x114,
918 [PWRAP_DVFS_ADR6] = 0x118,
919 [PWRAP_DVFS_WDATA6] = 0x11c,
920 [PWRAP_DVFS_ADR7] = 0x120,
921 [PWRAP_DVFS_WDATA7] = 0x124,
922 [PWRAP_SPMINF_STA] = 0x128,
923 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
924 [PWRAP_CIPHER_IV_SEL] = 0x130,
925 [PWRAP_CIPHER_EN] = 0x134,
926 [PWRAP_CIPHER_RDY] = 0x138,
927 [PWRAP_CIPHER_MODE] = 0x13c,
928 [PWRAP_CIPHER_SWRST] = 0x140,
929 [PWRAP_DCM_EN] = 0x144,
930 [PWRAP_DCM_DBC_PRD] = 0x148,
931 [PWRAP_SW_RST] = 0x168,
932 [PWRAP_OP_TYPE] = 0x16c,
933 [PWRAP_MSB_FIRST] = 0x170,
934 };
935
936 enum pmic_type {
937 PMIC_MT6323,
938 PMIC_MT6351,
939 PMIC_MT6357,
940 PMIC_MT6358,
941 PMIC_MT6380,
942 PMIC_MT6397,
943 };
944
945 enum pwrap_type {
946 PWRAP_MT2701,
947 PWRAP_MT6765,
948 PWRAP_MT6797,
949 PWRAP_MT7622,
950 PWRAP_MT8135,
951 PWRAP_MT8173,
952 PWRAP_MT8183,
953 PWRAP_MT8516,
954 };
955
956 struct pmic_wrapper;
957 struct pwrap_slv_type {
958 const u32 *dew_regs;
959 enum pmic_type type;
960 const struct regmap_config *regmap;
961 /* Flags indicating the capability for the target slave */
962 u32 caps;
963 /*
964 * pwrap operations are highly associated with the PMIC types,
965 * so the pointers added increases flexibility allowing determination
966 * which type is used by the detection through device tree.
967 */
968 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
969 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
970 };
971
972 struct pmic_wrapper {
973 struct device *dev;
974 void __iomem *base;
975 struct regmap *regmap;
976 const struct pmic_wrapper_type *master;
977 const struct pwrap_slv_type *slave;
978 struct clk *clk_spi;
979 struct clk *clk_wrap;
980 struct reset_control *rstc;
981
982 struct reset_control *rstc_bridge;
983 void __iomem *bridge_base;
984 };
985
986 struct pmic_wrapper_type {
987 int *regs;
988 enum pwrap_type type;
989 u32 arb_en_all;
990 u32 int_en_all;
991 u32 int1_en_all;
992 u32 spi_w;
993 u32 wdt_src;
994 /* Flags indicating the capability for the target pwrap */
995 u32 caps;
996 int (*init_reg_clock)(struct pmic_wrapper *wrp);
997 int (*init_soc_specific)(struct pmic_wrapper *wrp);
998 };
999
1000 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
1001 {
1002 return readl(wrp->base + wrp->master->regs[reg]);
1003 }
1004
1005 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
1006 {
1007 writel(val, wrp->base + wrp->master->regs[reg]);
1008 }
1009
1010 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
1011 {
1012 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1013
1014 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
1015 }
1016
1017 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
1018 {
1019 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1020
1021 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
1022 }
1023
1024 /*
1025 * Timeout issue sometimes caused by the last read command
1026 * failed because pmic wrap could not got the FSM_VLDCLR
1027 * in time after finishing WACS2_CMD. It made state machine
1028 * still on FSM_VLDCLR and timeout next time.
1029 * Check the status of FSM and clear the vldclr to recovery the
1030 * error.
1031 */
1032 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
1033 {
1034 if (pwrap_is_fsm_vldclr(wrp))
1035 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1036 }
1037
1038 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
1039 {
1040 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
1041 }
1042
1043 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
1044 {
1045 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1046
1047 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
1048 (val & PWRAP_STATE_SYNC_IDLE0);
1049 }
1050
1051 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
1052 bool (*fp)(struct pmic_wrapper *))
1053 {
1054 unsigned long timeout;
1055
1056 timeout = jiffies + usecs_to_jiffies(10000);
1057
1058 do {
1059 if (time_after(jiffies, timeout))
1060 return fp(wrp) ? 0 : -ETIMEDOUT;
1061 if (fp(wrp))
1062 return 0;
1063 } while (1);
1064 }
1065
1066 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1067 {
1068 int ret;
1069
1070 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1071 if (ret) {
1072 pwrap_leave_fsm_vldclr(wrp);
1073 return ret;
1074 }
1075
1076 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
1077
1078 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1079 if (ret)
1080 return ret;
1081
1082 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
1083
1084 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1085
1086 return 0;
1087 }
1088
1089 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1090 {
1091 int ret, msb;
1092
1093 *rdata = 0;
1094 for (msb = 0; msb < 2; msb++) {
1095 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1096 if (ret) {
1097 pwrap_leave_fsm_vldclr(wrp);
1098 return ret;
1099 }
1100
1101 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
1102 PWRAP_WACS2_CMD);
1103
1104 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1105 if (ret)
1106 return ret;
1107
1108 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
1109 PWRAP_WACS2_RDATA)) << (16 * msb));
1110
1111 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1112 }
1113
1114 return 0;
1115 }
1116
1117 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1118 {
1119 return wrp->slave->pwrap_read(wrp, adr, rdata);
1120 }
1121
1122 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1123 {
1124 int ret;
1125
1126 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1127 if (ret) {
1128 pwrap_leave_fsm_vldclr(wrp);
1129 return ret;
1130 }
1131
1132 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
1133 PWRAP_WACS2_CMD);
1134
1135 return 0;
1136 }
1137
1138 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1139 {
1140 int ret, msb, rdata;
1141
1142 for (msb = 0; msb < 2; msb++) {
1143 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1144 if (ret) {
1145 pwrap_leave_fsm_vldclr(wrp);
1146 return ret;
1147 }
1148
1149 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1150 ((wdata >> (msb * 16)) & 0xffff),
1151 PWRAP_WACS2_CMD);
1152
1153 /*
1154 * The pwrap_read operation is the requirement of hardware used
1155 * for the synchronization between two successive 16-bit
1156 * pwrap_writel operations composing one 32-bit bus writing.
1157 * Otherwise, we'll find the result fails on the lower 16-bit
1158 * pwrap writing.
1159 */
1160 if (!msb)
1161 pwrap_read(wrp, adr, &rdata);
1162 }
1163
1164 return 0;
1165 }
1166
1167 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1168 {
1169 return wrp->slave->pwrap_write(wrp, adr, wdata);
1170 }
1171
1172 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
1173 {
1174 return pwrap_read(context, adr, rdata);
1175 }
1176
1177 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
1178 {
1179 return pwrap_write(context, adr, wdata);
1180 }
1181
1182 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1183 {
1184 int ret, i;
1185
1186 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1187 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1188 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1189 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1190 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1191
1192 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1193 PWRAP_MAN_CMD);
1194 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1195 PWRAP_MAN_CMD);
1196 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1197 PWRAP_MAN_CMD);
1198
1199 for (i = 0; i < 4; i++)
1200 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1201 PWRAP_MAN_CMD);
1202
1203 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
1204 if (ret) {
1205 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1206 return ret;
1207 }
1208
1209 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1210 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1211
1212 return 0;
1213 }
1214
1215 /*
1216 * pwrap_init_sidly - configure serial input delay
1217 *
1218 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
1219 * delay. Do a read test with all possible values and chose the best delay.
1220 */
1221 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1222 {
1223 u32 rdata;
1224 u32 i;
1225 u32 pass = 0;
1226 signed char dly[16] = {
1227 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
1228 };
1229
1230 for (i = 0; i < 4; i++) {
1231 pwrap_writel(wrp, i, PWRAP_SIDLY);
1232 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
1233 &rdata);
1234 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
1235 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1236 pass |= 1 << i;
1237 }
1238 }
1239
1240 if (dly[pass] < 0) {
1241 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1242 pass);
1243 return -EIO;
1244 }
1245
1246 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1247
1248 return 0;
1249 }
1250
1251 static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1252 {
1253 int ret;
1254 u32 rdata;
1255
1256 /* Enable dual IO mode */
1257 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1258
1259 /* Check IDLE & INIT_DONE in advance */
1260 ret = pwrap_wait_for_state(wrp,
1261 pwrap_is_fsm_idle_and_sync_idle);
1262 if (ret) {
1263 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1264 return ret;
1265 }
1266
1267 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1268
1269 /* Read Test */
1270 pwrap_read(wrp,
1271 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1272 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
1273 dev_err(wrp->dev,
1274 "Read failed on DIO mode: 0x%04x!=0x%04x\n",
1275 PWRAP_DEW_READ_TEST_VAL, rdata);
1276 return -EFAULT;
1277 }
1278
1279 return 0;
1280 }
1281
1282 /*
1283 * pwrap_init_chip_select_ext is used to configure CS extension time for each
1284 * phase during data transactions on the pwrap bus.
1285 */
1286 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1287 u8 hext_read, u8 lext_start,
1288 u8 lext_end)
1289 {
1290 /*
1291 * After finishing a write and read transaction, extends CS high time
1292 * to be at least xT of BUS CLK as hext_write and hext_read specifies
1293 * respectively.
1294 */
1295 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1296 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1297
1298 /*
1299 * Extends CS low time after CSL and before CSH command to be at
1300 * least xT of BUS CLK as lext_start and lext_end specifies
1301 * respectively.
1302 */
1303 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1304 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1305 }
1306
1307 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1308 {
1309 switch (wrp->master->type) {
1310 case PWRAP_MT8173:
1311 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1312 break;
1313 case PWRAP_MT8135:
1314 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1315 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1316 break;
1317 default:
1318 break;
1319 }
1320
1321 return 0;
1322 }
1323
1324 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1325 {
1326 switch (wrp->slave->type) {
1327 case PMIC_MT6397:
1328 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1329 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1330 break;
1331
1332 case PMIC_MT6323:
1333 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1334 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1335 0x8);
1336 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1337 break;
1338 default:
1339 break;
1340 }
1341
1342 return 0;
1343 }
1344
1345 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1346 {
1347 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1348 }
1349
1350 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1351 {
1352 u32 rdata;
1353 int ret;
1354
1355 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
1356 &rdata);
1357 if (ret)
1358 return false;
1359
1360 return rdata == 1;
1361 }
1362
1363 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1364 {
1365 int ret;
1366 u32 rdata = 0;
1367
1368 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1369 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1370 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1371 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1372
1373 switch (wrp->master->type) {
1374 case PWRAP_MT8135:
1375 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1376 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1377 break;
1378 case PWRAP_MT2701:
1379 case PWRAP_MT6765:
1380 case PWRAP_MT6797:
1381 case PWRAP_MT8173:
1382 case PWRAP_MT8516:
1383 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1384 break;
1385 case PWRAP_MT7622:
1386 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1387 break;
1388 case PWRAP_MT8183:
1389 break;
1390 }
1391
1392 /* Config cipher mode @PMIC */
1393 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1394 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1395 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1396 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1397
1398 switch (wrp->slave->type) {
1399 case PMIC_MT6397:
1400 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1401 0x1);
1402 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1403 0x1);
1404 break;
1405 case PMIC_MT6323:
1406 case PMIC_MT6351:
1407 case PMIC_MT6357:
1408 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1409 0x1);
1410 break;
1411 default:
1412 break;
1413 }
1414
1415 /* wait for cipher data ready@AP */
1416 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
1417 if (ret) {
1418 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1419 return ret;
1420 }
1421
1422 /* wait for cipher data ready@PMIC */
1423 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
1424 if (ret) {
1425 dev_err(wrp->dev,
1426 "timeout waiting for cipher data ready@PMIC\n");
1427 return ret;
1428 }
1429
1430 /* wait for cipher mode idle */
1431 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1432 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
1433 if (ret) {
1434 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1435 return ret;
1436 }
1437
1438 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1439
1440 /* Write Test */
1441 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1442 PWRAP_DEW_WRITE_TEST_VAL) ||
1443 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1444 &rdata) ||
1445 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1446 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1447 return -EFAULT;
1448 }
1449
1450 return 0;
1451 }
1452
1453 static int pwrap_init_security(struct pmic_wrapper *wrp)
1454 {
1455 int ret;
1456
1457 /* Enable encryption */
1458 ret = pwrap_init_cipher(wrp);
1459 if (ret)
1460 return ret;
1461
1462 /* Signature checking - using CRC */
1463 if (pwrap_write(wrp,
1464 wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
1465 return -EFAULT;
1466
1467 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1468 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1469 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
1470 PWRAP_SIG_ADR);
1471 pwrap_writel(wrp,
1472 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1473
1474 return 0;
1475 }
1476
1477 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1478 {
1479 /* enable pwrap events and pwrap bridge in AP side */
1480 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1481 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1482 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1483 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1484 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1485 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1486 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1487 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1488 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1489
1490 /* enable PMIC event out and sources */
1491 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1492 0x1) ||
1493 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1494 0xffff)) {
1495 dev_err(wrp->dev, "enable dewrap fail\n");
1496 return -EFAULT;
1497 }
1498
1499 return 0;
1500 }
1501
1502 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1503 {
1504 /* PMIC_DEWRAP enables */
1505 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1506 0x1) ||
1507 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1508 0xffff)) {
1509 dev_err(wrp->dev, "enable dewrap fail\n");
1510 return -EFAULT;
1511 }
1512
1513 return 0;
1514 }
1515
1516 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1517 {
1518 /* GPS_INTF initialization */
1519 switch (wrp->slave->type) {
1520 case PMIC_MT6323:
1521 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
1522 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
1523 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
1524 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
1525 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
1526 break;
1527 default:
1528 break;
1529 }
1530
1531 return 0;
1532 }
1533
1534 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1535 {
1536 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1537 /* enable 2wire SPI master */
1538 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1539
1540 return 0;
1541 }
1542
1543 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
1544 {
1545 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
1546
1547 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1548 pwrap_writel(wrp, 1, PWRAP_CRC_EN);
1549 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
1550 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
1551
1552 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
1553 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
1554 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
1555 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
1556
1557 return 0;
1558 }
1559
1560 static int pwrap_init(struct pmic_wrapper *wrp)
1561 {
1562 int ret;
1563
1564 if (wrp->rstc)
1565 reset_control_reset(wrp->rstc);
1566 if (wrp->rstc_bridge)
1567 reset_control_reset(wrp->rstc_bridge);
1568
1569 if (wrp->master->type == PWRAP_MT8173) {
1570 /* Enable DCM */
1571 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
1572 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1573 }
1574
1575 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1576 /* Reset SPI slave */
1577 ret = pwrap_reset_spislave(wrp);
1578 if (ret)
1579 return ret;
1580 }
1581
1582 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
1583
1584 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1585
1586 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
1587
1588 ret = wrp->master->init_reg_clock(wrp);
1589 if (ret)
1590 return ret;
1591
1592 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1593 /* Setup serial input delay */
1594 ret = pwrap_init_sidly(wrp);
1595 if (ret)
1596 return ret;
1597 }
1598
1599 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
1600 /* Enable dual I/O mode */
1601 ret = pwrap_init_dual_io(wrp);
1602 if (ret)
1603 return ret;
1604 }
1605
1606 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
1607 /* Enable security on bus */
1608 ret = pwrap_init_security(wrp);
1609 if (ret)
1610 return ret;
1611 }
1612
1613 if (wrp->master->type == PWRAP_MT8135)
1614 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
1615
1616 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
1617 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
1618 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1619 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
1620 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1621
1622 if (wrp->master->init_soc_specific) {
1623 ret = wrp->master->init_soc_specific(wrp);
1624 if (ret)
1625 return ret;
1626 }
1627
1628 /* Setup the init done registers */
1629 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
1630 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
1631 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
1632
1633 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1634 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
1635 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
1636 }
1637
1638 return 0;
1639 }
1640
1641 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
1642 {
1643 u32 rdata;
1644 struct pmic_wrapper *wrp = dev_id;
1645
1646 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1647 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1648 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1649
1650 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
1651 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
1652 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
1653 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
1654 }
1655
1656 return IRQ_HANDLED;
1657 }
1658
1659 static const struct regmap_config pwrap_regmap_config16 = {
1660 .reg_bits = 16,
1661 .val_bits = 16,
1662 .reg_stride = 2,
1663 .reg_read = pwrap_regmap_read,
1664 .reg_write = pwrap_regmap_write,
1665 .max_register = 0xffff,
1666 };
1667
1668 static const struct regmap_config pwrap_regmap_config32 = {
1669 .reg_bits = 32,
1670 .val_bits = 32,
1671 .reg_stride = 4,
1672 .reg_read = pwrap_regmap_read,
1673 .reg_write = pwrap_regmap_write,
1674 .max_register = 0xffff,
1675 };
1676
1677 static const struct pwrap_slv_type pmic_mt6323 = {
1678 .dew_regs = mt6323_regs,
1679 .type = PMIC_MT6323,
1680 .regmap = &pwrap_regmap_config16,
1681 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1682 PWRAP_SLV_CAP_SECURITY,
1683 .pwrap_read = pwrap_read16,
1684 .pwrap_write = pwrap_write16,
1685 };
1686
1687 static const struct pwrap_slv_type pmic_mt6351 = {
1688 .dew_regs = mt6351_regs,
1689 .type = PMIC_MT6351,
1690 .regmap = &pwrap_regmap_config16,
1691 .caps = 0,
1692 .pwrap_read = pwrap_read16,
1693 .pwrap_write = pwrap_write16,
1694 };
1695
1696 static const struct pwrap_slv_type pmic_mt6357 = {
1697 .dew_regs = mt6357_regs,
1698 .type = PMIC_MT6357,
1699 .regmap = &pwrap_regmap_config16,
1700 .caps = 0,
1701 .pwrap_read = pwrap_read16,
1702 .pwrap_write = pwrap_write16,
1703 };
1704
1705 static const struct pwrap_slv_type pmic_mt6358 = {
1706 .dew_regs = mt6358_regs,
1707 .type = PMIC_MT6358,
1708 .regmap = &pwrap_regmap_config16,
1709 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
1710 .pwrap_read = pwrap_read16,
1711 .pwrap_write = pwrap_write16,
1712 };
1713
1714 static const struct pwrap_slv_type pmic_mt6380 = {
1715 .dew_regs = NULL,
1716 .type = PMIC_MT6380,
1717 .regmap = &pwrap_regmap_config32,
1718 .caps = 0,
1719 .pwrap_read = pwrap_read32,
1720 .pwrap_write = pwrap_write32,
1721 };
1722
1723 static const struct pwrap_slv_type pmic_mt6397 = {
1724 .dew_regs = mt6397_regs,
1725 .type = PMIC_MT6397,
1726 .regmap = &pwrap_regmap_config16,
1727 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1728 PWRAP_SLV_CAP_SECURITY,
1729 .pwrap_read = pwrap_read16,
1730 .pwrap_write = pwrap_write16,
1731 };
1732
1733 static const struct of_device_id of_slave_match_tbl[] = {
1734 {
1735 .compatible = "mediatek,mt6323",
1736 .data = &pmic_mt6323,
1737 }, {
1738 .compatible = "mediatek,mt6351",
1739 .data = &pmic_mt6351,
1740 }, {
1741 .compatible = "mediatek,mt6357",
1742 .data = &pmic_mt6357,
1743 }, {
1744 .compatible = "mediatek,mt6358",
1745 .data = &pmic_mt6358,
1746 }, {
1747 /* The MT6380 PMIC only implements a regulator, so we bind it
1748 * directly instead of using a MFD.
1749 */
1750 .compatible = "mediatek,mt6380-regulator",
1751 .data = &pmic_mt6380,
1752 }, {
1753 .compatible = "mediatek,mt6397",
1754 .data = &pmic_mt6397,
1755 }, {
1756 /* sentinel */
1757 }
1758 };
1759 MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
1760
1761 static const struct pmic_wrapper_type pwrap_mt2701 = {
1762 .regs = mt2701_regs,
1763 .type = PWRAP_MT2701,
1764 .arb_en_all = 0x3f,
1765 .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1766 .int1_en_all = 0,
1767 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
1768 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1769 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1770 .init_reg_clock = pwrap_mt2701_init_reg_clock,
1771 .init_soc_specific = pwrap_mt2701_init_soc_specific,
1772 };
1773
1774 static const struct pmic_wrapper_type pwrap_mt6765 = {
1775 .regs = mt6765_regs,
1776 .type = PWRAP_MT6765,
1777 .arb_en_all = 0x3fd35,
1778 .int_en_all = 0xffffffff,
1779 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1780 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1781 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1782 .init_reg_clock = pwrap_common_init_reg_clock,
1783 .init_soc_specific = NULL,
1784 };
1785
1786 static const struct pmic_wrapper_type pwrap_mt6797 = {
1787 .regs = mt6797_regs,
1788 .type = PWRAP_MT6797,
1789 .arb_en_all = 0x01fff,
1790 .int_en_all = 0xffffffc6,
1791 .int1_en_all = 0,
1792 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1793 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1794 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1795 .init_reg_clock = pwrap_common_init_reg_clock,
1796 .init_soc_specific = NULL,
1797 };
1798
1799 static const struct pmic_wrapper_type pwrap_mt7622 = {
1800 .regs = mt7622_regs,
1801 .type = PWRAP_MT7622,
1802 .arb_en_all = 0xff,
1803 .int_en_all = ~(u32)BIT(31),
1804 .int1_en_all = 0,
1805 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1806 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1807 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1808 .init_reg_clock = pwrap_common_init_reg_clock,
1809 .init_soc_specific = pwrap_mt7622_init_soc_specific,
1810 };
1811
1812 static const struct pmic_wrapper_type pwrap_mt8135 = {
1813 .regs = mt8135_regs,
1814 .type = PWRAP_MT8135,
1815 .arb_en_all = 0x1ff,
1816 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1817 .int1_en_all = 0,
1818 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1819 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1820 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1821 .init_reg_clock = pwrap_common_init_reg_clock,
1822 .init_soc_specific = pwrap_mt8135_init_soc_specific,
1823 };
1824
1825 static const struct pmic_wrapper_type pwrap_mt8173 = {
1826 .regs = mt8173_regs,
1827 .type = PWRAP_MT8173,
1828 .arb_en_all = 0x3f,
1829 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1830 .int1_en_all = 0,
1831 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1832 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
1833 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1834 .init_reg_clock = pwrap_common_init_reg_clock,
1835 .init_soc_specific = pwrap_mt8173_init_soc_specific,
1836 };
1837
1838 static const struct pmic_wrapper_type pwrap_mt8183 = {
1839 .regs = mt8183_regs,
1840 .type = PWRAP_MT8183,
1841 .arb_en_all = 0x3fa75,
1842 .int_en_all = 0xffffffff,
1843 .int1_en_all = 0xeef7ffff,
1844 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1845 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1846 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
1847 .init_reg_clock = pwrap_common_init_reg_clock,
1848 .init_soc_specific = pwrap_mt8183_init_soc_specific,
1849 };
1850
1851 static struct pmic_wrapper_type pwrap_mt8516 = {
1852 .regs = mt8516_regs,
1853 .type = PWRAP_MT8516,
1854 .arb_en_all = 0xff,
1855 .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1856 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1857 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1858 .caps = PWRAP_CAP_DCM,
1859 .init_reg_clock = pwrap_mt2701_init_reg_clock,
1860 .init_soc_specific = NULL,
1861 };
1862
1863 static const struct of_device_id of_pwrap_match_tbl[] = {
1864 {
1865 .compatible = "mediatek,mt2701-pwrap",
1866 .data = &pwrap_mt2701,
1867 }, {
1868 .compatible = "mediatek,mt6765-pwrap",
1869 .data = &pwrap_mt6765,
1870 }, {
1871 .compatible = "mediatek,mt6797-pwrap",
1872 .data = &pwrap_mt6797,
1873 }, {
1874 .compatible = "mediatek,mt7622-pwrap",
1875 .data = &pwrap_mt7622,
1876 }, {
1877 .compatible = "mediatek,mt8135-pwrap",
1878 .data = &pwrap_mt8135,
1879 }, {
1880 .compatible = "mediatek,mt8173-pwrap",
1881 .data = &pwrap_mt8173,
1882 }, {
1883 .compatible = "mediatek,mt8183-pwrap",
1884 .data = &pwrap_mt8183,
1885 }, {
1886 .compatible = "mediatek,mt8516-pwrap",
1887 .data = &pwrap_mt8516,
1888 }, {
1889 /* sentinel */
1890 }
1891 };
1892 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
1893
1894 static int pwrap_probe(struct platform_device *pdev)
1895 {
1896 int ret, irq;
1897 struct pmic_wrapper *wrp;
1898 struct device_node *np = pdev->dev.of_node;
1899 const struct of_device_id *of_slave_id = NULL;
1900 struct resource *res;
1901
1902 if (np->child)
1903 of_slave_id = of_match_node(of_slave_match_tbl, np->child);
1904
1905 if (!of_slave_id) {
1906 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
1907 return -EINVAL;
1908 }
1909
1910 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
1911 if (!wrp)
1912 return -ENOMEM;
1913
1914 platform_set_drvdata(pdev, wrp);
1915
1916 wrp->master = of_device_get_match_data(&pdev->dev);
1917 wrp->slave = of_slave_id->data;
1918 wrp->dev = &pdev->dev;
1919
1920 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
1921 wrp->base = devm_ioremap_resource(wrp->dev, res);
1922 if (IS_ERR(wrp->base))
1923 return PTR_ERR(wrp->base);
1924
1925 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
1926 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
1927 if (IS_ERR(wrp->rstc)) {
1928 ret = PTR_ERR(wrp->rstc);
1929 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
1930 return ret;
1931 }
1932 }
1933
1934 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1935 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1936 "pwrap-bridge");
1937 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
1938 if (IS_ERR(wrp->bridge_base))
1939 return PTR_ERR(wrp->bridge_base);
1940
1941 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
1942 "pwrap-bridge");
1943 if (IS_ERR(wrp->rstc_bridge)) {
1944 ret = PTR_ERR(wrp->rstc_bridge);
1945 dev_dbg(wrp->dev,
1946 "cannot get pwrap-bridge reset: %d\n", ret);
1947 return ret;
1948 }
1949 }
1950
1951 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
1952 if (IS_ERR(wrp->clk_spi)) {
1953 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
1954 PTR_ERR(wrp->clk_spi));
1955 return PTR_ERR(wrp->clk_spi);
1956 }
1957
1958 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
1959 if (IS_ERR(wrp->clk_wrap)) {
1960 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
1961 PTR_ERR(wrp->clk_wrap));
1962 return PTR_ERR(wrp->clk_wrap);
1963 }
1964
1965 ret = clk_prepare_enable(wrp->clk_spi);
1966 if (ret)
1967 return ret;
1968
1969 ret = clk_prepare_enable(wrp->clk_wrap);
1970 if (ret)
1971 goto err_out1;
1972
1973 /* Enable internal dynamic clock */
1974 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
1975 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
1976 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1977 }
1978
1979 /*
1980 * The PMIC could already be initialized by the bootloader.
1981 * Skip initialization here in this case.
1982 */
1983 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
1984 ret = pwrap_init(wrp);
1985 if (ret) {
1986 dev_dbg(wrp->dev, "init failed with %d\n", ret);
1987 goto err_out2;
1988 }
1989 }
1990
1991 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
1992 dev_dbg(wrp->dev, "initialization isn't finished\n");
1993 ret = -ENODEV;
1994 goto err_out2;
1995 }
1996
1997 /* Initialize watchdog, may not be done by the bootloader */
1998 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
1999 /*
2000 * Since STAUPD was not used on mt8173 platform,
2001 * so STAUPD of WDT_SRC which should be turned off
2002 */
2003 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2004 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
2005 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
2006
2007 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
2008 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2009 /*
2010 * We add INT1 interrupt to handle starvation and request exception
2011 * If we support it, we should enable it here.
2012 */
2013 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2014 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
2015
2016 irq = platform_get_irq(pdev, 0);
2017 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
2018 IRQF_TRIGGER_HIGH,
2019 "mt-pmic-pwrap", wrp);
2020 if (ret)
2021 goto err_out2;
2022
2023 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
2024 if (IS_ERR(wrp->regmap)) {
2025 ret = PTR_ERR(wrp->regmap);
2026 goto err_out2;
2027 }
2028
2029 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
2030 if (ret) {
2031 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
2032 np);
2033 goto err_out2;
2034 }
2035
2036 return 0;
2037
2038 err_out2:
2039 clk_disable_unprepare(wrp->clk_wrap);
2040 err_out1:
2041 clk_disable_unprepare(wrp->clk_spi);
2042
2043 return ret;
2044 }
2045
2046 static struct platform_driver pwrap_drv = {
2047 .driver = {
2048 .name = "mt-pmic-pwrap",
2049 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
2050 },
2051 .probe = pwrap_probe,
2052 };
2053
2054 module_platform_driver(pwrap_drv);
2055
2056 MODULE_AUTHOR("Flora Fu, MediaTek");
2057 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
2058 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support