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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / soc / tegra / pmc.c
blob1699dda6b393a664f5b74dadfa315c244a7a80c4
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/soc/tegra/pmc.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Colin Cross <ccross@google.com>
10 */
11
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
13
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk/tegra.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/iopoll.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/of_address.h>
28 #include <linux/of_clk.h>
29 #include <linux/of.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinconf.h>
34 #include <linux/pinctrl/pinctrl.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_domain.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42
43 #include <soc/tegra/common.h>
44 #include <soc/tegra/fuse.h>
45 #include <soc/tegra/pmc.h>
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
49 #include <dt-bindings/gpio/tegra186-gpio.h>
50 #include <dt-bindings/gpio/tegra194-gpio.h>
51
52 #define PMC_CNTRL 0x0
53 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
54 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
55 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
56 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
57 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
58 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
59 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
60 #define PMC_CNTRL_MAIN_RST BIT(4)
61
62 #define PMC_WAKE_MASK 0x0c
63 #define PMC_WAKE_LEVEL 0x10
64 #define PMC_WAKE_STATUS 0x14
65 #define PMC_SW_WAKE_STATUS 0x18
66
67 #define DPD_SAMPLE 0x020
68 #define DPD_SAMPLE_ENABLE BIT(0)
69 #define DPD_SAMPLE_DISABLE (0 << 0)
70
71 #define PWRGATE_TOGGLE 0x30
72 #define PWRGATE_TOGGLE_START BIT(8)
73
74 #define REMOVE_CLAMPING 0x34
75
76 #define PWRGATE_STATUS 0x38
77
78 #define PMC_IMPL_E_33V_PWR 0x40
79
80 #define PMC_PWR_DET 0x48
81
82 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
83 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
84 #define PMC_SCRATCH0_MODE_RCM BIT(1)
85 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
86 PMC_SCRATCH0_MODE_BOOTLOADER | \
87 PMC_SCRATCH0_MODE_RCM)
88
89 #define PMC_CPUPWRGOOD_TIMER 0xc8
90 #define PMC_CPUPWROFF_TIMER 0xcc
91 #define PMC_COREPWRGOOD_TIMER 0x3c
92 #define PMC_COREPWROFF_TIMER 0xe0
93
94 #define PMC_PWR_DET_VALUE 0xe4
95
96 #define PMC_SCRATCH41 0x140
97
98 #define PMC_WAKE2_MASK 0x160
99 #define PMC_WAKE2_LEVEL 0x164
100 #define PMC_WAKE2_STATUS 0x168
101 #define PMC_SW_WAKE2_STATUS 0x16c
102
103 #define PMC_SENSOR_CTRL 0x1b0
104 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
105 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
106
107 #define PMC_RST_STATUS_POR 0
108 #define PMC_RST_STATUS_WATCHDOG 1
109 #define PMC_RST_STATUS_SENSOR 2
110 #define PMC_RST_STATUS_SW_MAIN 3
111 #define PMC_RST_STATUS_LP0 4
112 #define PMC_RST_STATUS_AOTAG 5
113
114 #define IO_DPD_REQ 0x1b8
115 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
116 #define IO_DPD_REQ_CODE_OFF (1U << 30)
117 #define IO_DPD_REQ_CODE_ON (2U << 30)
118 #define IO_DPD_REQ_CODE_MASK (3U << 30)
119
120 #define IO_DPD_STATUS 0x1bc
121 #define IO_DPD2_REQ 0x1c0
122 #define IO_DPD2_STATUS 0x1c4
123 #define SEL_DPD_TIM 0x1c8
124
125 #define PMC_SCRATCH54 0x258
126 #define PMC_SCRATCH54_DATA_SHIFT 8
127 #define PMC_SCRATCH54_ADDR_SHIFT 0
128
129 #define PMC_SCRATCH55 0x25c
130 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
131 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
132 #define PMC_SCRATCH55_PINMUX_SHIFT 24
133 #define PMC_SCRATCH55_16BITOP BIT(15)
134 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
135 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
136
137 #define GPU_RG_CNTRL 0x2d4
138
139 /* Tegra186 and later */
140 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
141 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
142 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
143 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
144 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
145 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
146 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
147 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
148 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
149
150 #define WAKE_AOWAKE_CTRL 0x4f4
151 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
152
153 /* for secure PMC */
154 #define TEGRA_SMC_PMC 0xc2fffe00
155 #define TEGRA_SMC_PMC_READ 0xaa
156 #define TEGRA_SMC_PMC_WRITE 0xbb
157
158 struct tegra_powergate {
159 struct generic_pm_domain genpd;
160 struct tegra_pmc *pmc;
161 unsigned int id;
162 struct clk **clks;
163 unsigned int num_clks;
164 struct reset_control *reset;
165 };
166
167 struct tegra_io_pad_soc {
168 enum tegra_io_pad id;
169 unsigned int dpd;
170 unsigned int voltage;
171 const char *name;
172 };
173
174 struct tegra_pmc_regs {
175 unsigned int scratch0;
176 unsigned int dpd_req;
177 unsigned int dpd_status;
178 unsigned int dpd2_req;
179 unsigned int dpd2_status;
180 unsigned int rst_status;
181 unsigned int rst_source_shift;
182 unsigned int rst_source_mask;
183 unsigned int rst_level_shift;
184 unsigned int rst_level_mask;
185 };
186
187 struct tegra_wake_event {
188 const char *name;
189 unsigned int id;
190 unsigned int irq;
191 struct {
192 unsigned int instance;
193 unsigned int pin;
194 } gpio;
195 };
196
197 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
198 { \
199 .name = _name, \
200 .id = _id, \
201 .irq = _irq, \
202 .gpio = { \
203 .instance = UINT_MAX, \
204 .pin = UINT_MAX, \
205 }, \
206 }
207
208 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
209 { \
210 .name = _name, \
211 .id = _id, \
212 .irq = 0, \
213 .gpio = { \
214 .instance = _instance, \
215 .pin = _pin, \
216 }, \
217 }
218
219 struct tegra_pmc_soc {
220 unsigned int num_powergates;
221 const char *const *powergates;
222 unsigned int num_cpu_powergates;
223 const u8 *cpu_powergates;
224
225 bool has_tsense_reset;
226 bool has_gpu_clamps;
227 bool needs_mbist_war;
228 bool has_impl_33v_pwr;
229 bool maybe_tz_only;
230
231 const struct tegra_io_pad_soc *io_pads;
232 unsigned int num_io_pads;
233
234 const struct pinctrl_pin_desc *pin_descs;
235 unsigned int num_pin_descs;
236
237 const struct tegra_pmc_regs *regs;
238 void (*init)(struct tegra_pmc *pmc);
239 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
240 struct device_node *np,
241 bool invert);
242 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
243 int (*irq_set_type)(struct irq_data *data, unsigned int type);
244
245 const char * const *reset_sources;
246 unsigned int num_reset_sources;
247 const char * const *reset_levels;
248 unsigned int num_reset_levels;
249
250 /*
251 * These describe events that can wake the system from sleep (i.e.
252 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
253 * are dealt with in the LIC.
254 */
255 const struct tegra_wake_event *wake_events;
256 unsigned int num_wake_events;
257 };
258
259 static const char * const tegra186_reset_sources[] = {
260 "SYS_RESET",
261 "AOWDT",
262 "MCCPLEXWDT",
263 "BPMPWDT",
264 "SCEWDT",
265 "SPEWDT",
266 "APEWDT",
267 "BCCPLEXWDT",
268 "SENSOR",
269 "AOTAG",
270 "VFSENSOR",
271 "SWREST",
272 "SC7",
273 "HSM",
274 "CORESIGHT"
275 };
276
277 static const char * const tegra186_reset_levels[] = {
278 "L0", "L1", "L2", "WARM"
279 };
280
281 static const char * const tegra30_reset_sources[] = {
282 "POWER_ON_RESET",
283 "WATCHDOG",
284 "SENSOR",
285 "SW_MAIN",
286 "LP0"
287 };
288
289 static const char * const tegra210_reset_sources[] = {
290 "POWER_ON_RESET",
291 "WATCHDOG",
292 "SENSOR",
293 "SW_MAIN",
294 "LP0",
295 "AOTAG"
296 };
297
298 /**
299 * struct tegra_pmc - NVIDIA Tegra PMC
300 * @dev: pointer to PMC device structure
301 * @base: pointer to I/O remapped register region
302 * @wake: pointer to I/O remapped region for WAKE registers
303 * @aotag: pointer to I/O remapped region for AOTAG registers
304 * @scratch: pointer to I/O remapped region for scratch registers
305 * @clk: pointer to pclk clock
306 * @soc: pointer to SoC data structure
307 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
308 * @debugfs: pointer to debugfs entry
309 * @rate: currently configured rate of pclk
310 * @suspend_mode: lowest suspend mode available
311 * @cpu_good_time: CPU power good time (in microseconds)
312 * @cpu_off_time: CPU power off time (in microsecends)
313 * @core_osc_time: core power good OSC time (in microseconds)
314 * @core_pmu_time: core power good PMU time (in microseconds)
315 * @core_off_time: core power off time (in microseconds)
316 * @corereq_high: core power request is active-high
317 * @sysclkreq_high: system clock request is active-high
318 * @combined_req: combined power request for CPU & core
319 * @cpu_pwr_good_en: CPU power good signal is enabled
320 * @lp0_vec_phys: physical base address of the LP0 warm boot code
321 * @lp0_vec_size: size of the LP0 warm boot code
322 * @powergates_available: Bitmap of available power gates
323 * @powergates_lock: mutex for power gate register access
324 * @pctl_dev: pin controller exposed by the PMC
325 * @domain: IRQ domain provided by the PMC
326 * @irq: chip implementation for the IRQ domain
327 * @clk_nb: pclk clock changes handler
328 */
329 struct tegra_pmc {
330 struct device *dev;
331 void __iomem *base;
332 void __iomem *wake;
333 void __iomem *aotag;
334 void __iomem *scratch;
335 struct clk *clk;
336 struct dentry *debugfs;
337
338 const struct tegra_pmc_soc *soc;
339 bool tz_only;
340
341 unsigned long rate;
342
343 enum tegra_suspend_mode suspend_mode;
344 u32 cpu_good_time;
345 u32 cpu_off_time;
346 u32 core_osc_time;
347 u32 core_pmu_time;
348 u32 core_off_time;
349 bool corereq_high;
350 bool sysclkreq_high;
351 bool combined_req;
352 bool cpu_pwr_good_en;
353 u32 lp0_vec_phys;
354 u32 lp0_vec_size;
355 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
356
357 struct mutex powergates_lock;
358
359 struct pinctrl_dev *pctl_dev;
360
361 struct irq_domain *domain;
362 struct irq_chip irq;
363
364 struct notifier_block clk_nb;
365 };
366
367 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
368 .base = NULL,
369 .suspend_mode = TEGRA_SUSPEND_NONE,
370 };
371
372 static inline struct tegra_powergate *
373 to_powergate(struct generic_pm_domain *domain)
374 {
375 return container_of(domain, struct tegra_powergate, genpd);
376 }
377
378 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
379 {
380 struct arm_smccc_res res;
381
382 if (pmc->tz_only) {
383 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
384 0, 0, 0, &res);
385 if (res.a0) {
386 if (pmc->dev)
387 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
388 __func__, res.a0);
389 else
390 pr_warn("%s(): SMC failed: %lu\n", __func__,
391 res.a0);
392 }
393
394 return res.a1;
395 }
396
397 return readl(pmc->base + offset);
398 }
399
400 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
401 unsigned long offset)
402 {
403 struct arm_smccc_res res;
404
405 if (pmc->tz_only) {
406 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
407 value, 0, 0, 0, 0, &res);
408 if (res.a0) {
409 if (pmc->dev)
410 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
411 __func__, res.a0);
412 else
413 pr_warn("%s(): SMC failed: %lu\n", __func__,
414 res.a0);
415 }
416 } else {
417 writel(value, pmc->base + offset);
418 }
419 }
420
421 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
422 {
423 if (pmc->tz_only)
424 return tegra_pmc_readl(pmc, offset);
425
426 return readl(pmc->scratch + offset);
427 }
428
429 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
430 unsigned long offset)
431 {
432 if (pmc->tz_only)
433 tegra_pmc_writel(pmc, value, offset);
434 else
435 writel(value, pmc->scratch + offset);
436 }
437
438 /*
439 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
440 * This currently doesn't work because readx_poll_timeout() can only operate
441 * on functions that take a single argument.
442 */
443 static inline bool tegra_powergate_state(int id)
444 {
445 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
446 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
447 else
448 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
449 }
450
451 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
452 {
453 return (pmc->soc && pmc->soc->powergates[id]);
454 }
455
456 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
457 {
458 return test_bit(id, pmc->powergates_available);
459 }
460
461 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
462 {
463 unsigned int i;
464
465 if (!pmc || !pmc->soc || !name)
466 return -EINVAL;
467
468 for (i = 0; i < pmc->soc->num_powergates; i++) {
469 if (!tegra_powergate_is_valid(pmc, i))
470 continue;
471
472 if (!strcmp(name, pmc->soc->powergates[i]))
473 return i;
474 }
475
476 return -ENODEV;
477 }
478
479 /**
480 * tegra_powergate_set() - set the state of a partition
481 * @pmc: power management controller
482 * @id: partition ID
483 * @new_state: new state of the partition
484 */
485 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
486 bool new_state)
487 {
488 bool status;
489 int err;
490
491 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
492 return -EINVAL;
493
494 mutex_lock(&pmc->powergates_lock);
495
496 if (tegra_powergate_state(id) == new_state) {
497 mutex_unlock(&pmc->powergates_lock);
498 return 0;
499 }
500
501 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
502
503 err = readx_poll_timeout(tegra_powergate_state, id, status,
504 status == new_state, 10, 100000);
505
506 mutex_unlock(&pmc->powergates_lock);
507
508 return err;
509 }
510
511 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
512 unsigned int id)
513 {
514 u32 mask;
515
516 mutex_lock(&pmc->powergates_lock);
517
518 /*
519 * On Tegra124 and later, the clamps for the GPU are controlled by a
520 * separate register (with different semantics).
521 */
522 if (id == TEGRA_POWERGATE_3D) {
523 if (pmc->soc->has_gpu_clamps) {
524 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
525 goto out;
526 }
527 }
528
529 /*
530 * Tegra 2 has a bug where PCIE and VDE clamping masks are
531 * swapped relatively to the partition ids
532 */
533 if (id == TEGRA_POWERGATE_VDEC)
534 mask = (1 << TEGRA_POWERGATE_PCIE);
535 else if (id == TEGRA_POWERGATE_PCIE)
536 mask = (1 << TEGRA_POWERGATE_VDEC);
537 else
538 mask = (1 << id);
539
540 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
541
542 out:
543 mutex_unlock(&pmc->powergates_lock);
544
545 return 0;
546 }
547
548 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
549 {
550 unsigned int i;
551
552 for (i = 0; i < pg->num_clks; i++)
553 clk_disable_unprepare(pg->clks[i]);
554 }
555
556 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
557 {
558 unsigned int i;
559 int err;
560
561 for (i = 0; i < pg->num_clks; i++) {
562 err = clk_prepare_enable(pg->clks[i]);
563 if (err)
564 goto out;
565 }
566
567 return 0;
568
569 out:
570 while (i--)
571 clk_disable_unprepare(pg->clks[i]);
572
573 return err;
574 }
575
576 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
577 {
578 return 0;
579 }
580
581 static int tegra_powergate_power_up(struct tegra_powergate *pg,
582 bool disable_clocks)
583 {
584 int err;
585
586 err = reset_control_assert(pg->reset);
587 if (err)
588 return err;
589
590 usleep_range(10, 20);
591
592 err = tegra_powergate_set(pg->pmc, pg->id, true);
593 if (err < 0)
594 return err;
595
596 usleep_range(10, 20);
597
598 err = tegra_powergate_enable_clocks(pg);
599 if (err)
600 goto disable_clks;
601
602 usleep_range(10, 20);
603
604 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
605 if (err)
606 goto disable_clks;
607
608 usleep_range(10, 20);
609
610 err = reset_control_deassert(pg->reset);
611 if (err)
612 goto powergate_off;
613
614 usleep_range(10, 20);
615
616 if (pg->pmc->soc->needs_mbist_war)
617 err = tegra210_clk_handle_mbist_war(pg->id);
618 if (err)
619 goto disable_clks;
620
621 if (disable_clocks)
622 tegra_powergate_disable_clocks(pg);
623
624 return 0;
625
626 disable_clks:
627 tegra_powergate_disable_clocks(pg);
628 usleep_range(10, 20);
629
630 powergate_off:
631 tegra_powergate_set(pg->pmc, pg->id, false);
632
633 return err;
634 }
635
636 static int tegra_powergate_power_down(struct tegra_powergate *pg)
637 {
638 int err;
639
640 err = tegra_powergate_enable_clocks(pg);
641 if (err)
642 return err;
643
644 usleep_range(10, 20);
645
646 err = reset_control_assert(pg->reset);
647 if (err)
648 goto disable_clks;
649
650 usleep_range(10, 20);
651
652 tegra_powergate_disable_clocks(pg);
653
654 usleep_range(10, 20);
655
656 err = tegra_powergate_set(pg->pmc, pg->id, false);
657 if (err)
658 goto assert_resets;
659
660 return 0;
661
662 assert_resets:
663 tegra_powergate_enable_clocks(pg);
664 usleep_range(10, 20);
665 reset_control_deassert(pg->reset);
666 usleep_range(10, 20);
667
668 disable_clks:
669 tegra_powergate_disable_clocks(pg);
670
671 return err;
672 }
673
674 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
675 {
676 struct tegra_powergate *pg = to_powergate(domain);
677 struct device *dev = pg->pmc->dev;
678 int err;
679
680 err = tegra_powergate_power_up(pg, true);
681 if (err) {
682 dev_err(dev, "failed to turn on PM domain %s: %d\n",
683 pg->genpd.name, err);
684 goto out;
685 }
686
687 reset_control_release(pg->reset);
688
689 out:
690 return err;
691 }
692
693 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
694 {
695 struct tegra_powergate *pg = to_powergate(domain);
696 struct device *dev = pg->pmc->dev;
697 int err;
698
699 err = reset_control_acquire(pg->reset);
700 if (err < 0) {
701 pr_err("failed to acquire resets: %d\n", err);
702 return err;
703 }
704
705 err = tegra_powergate_power_down(pg);
706 if (err) {
707 dev_err(dev, "failed to turn off PM domain %s: %d\n",
708 pg->genpd.name, err);
709 reset_control_release(pg->reset);
710 }
711
712 return err;
713 }
714
715 /**
716 * tegra_powergate_power_on() - power on partition
717 * @id: partition ID
718 */
719 int tegra_powergate_power_on(unsigned int id)
720 {
721 if (!tegra_powergate_is_available(pmc, id))
722 return -EINVAL;
723
724 return tegra_powergate_set(pmc, id, true);
725 }
726 EXPORT_SYMBOL(tegra_powergate_power_on);
727
728 /**
729 * tegra_powergate_power_off() - power off partition
730 * @id: partition ID
731 */
732 int tegra_powergate_power_off(unsigned int id)
733 {
734 if (!tegra_powergate_is_available(pmc, id))
735 return -EINVAL;
736
737 return tegra_powergate_set(pmc, id, false);
738 }
739 EXPORT_SYMBOL(tegra_powergate_power_off);
740
741 /**
742 * tegra_powergate_is_powered() - check if partition is powered
743 * @pmc: power management controller
744 * @id: partition ID
745 */
746 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
747 {
748 if (!tegra_powergate_is_valid(pmc, id))
749 return -EINVAL;
750
751 return tegra_powergate_state(id);
752 }
753
754 /**
755 * tegra_powergate_remove_clamping() - remove power clamps for partition
756 * @id: partition ID
757 */
758 int tegra_powergate_remove_clamping(unsigned int id)
759 {
760 if (!tegra_powergate_is_available(pmc, id))
761 return -EINVAL;
762
763 return __tegra_powergate_remove_clamping(pmc, id);
764 }
765 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
766
767 /**
768 * tegra_powergate_sequence_power_up() - power up partition
769 * @id: partition ID
770 * @clk: clock for partition
771 * @rst: reset for partition
772 *
773 * Must be called with clk disabled, and returns with clk enabled.
774 */
775 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
776 struct reset_control *rst)
777 {
778 struct tegra_powergate *pg;
779 int err;
780
781 if (!tegra_powergate_is_available(pmc, id))
782 return -EINVAL;
783
784 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
785 if (!pg)
786 return -ENOMEM;
787
788 pg->id = id;
789 pg->clks = &clk;
790 pg->num_clks = 1;
791 pg->reset = rst;
792 pg->pmc = pmc;
793
794 err = tegra_powergate_power_up(pg, false);
795 if (err)
796 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
797 err);
798
799 kfree(pg);
800
801 return err;
802 }
803 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
804
805 /**
806 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
807 * @pmc: power management controller
808 * @cpuid: CPU partition ID
809 *
810 * Returns the partition ID corresponding to the CPU partition ID or a
811 * negative error code on failure.
812 */
813 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
814 unsigned int cpuid)
815 {
816 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
817 return pmc->soc->cpu_powergates[cpuid];
818
819 return -EINVAL;
820 }
821
822 /**
823 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
824 * @cpuid: CPU partition ID
825 */
826 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
827 {
828 int id;
829
830 id = tegra_get_cpu_powergate_id(pmc, cpuid);
831 if (id < 0)
832 return false;
833
834 return tegra_powergate_is_powered(pmc, id);
835 }
836
837 /**
838 * tegra_pmc_cpu_power_on() - power on CPU partition
839 * @cpuid: CPU partition ID
840 */
841 int tegra_pmc_cpu_power_on(unsigned int cpuid)
842 {
843 int id;
844
845 id = tegra_get_cpu_powergate_id(pmc, cpuid);
846 if (id < 0)
847 return id;
848
849 return tegra_powergate_set(pmc, id, true);
850 }
851
852 /**
853 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
854 * @cpuid: CPU partition ID
855 */
856 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
857 {
858 int id;
859
860 id = tegra_get_cpu_powergate_id(pmc, cpuid);
861 if (id < 0)
862 return id;
863
864 return tegra_powergate_remove_clamping(id);
865 }
866
867 static int tegra_pmc_restart_notify(struct notifier_block *this,
868 unsigned long action, void *data)
869 {
870 const char *cmd = data;
871 u32 value;
872
873 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
874 value &= ~PMC_SCRATCH0_MODE_MASK;
875
876 if (cmd) {
877 if (strcmp(cmd, "recovery") == 0)
878 value |= PMC_SCRATCH0_MODE_RECOVERY;
879
880 if (strcmp(cmd, "bootloader") == 0)
881 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
882
883 if (strcmp(cmd, "forced-recovery") == 0)
884 value |= PMC_SCRATCH0_MODE_RCM;
885 }
886
887 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
888
889 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
890 value = tegra_pmc_readl(pmc, PMC_CNTRL);
891 value |= PMC_CNTRL_MAIN_RST;
892 tegra_pmc_writel(pmc, value, PMC_CNTRL);
893
894 return NOTIFY_DONE;
895 }
896
897 static struct notifier_block tegra_pmc_restart_handler = {
898 .notifier_call = tegra_pmc_restart_notify,
899 .priority = 128,
900 };
901
902 static int powergate_show(struct seq_file *s, void *data)
903 {
904 unsigned int i;
905 int status;
906
907 seq_printf(s, " powergate powered\n");
908 seq_printf(s, "------------------\n");
909
910 for (i = 0; i < pmc->soc->num_powergates; i++) {
911 status = tegra_powergate_is_powered(pmc, i);
912 if (status < 0)
913 continue;
914
915 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
916 status ? "yes" : "no");
917 }
918
919 return 0;
920 }
921
922 DEFINE_SHOW_ATTRIBUTE(powergate);
923
924 static int tegra_powergate_debugfs_init(void)
925 {
926 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
927 &powergate_fops);
928 if (!pmc->debugfs)
929 return -ENOMEM;
930
931 return 0;
932 }
933
934 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
935 struct device_node *np)
936 {
937 struct clk *clk;
938 unsigned int i, count;
939 int err;
940
941 count = of_clk_get_parent_count(np);
942 if (count == 0)
943 return -ENODEV;
944
945 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
946 if (!pg->clks)
947 return -ENOMEM;
948
949 for (i = 0; i < count; i++) {
950 pg->clks[i] = of_clk_get(np, i);
951 if (IS_ERR(pg->clks[i])) {
952 err = PTR_ERR(pg->clks[i]);
953 goto err;
954 }
955 }
956
957 pg->num_clks = count;
958
959 return 0;
960
961 err:
962 while (i--)
963 clk_put(pg->clks[i]);
964
965 kfree(pg->clks);
966
967 return err;
968 }
969
970 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
971 struct device_node *np, bool off)
972 {
973 struct device *dev = pg->pmc->dev;
974 int err;
975
976 pg->reset = of_reset_control_array_get_exclusive_released(np);
977 if (IS_ERR(pg->reset)) {
978 err = PTR_ERR(pg->reset);
979 dev_err(dev, "failed to get device resets: %d\n", err);
980 return err;
981 }
982
983 err = reset_control_acquire(pg->reset);
984 if (err < 0) {
985 pr_err("failed to acquire resets: %d\n", err);
986 goto out;
987 }
988
989 if (off) {
990 err = reset_control_assert(pg->reset);
991 } else {
992 err = reset_control_deassert(pg->reset);
993 if (err < 0)
994 goto out;
995
996 reset_control_release(pg->reset);
997 }
998
999 out:
1000 if (err) {
1001 reset_control_release(pg->reset);
1002 reset_control_put(pg->reset);
1003 }
1004
1005 return err;
1006 }
1007
1008 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1009 {
1010 struct device *dev = pmc->dev;
1011 struct tegra_powergate *pg;
1012 int id, err = 0;
1013 bool off;
1014
1015 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1016 if (!pg)
1017 return -ENOMEM;
1018
1019 id = tegra_powergate_lookup(pmc, np->name);
1020 if (id < 0) {
1021 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1022 err = -ENODEV;
1023 goto free_mem;
1024 }
1025
1026 /*
1027 * Clear the bit for this powergate so it cannot be managed
1028 * directly via the legacy APIs for controlling powergates.
1029 */
1030 clear_bit(id, pmc->powergates_available);
1031
1032 pg->id = id;
1033 pg->genpd.name = np->name;
1034 pg->genpd.power_off = tegra_genpd_power_off;
1035 pg->genpd.power_on = tegra_genpd_power_on;
1036 pg->pmc = pmc;
1037
1038 off = !tegra_powergate_is_powered(pmc, pg->id);
1039
1040 err = tegra_powergate_of_get_clks(pg, np);
1041 if (err < 0) {
1042 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1043 goto set_available;
1044 }
1045
1046 err = tegra_powergate_of_get_resets(pg, np, off);
1047 if (err < 0) {
1048 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1049 goto remove_clks;
1050 }
1051
1052 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1053 if (off)
1054 WARN_ON(tegra_powergate_power_up(pg, true));
1055
1056 goto remove_resets;
1057 }
1058
1059 err = pm_genpd_init(&pg->genpd, NULL, off);
1060 if (err < 0) {
1061 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1062 err);
1063 goto remove_resets;
1064 }
1065
1066 err = of_genpd_add_provider_simple(np, &pg->genpd);
1067 if (err < 0) {
1068 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1069 np, err);
1070 goto remove_genpd;
1071 }
1072
1073 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1074
1075 return 0;
1076
1077 remove_genpd:
1078 pm_genpd_remove(&pg->genpd);
1079
1080 remove_resets:
1081 reset_control_put(pg->reset);
1082
1083 remove_clks:
1084 while (pg->num_clks--)
1085 clk_put(pg->clks[pg->num_clks]);
1086
1087 kfree(pg->clks);
1088
1089 set_available:
1090 set_bit(id, pmc->powergates_available);
1091
1092 free_mem:
1093 kfree(pg);
1094
1095 return err;
1096 }
1097
1098 static int tegra_powergate_init(struct tegra_pmc *pmc,
1099 struct device_node *parent)
1100 {
1101 struct device_node *np, *child;
1102 int err = 0;
1103
1104 np = of_get_child_by_name(parent, "powergates");
1105 if (!np)
1106 return 0;
1107
1108 for_each_child_of_node(np, child) {
1109 err = tegra_powergate_add(pmc, child);
1110 if (err < 0) {
1111 of_node_put(child);
1112 break;
1113 }
1114 }
1115
1116 of_node_put(np);
1117
1118 return err;
1119 }
1120
1121 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1122 {
1123 struct tegra_powergate *pg = to_powergate(genpd);
1124
1125 reset_control_put(pg->reset);
1126
1127 while (pg->num_clks--)
1128 clk_put(pg->clks[pg->num_clks]);
1129
1130 kfree(pg->clks);
1131
1132 set_bit(pg->id, pmc->powergates_available);
1133
1134 kfree(pg);
1135 }
1136
1137 static void tegra_powergate_remove_all(struct device_node *parent)
1138 {
1139 struct generic_pm_domain *genpd;
1140 struct device_node *np, *child;
1141
1142 np = of_get_child_by_name(parent, "powergates");
1143 if (!np)
1144 return;
1145
1146 for_each_child_of_node(np, child) {
1147 of_genpd_del_provider(child);
1148
1149 genpd = of_genpd_remove_last(child);
1150 if (IS_ERR(genpd))
1151 continue;
1152
1153 tegra_powergate_remove(genpd);
1154 }
1155
1156 of_node_put(np);
1157 }
1158
1159 static const struct tegra_io_pad_soc *
1160 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1161 {
1162 unsigned int i;
1163
1164 for (i = 0; i < pmc->soc->num_io_pads; i++)
1165 if (pmc->soc->io_pads[i].id == id)
1166 return &pmc->soc->io_pads[i];
1167
1168 return NULL;
1169 }
1170
1171 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1172 enum tegra_io_pad id,
1173 unsigned long *request,
1174 unsigned long *status,
1175 u32 *mask)
1176 {
1177 const struct tegra_io_pad_soc *pad;
1178
1179 pad = tegra_io_pad_find(pmc, id);
1180 if (!pad) {
1181 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1182 return -ENOENT;
1183 }
1184
1185 if (pad->dpd == UINT_MAX)
1186 return -ENOTSUPP;
1187
1188 *mask = BIT(pad->dpd % 32);
1189
1190 if (pad->dpd < 32) {
1191 *status = pmc->soc->regs->dpd_status;
1192 *request = pmc->soc->regs->dpd_req;
1193 } else {
1194 *status = pmc->soc->regs->dpd2_status;
1195 *request = pmc->soc->regs->dpd2_req;
1196 }
1197
1198 return 0;
1199 }
1200
1201 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1202 unsigned long *request, unsigned long *status,
1203 u32 *mask)
1204 {
1205 unsigned long rate, value;
1206 int err;
1207
1208 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1209 if (err)
1210 return err;
1211
1212 if (pmc->clk) {
1213 rate = pmc->rate;
1214 if (!rate) {
1215 dev_err(pmc->dev, "failed to get clock rate\n");
1216 return -ENODEV;
1217 }
1218
1219 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1220
1221 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1222 value = DIV_ROUND_UP(1000000000, rate);
1223 value = DIV_ROUND_UP(200, value);
1224 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1225 }
1226
1227 return 0;
1228 }
1229
1230 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1231 u32 mask, u32 val, unsigned long timeout)
1232 {
1233 u32 value;
1234
1235 timeout = jiffies + msecs_to_jiffies(timeout);
1236
1237 while (time_after(timeout, jiffies)) {
1238 value = tegra_pmc_readl(pmc, offset);
1239 if ((value & mask) == val)
1240 return 0;
1241
1242 usleep_range(250, 1000);
1243 }
1244
1245 return -ETIMEDOUT;
1246 }
1247
1248 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1249 {
1250 if (pmc->clk)
1251 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1252 }
1253
1254 /**
1255 * tegra_io_pad_power_enable() - enable power to I/O pad
1256 * @id: Tegra I/O pad ID for which to enable power
1257 *
1258 * Returns: 0 on success or a negative error code on failure.
1259 */
1260 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1261 {
1262 unsigned long request, status;
1263 u32 mask;
1264 int err;
1265
1266 mutex_lock(&pmc->powergates_lock);
1267
1268 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1269 if (err < 0) {
1270 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1271 goto unlock;
1272 }
1273
1274 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1275
1276 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1277 if (err < 0) {
1278 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1279 goto unlock;
1280 }
1281
1282 tegra_io_pad_unprepare(pmc);
1283
1284 unlock:
1285 mutex_unlock(&pmc->powergates_lock);
1286 return err;
1287 }
1288 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1289
1290 /**
1291 * tegra_io_pad_power_disable() - disable power to I/O pad
1292 * @id: Tegra I/O pad ID for which to disable power
1293 *
1294 * Returns: 0 on success or a negative error code on failure.
1295 */
1296 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1297 {
1298 unsigned long request, status;
1299 u32 mask;
1300 int err;
1301
1302 mutex_lock(&pmc->powergates_lock);
1303
1304 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1305 if (err < 0) {
1306 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1307 goto unlock;
1308 }
1309
1310 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1311
1312 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1313 if (err < 0) {
1314 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1315 goto unlock;
1316 }
1317
1318 tegra_io_pad_unprepare(pmc);
1319
1320 unlock:
1321 mutex_unlock(&pmc->powergates_lock);
1322 return err;
1323 }
1324 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1325
1326 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1327 {
1328 unsigned long request, status;
1329 u32 mask, value;
1330 int err;
1331
1332 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1333 &mask);
1334 if (err)
1335 return err;
1336
1337 value = tegra_pmc_readl(pmc, status);
1338
1339 return !(value & mask);
1340 }
1341
1342 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1343 int voltage)
1344 {
1345 const struct tegra_io_pad_soc *pad;
1346 u32 value;
1347
1348 pad = tegra_io_pad_find(pmc, id);
1349 if (!pad)
1350 return -ENOENT;
1351
1352 if (pad->voltage == UINT_MAX)
1353 return -ENOTSUPP;
1354
1355 mutex_lock(&pmc->powergates_lock);
1356
1357 if (pmc->soc->has_impl_33v_pwr) {
1358 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1359
1360 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1361 value &= ~BIT(pad->voltage);
1362 else
1363 value |= BIT(pad->voltage);
1364
1365 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1366 } else {
1367 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1368 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1369 value |= BIT(pad->voltage);
1370 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1371
1372 /* update I/O voltage */
1373 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1374
1375 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1376 value &= ~BIT(pad->voltage);
1377 else
1378 value |= BIT(pad->voltage);
1379
1380 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1381 }
1382
1383 mutex_unlock(&pmc->powergates_lock);
1384
1385 usleep_range(100, 250);
1386
1387 return 0;
1388 }
1389
1390 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1391 {
1392 const struct tegra_io_pad_soc *pad;
1393 u32 value;
1394
1395 pad = tegra_io_pad_find(pmc, id);
1396 if (!pad)
1397 return -ENOENT;
1398
1399 if (pad->voltage == UINT_MAX)
1400 return -ENOTSUPP;
1401
1402 if (pmc->soc->has_impl_33v_pwr)
1403 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1404 else
1405 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1406
1407 if ((value & BIT(pad->voltage)) == 0)
1408 return TEGRA_IO_PAD_VOLTAGE_1V8;
1409
1410 return TEGRA_IO_PAD_VOLTAGE_3V3;
1411 }
1412
1413 /**
1414 * tegra_io_rail_power_on() - enable power to I/O rail
1415 * @id: Tegra I/O pad ID for which to enable power
1416 *
1417 * See also: tegra_io_pad_power_enable()
1418 */
1419 int tegra_io_rail_power_on(unsigned int id)
1420 {
1421 return tegra_io_pad_power_enable(id);
1422 }
1423 EXPORT_SYMBOL(tegra_io_rail_power_on);
1424
1425 /**
1426 * tegra_io_rail_power_off() - disable power to I/O rail
1427 * @id: Tegra I/O pad ID for which to disable power
1428 *
1429 * See also: tegra_io_pad_power_disable()
1430 */
1431 int tegra_io_rail_power_off(unsigned int id)
1432 {
1433 return tegra_io_pad_power_disable(id);
1434 }
1435 EXPORT_SYMBOL(tegra_io_rail_power_off);
1436
1437 #ifdef CONFIG_PM_SLEEP
1438 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1439 {
1440 return pmc->suspend_mode;
1441 }
1442
1443 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1444 {
1445 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1446 return;
1447
1448 pmc->suspend_mode = mode;
1449 }
1450
1451 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1452 {
1453 unsigned long long rate = 0;
1454 u64 ticks;
1455 u32 value;
1456
1457 switch (mode) {
1458 case TEGRA_SUSPEND_LP1:
1459 rate = 32768;
1460 break;
1461
1462 case TEGRA_SUSPEND_LP2:
1463 rate = pmc->rate;
1464 break;
1465
1466 default:
1467 break;
1468 }
1469
1470 if (WARN_ON_ONCE(rate == 0))
1471 rate = 100000000;
1472
1473 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1474 do_div(ticks, USEC_PER_SEC);
1475 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1476
1477 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1478 do_div(ticks, USEC_PER_SEC);
1479 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1480
1481 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1482 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1483 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1484 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1485 }
1486 #endif
1487
1488 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1489 {
1490 u32 value, values[2];
1491
1492 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1493 } else {
1494 switch (value) {
1495 case 0:
1496 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1497 break;
1498
1499 case 1:
1500 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1501 break;
1502
1503 case 2:
1504 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1505 break;
1506
1507 default:
1508 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1509 break;
1510 }
1511 }
1512
1513 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1514
1515 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1516 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1517
1518 pmc->cpu_good_time = value;
1519
1520 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1521 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1522
1523 pmc->cpu_off_time = value;
1524
1525 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1526 values, ARRAY_SIZE(values)))
1527 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1528
1529 pmc->core_osc_time = values[0];
1530 pmc->core_pmu_time = values[1];
1531
1532 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1533 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1534
1535 pmc->core_off_time = value;
1536
1537 pmc->corereq_high = of_property_read_bool(np,
1538 "nvidia,core-power-req-active-high");
1539
1540 pmc->sysclkreq_high = of_property_read_bool(np,
1541 "nvidia,sys-clock-req-active-high");
1542
1543 pmc->combined_req = of_property_read_bool(np,
1544 "nvidia,combined-power-req");
1545
1546 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1547 "nvidia,cpu-pwr-good-en");
1548
1549 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1550 ARRAY_SIZE(values)))
1551 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1552 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1553
1554 pmc->lp0_vec_phys = values[0];
1555 pmc->lp0_vec_size = values[1];
1556
1557 return 0;
1558 }
1559
1560 static void tegra_pmc_init(struct tegra_pmc *pmc)
1561 {
1562 if (pmc->soc->init)
1563 pmc->soc->init(pmc);
1564 }
1565
1566 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1567 {
1568 static const char disabled[] = "emergency thermal reset disabled";
1569 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1570 struct device *dev = pmc->dev;
1571 struct device_node *np;
1572 u32 value, checksum;
1573
1574 if (!pmc->soc->has_tsense_reset)
1575 return;
1576
1577 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1578 if (!np) {
1579 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1580 return;
1581 }
1582
1583 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1584 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1585 goto out;
1586 }
1587
1588 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1589 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1590 goto out;
1591 }
1592
1593 if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {
1594 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1595 goto out;
1596 }
1597
1598 if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {
1599 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1600 goto out;
1601 }
1602
1603 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1604 pinmux = 0;
1605
1606 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1607 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1608 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1609
1610 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1611 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1612 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1613
1614 value = PMC_SCRATCH55_RESET_TEGRA;
1615 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1616 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1617 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1618
1619 /*
1620 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1621 * contain the checksum and are currently zero, so they are not added.
1622 */
1623 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1624 + ((value >> 24) & 0xff);
1625 checksum &= 0xff;
1626 checksum = 0x100 - checksum;
1627
1628 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1629
1630 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1631
1632 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1633 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1634 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1635
1636 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1637
1638 out:
1639 of_node_put(np);
1640 }
1641
1642 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1643 {
1644 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1645
1646 return pmc->soc->num_io_pads;
1647 }
1648
1649 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1650 unsigned int group)
1651 {
1652 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1653
1654 return pmc->soc->io_pads[group].name;
1655 }
1656
1657 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1658 unsigned int group,
1659 const unsigned int **pins,
1660 unsigned int *num_pins)
1661 {
1662 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1663
1664 *pins = &pmc->soc->io_pads[group].id;
1665 *num_pins = 1;
1666
1667 return 0;
1668 }
1669
1670 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1671 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1672 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1673 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1674 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1675 .dt_free_map = pinconf_generic_dt_free_map,
1676 };
1677
1678 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1679 unsigned int pin, unsigned long *config)
1680 {
1681 enum pin_config_param param = pinconf_to_config_param(*config);
1682 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1683 const struct tegra_io_pad_soc *pad;
1684 int ret;
1685 u32 arg;
1686
1687 pad = tegra_io_pad_find(pmc, pin);
1688 if (!pad)
1689 return -EINVAL;
1690
1691 switch (param) {
1692 case PIN_CONFIG_POWER_SOURCE:
1693 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1694 if (ret < 0)
1695 return ret;
1696
1697 arg = ret;
1698 break;
1699
1700 case PIN_CONFIG_LOW_POWER_MODE:
1701 ret = tegra_io_pad_is_powered(pmc, pad->id);
1702 if (ret < 0)
1703 return ret;
1704
1705 arg = !ret;
1706 break;
1707
1708 default:
1709 return -EINVAL;
1710 }
1711
1712 *config = pinconf_to_config_packed(param, arg);
1713
1714 return 0;
1715 }
1716
1717 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1718 unsigned int pin, unsigned long *configs,
1719 unsigned int num_configs)
1720 {
1721 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1722 const struct tegra_io_pad_soc *pad;
1723 enum pin_config_param param;
1724 unsigned int i;
1725 int err;
1726 u32 arg;
1727
1728 pad = tegra_io_pad_find(pmc, pin);
1729 if (!pad)
1730 return -EINVAL;
1731
1732 for (i = 0; i < num_configs; ++i) {
1733 param = pinconf_to_config_param(configs[i]);
1734 arg = pinconf_to_config_argument(configs[i]);
1735
1736 switch (param) {
1737 case PIN_CONFIG_LOW_POWER_MODE:
1738 if (arg)
1739 err = tegra_io_pad_power_disable(pad->id);
1740 else
1741 err = tegra_io_pad_power_enable(pad->id);
1742 if (err)
1743 return err;
1744 break;
1745 case PIN_CONFIG_POWER_SOURCE:
1746 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1747 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1748 return -EINVAL;
1749 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1750 if (err)
1751 return err;
1752 break;
1753 default:
1754 return -EINVAL;
1755 }
1756 }
1757
1758 return 0;
1759 }
1760
1761 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1762 .pin_config_get = tegra_io_pad_pinconf_get,
1763 .pin_config_set = tegra_io_pad_pinconf_set,
1764 .is_generic = true,
1765 };
1766
1767 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1768 .pctlops = &tegra_io_pad_pinctrl_ops,
1769 .confops = &tegra_io_pad_pinconf_ops,
1770 };
1771
1772 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1773 {
1774 int err;
1775
1776 if (!pmc->soc->num_pin_descs)
1777 return 0;
1778
1779 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1780 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1781 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1782
1783 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1784 pmc);
1785 if (IS_ERR(pmc->pctl_dev)) {
1786 err = PTR_ERR(pmc->pctl_dev);
1787 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1788 err);
1789 return err;
1790 }
1791
1792 return 0;
1793 }
1794
1795 static ssize_t reset_reason_show(struct device *dev,
1796 struct device_attribute *attr, char *buf)
1797 {
1798 u32 value;
1799
1800 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1801 value &= pmc->soc->regs->rst_source_mask;
1802 value >>= pmc->soc->regs->rst_source_shift;
1803
1804 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1805 return sprintf(buf, "%s\n", "UNKNOWN");
1806
1807 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1808 }
1809
1810 static DEVICE_ATTR_RO(reset_reason);
1811
1812 static ssize_t reset_level_show(struct device *dev,
1813 struct device_attribute *attr, char *buf)
1814 {
1815 u32 value;
1816
1817 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1818 value &= pmc->soc->regs->rst_level_mask;
1819 value >>= pmc->soc->regs->rst_level_shift;
1820
1821 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1822 return sprintf(buf, "%s\n", "UNKNOWN");
1823
1824 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1825 }
1826
1827 static DEVICE_ATTR_RO(reset_level);
1828
1829 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
1830 {
1831 struct device *dev = pmc->dev;
1832 int err = 0;
1833
1834 if (pmc->soc->reset_sources) {
1835 err = device_create_file(dev, &dev_attr_reset_reason);
1836 if (err < 0)
1837 dev_warn(dev,
1838 "failed to create attr \"reset_reason\": %d\n",
1839 err);
1840 }
1841
1842 if (pmc->soc->reset_levels) {
1843 err = device_create_file(dev, &dev_attr_reset_level);
1844 if (err < 0)
1845 dev_warn(dev,
1846 "failed to create attr \"reset_level\": %d\n",
1847 err);
1848 }
1849 }
1850
1851 static int tegra_pmc_irq_translate(struct irq_domain *domain,
1852 struct irq_fwspec *fwspec,
1853 unsigned long *hwirq,
1854 unsigned int *type)
1855 {
1856 if (WARN_ON(fwspec->param_count < 2))
1857 return -EINVAL;
1858
1859 *hwirq = fwspec->param[0];
1860 *type = fwspec->param[1];
1861
1862 return 0;
1863 }
1864
1865 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
1866 unsigned int num_irqs, void *data)
1867 {
1868 struct tegra_pmc *pmc = domain->host_data;
1869 const struct tegra_pmc_soc *soc = pmc->soc;
1870 struct irq_fwspec *fwspec = data;
1871 unsigned int i;
1872 int err = 0;
1873
1874 if (WARN_ON(num_irqs > 1))
1875 return -EINVAL;
1876
1877 for (i = 0; i < soc->num_wake_events; i++) {
1878 const struct tegra_wake_event *event = &soc->wake_events[i];
1879
1880 if (fwspec->param_count == 2) {
1881 struct irq_fwspec spec;
1882
1883 if (event->id != fwspec->param[0])
1884 continue;
1885
1886 err = irq_domain_set_hwirq_and_chip(domain, virq,
1887 event->id,
1888 &pmc->irq, pmc);
1889 if (err < 0)
1890 break;
1891
1892 spec.fwnode = &pmc->dev->of_node->fwnode;
1893 spec.param_count = 3;
1894 spec.param[0] = GIC_SPI;
1895 spec.param[1] = event->irq;
1896 spec.param[2] = fwspec->param[1];
1897
1898 err = irq_domain_alloc_irqs_parent(domain, virq,
1899 num_irqs, &spec);
1900
1901 break;
1902 }
1903
1904 if (fwspec->param_count == 3) {
1905 if (event->gpio.instance != fwspec->param[0] ||
1906 event->gpio.pin != fwspec->param[1])
1907 continue;
1908
1909 err = irq_domain_set_hwirq_and_chip(domain, virq,
1910 event->id,
1911 &pmc->irq, pmc);
1912
1913 /*
1914 * GPIOs don't have an equivalent interrupt in the
1915 * parent controller (GIC). However some code, such
1916 * as the one in irq_get_irqchip_state(), require a
1917 * valid IRQ chip to be set. Make sure that's the
1918 * case by passing NULL here, which will install a
1919 * dummy IRQ chip for the interrupt in the parent
1920 * domain.
1921 */
1922 if (domain->parent)
1923 irq_domain_set_hwirq_and_chip(domain->parent,
1924 virq, 0, NULL,
1925 NULL);
1926
1927 break;
1928 }
1929 }
1930
1931 /*
1932 * For interrupts that don't have associated wake events, assign a
1933 * dummy hardware IRQ number. This is used in the ->irq_set_type()
1934 * and ->irq_set_wake() callbacks to return early for these IRQs.
1935 */
1936 if (i == soc->num_wake_events) {
1937 err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX,
1938 &pmc->irq, pmc);
1939
1940 /*
1941 * Interrupts without a wake event don't have a corresponding
1942 * interrupt in the parent controller (GIC). Pass NULL for the
1943 * chip here, which causes a dummy IRQ chip to be installed
1944 * for the interrupt in the parent domain, to make this
1945 * explicit.
1946 */
1947 if (domain->parent)
1948 irq_domain_set_hwirq_and_chip(domain->parent, virq, 0,
1949 NULL, NULL);
1950 }
1951
1952 return err;
1953 }
1954
1955 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
1956 .translate = tegra_pmc_irq_translate,
1957 .alloc = tegra_pmc_irq_alloc,
1958 };
1959
1960 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
1961 {
1962 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1963 unsigned int offset, bit;
1964 u32 value;
1965
1966 if (data->hwirq == ULONG_MAX)
1967 return 0;
1968
1969 offset = data->hwirq / 32;
1970 bit = data->hwirq % 32;
1971
1972 /* clear wake status */
1973 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
1974 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
1975
1976 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
1977 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
1978
1979 /* enable PMC wake */
1980 if (data->hwirq >= 32)
1981 offset = PMC_WAKE2_MASK;
1982 else
1983 offset = PMC_WAKE_MASK;
1984
1985 value = tegra_pmc_readl(pmc, offset);
1986
1987 if (on)
1988 value |= BIT(bit);
1989 else
1990 value &= ~BIT(bit);
1991
1992 tegra_pmc_writel(pmc, value, offset);
1993
1994 return 0;
1995 }
1996
1997 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
1998 {
1999 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2000 unsigned int offset, bit;
2001 u32 value;
2002
2003 if (data->hwirq == ULONG_MAX)
2004 return 0;
2005
2006 offset = data->hwirq / 32;
2007 bit = data->hwirq % 32;
2008
2009 if (data->hwirq >= 32)
2010 offset = PMC_WAKE2_LEVEL;
2011 else
2012 offset = PMC_WAKE_LEVEL;
2013
2014 value = tegra_pmc_readl(pmc, offset);
2015
2016 switch (type) {
2017 case IRQ_TYPE_EDGE_RISING:
2018 case IRQ_TYPE_LEVEL_HIGH:
2019 value |= BIT(bit);
2020 break;
2021
2022 case IRQ_TYPE_EDGE_FALLING:
2023 case IRQ_TYPE_LEVEL_LOW:
2024 value &= ~BIT(bit);
2025 break;
2026
2027 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2028 value ^= BIT(bit);
2029 break;
2030
2031 default:
2032 return -EINVAL;
2033 }
2034
2035 tegra_pmc_writel(pmc, value, offset);
2036
2037 return 0;
2038 }
2039
2040 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2041 {
2042 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2043 unsigned int offset, bit;
2044 u32 value;
2045
2046 /* nothing to do if there's no associated wake event */
2047 if (WARN_ON(data->hwirq == ULONG_MAX))
2048 return 0;
2049
2050 offset = data->hwirq / 32;
2051 bit = data->hwirq % 32;
2052
2053 /* clear wake status */
2054 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2055
2056 /* route wake to tier 2 */
2057 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2058
2059 if (!on)
2060 value &= ~(1 << bit);
2061 else
2062 value |= 1 << bit;
2063
2064 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2065
2066 /* enable wakeup event */
2067 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2068
2069 return 0;
2070 }
2071
2072 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2073 {
2074 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2075 u32 value;
2076
2077 /* nothing to do if there's no associated wake event */
2078 if (data->hwirq == ULONG_MAX)
2079 return 0;
2080
2081 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2082
2083 switch (type) {
2084 case IRQ_TYPE_EDGE_RISING:
2085 case IRQ_TYPE_LEVEL_HIGH:
2086 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2087 break;
2088
2089 case IRQ_TYPE_EDGE_FALLING:
2090 case IRQ_TYPE_LEVEL_LOW:
2091 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2092 break;
2093
2094 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2095 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2096 break;
2097
2098 default:
2099 return -EINVAL;
2100 }
2101
2102 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2103
2104 return 0;
2105 }
2106
2107 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2108 {
2109 struct irq_domain *parent = NULL;
2110 struct device_node *np;
2111
2112 np = of_irq_find_parent(pmc->dev->of_node);
2113 if (np) {
2114 parent = irq_find_host(np);
2115 of_node_put(np);
2116 }
2117
2118 if (!parent)
2119 return 0;
2120
2121 pmc->irq.name = dev_name(pmc->dev);
2122 pmc->irq.irq_mask = irq_chip_mask_parent;
2123 pmc->irq.irq_unmask = irq_chip_unmask_parent;
2124 pmc->irq.irq_eoi = irq_chip_eoi_parent;
2125 pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent;
2126 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2127 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2128
2129 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2130 &tegra_pmc_irq_domain_ops, pmc);
2131 if (!pmc->domain) {
2132 dev_err(pmc->dev, "failed to allocate domain\n");
2133 return -ENOMEM;
2134 }
2135
2136 return 0;
2137 }
2138
2139 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2140 unsigned long action, void *ptr)
2141 {
2142 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2143 struct clk_notifier_data *data = ptr;
2144
2145 switch (action) {
2146 case PRE_RATE_CHANGE:
2147 mutex_lock(&pmc->powergates_lock);
2148 break;
2149
2150 case POST_RATE_CHANGE:
2151 pmc->rate = data->new_rate;
2152 /* fall through */
2153
2154 case ABORT_RATE_CHANGE:
2155 mutex_unlock(&pmc->powergates_lock);
2156 break;
2157
2158 default:
2159 WARN_ON_ONCE(1);
2160 return notifier_from_errno(-EINVAL);
2161 }
2162
2163 return NOTIFY_OK;
2164 }
2165
2166 static int tegra_pmc_probe(struct platform_device *pdev)
2167 {
2168 void __iomem *base;
2169 struct resource *res;
2170 int err;
2171
2172 /*
2173 * Early initialisation should have configured an initial
2174 * register mapping and setup the soc data pointer. If these
2175 * are not valid then something went badly wrong!
2176 */
2177 if (WARN_ON(!pmc->base || !pmc->soc))
2178 return -ENODEV;
2179
2180 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2181 if (err < 0)
2182 return err;
2183
2184 /* take over the memory region from the early initialization */
2185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2186 base = devm_ioremap_resource(&pdev->dev, res);
2187 if (IS_ERR(base))
2188 return PTR_ERR(base);
2189
2190 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2191 if (res) {
2192 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2193 if (IS_ERR(pmc->wake))
2194 return PTR_ERR(pmc->wake);
2195 } else {
2196 pmc->wake = base;
2197 }
2198
2199 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2200 if (res) {
2201 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2202 if (IS_ERR(pmc->aotag))
2203 return PTR_ERR(pmc->aotag);
2204 } else {
2205 pmc->aotag = base;
2206 }
2207
2208 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2209 if (res) {
2210 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2211 if (IS_ERR(pmc->scratch))
2212 return PTR_ERR(pmc->scratch);
2213 } else {
2214 pmc->scratch = base;
2215 }
2216
2217 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2218 if (IS_ERR(pmc->clk)) {
2219 err = PTR_ERR(pmc->clk);
2220
2221 if (err != -ENOENT) {
2222 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2223 return err;
2224 }
2225
2226 pmc->clk = NULL;
2227 }
2228
2229 /*
2230 * PCLK clock rate can't be retrieved using CLK API because it
2231 * causes lockup if CPU enters LP2 idle state from some other
2232 * CLK notifier, hence we're caching the rate's value locally.
2233 */
2234 if (pmc->clk) {
2235 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2236 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2237 if (err) {
2238 dev_err(&pdev->dev,
2239 "failed to register clk notifier\n");
2240 return err;
2241 }
2242
2243 pmc->rate = clk_get_rate(pmc->clk);
2244 }
2245
2246 pmc->dev = &pdev->dev;
2247
2248 tegra_pmc_init(pmc);
2249
2250 tegra_pmc_init_tsense_reset(pmc);
2251
2252 tegra_pmc_reset_sysfs_init(pmc);
2253
2254 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2255 err = tegra_powergate_debugfs_init();
2256 if (err < 0)
2257 goto cleanup_sysfs;
2258 }
2259
2260 err = register_restart_handler(&tegra_pmc_restart_handler);
2261 if (err) {
2262 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2263 err);
2264 goto cleanup_debugfs;
2265 }
2266
2267 err = tegra_pmc_pinctrl_init(pmc);
2268 if (err)
2269 goto cleanup_restart_handler;
2270
2271 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2272 if (err < 0)
2273 goto cleanup_powergates;
2274
2275 err = tegra_pmc_irq_init(pmc);
2276 if (err < 0)
2277 goto cleanup_powergates;
2278
2279 mutex_lock(&pmc->powergates_lock);
2280 iounmap(pmc->base);
2281 pmc->base = base;
2282 mutex_unlock(&pmc->powergates_lock);
2283
2284 platform_set_drvdata(pdev, pmc);
2285
2286 return 0;
2287
2288 cleanup_powergates:
2289 tegra_powergate_remove_all(pdev->dev.of_node);
2290 cleanup_restart_handler:
2291 unregister_restart_handler(&tegra_pmc_restart_handler);
2292 cleanup_debugfs:
2293 debugfs_remove(pmc->debugfs);
2294 cleanup_sysfs:
2295 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2296 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2297 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2298
2299 return err;
2300 }
2301
2302 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2303 static int tegra_pmc_suspend(struct device *dev)
2304 {
2305 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2306
2307 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2308
2309 return 0;
2310 }
2311
2312 static int tegra_pmc_resume(struct device *dev)
2313 {
2314 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2315
2316 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2317
2318 return 0;
2319 }
2320
2321 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2322
2323 #endif
2324
2325 static const char * const tegra20_powergates[] = {
2326 [TEGRA_POWERGATE_CPU] = "cpu",
2327 [TEGRA_POWERGATE_3D] = "3d",
2328 [TEGRA_POWERGATE_VENC] = "venc",
2329 [TEGRA_POWERGATE_VDEC] = "vdec",
2330 [TEGRA_POWERGATE_PCIE] = "pcie",
2331 [TEGRA_POWERGATE_L2] = "l2",
2332 [TEGRA_POWERGATE_MPE] = "mpe",
2333 };
2334
2335 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2336 .scratch0 = 0x50,
2337 .dpd_req = 0x1b8,
2338 .dpd_status = 0x1bc,
2339 .dpd2_req = 0x1c0,
2340 .dpd2_status = 0x1c4,
2341 .rst_status = 0x1b4,
2342 .rst_source_shift = 0x0,
2343 .rst_source_mask = 0x7,
2344 .rst_level_shift = 0x0,
2345 .rst_level_mask = 0x0,
2346 };
2347
2348 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2349 {
2350 u32 value, osc, pmu, off;
2351
2352 /* Always enable CPU power request */
2353 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2354 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2355 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2356
2357 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2358
2359 if (pmc->sysclkreq_high)
2360 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2361 else
2362 value |= PMC_CNTRL_SYSCLK_POLARITY;
2363
2364 if (pmc->corereq_high)
2365 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
2366 else
2367 value |= PMC_CNTRL_PWRREQ_POLARITY;
2368
2369 /* configure the output polarity while the request is tristated */
2370 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2371
2372 /* now enable the request */
2373 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2374 value |= PMC_CNTRL_SYSCLK_OE;
2375 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2376
2377 /* program core timings which are applicable only for suspend state */
2378 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
2379 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
2380 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
2381 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
2382 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
2383 PMC_COREPWRGOOD_TIMER);
2384 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
2385 }
2386 }
2387
2388 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2389 struct device_node *np,
2390 bool invert)
2391 {
2392 u32 value;
2393
2394 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2395
2396 if (invert)
2397 value |= PMC_CNTRL_INTR_POLARITY;
2398 else
2399 value &= ~PMC_CNTRL_INTR_POLARITY;
2400
2401 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2402 }
2403
2404 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2405 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2406 .powergates = tegra20_powergates,
2407 .num_cpu_powergates = 0,
2408 .cpu_powergates = NULL,
2409 .has_tsense_reset = false,
2410 .has_gpu_clamps = false,
2411 .needs_mbist_war = false,
2412 .has_impl_33v_pwr = false,
2413 .maybe_tz_only = false,
2414 .num_io_pads = 0,
2415 .io_pads = NULL,
2416 .num_pin_descs = 0,
2417 .pin_descs = NULL,
2418 .regs = &tegra20_pmc_regs,
2419 .init = tegra20_pmc_init,
2420 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2421 .reset_sources = NULL,
2422 .num_reset_sources = 0,
2423 .reset_levels = NULL,
2424 .num_reset_levels = 0,
2425 };
2426
2427 static const char * const tegra30_powergates[] = {
2428 [TEGRA_POWERGATE_CPU] = "cpu0",
2429 [TEGRA_POWERGATE_3D] = "3d0",
2430 [TEGRA_POWERGATE_VENC] = "venc",
2431 [TEGRA_POWERGATE_VDEC] = "vdec",
2432 [TEGRA_POWERGATE_PCIE] = "pcie",
2433 [TEGRA_POWERGATE_L2] = "l2",
2434 [TEGRA_POWERGATE_MPE] = "mpe",
2435 [TEGRA_POWERGATE_HEG] = "heg",
2436 [TEGRA_POWERGATE_SATA] = "sata",
2437 [TEGRA_POWERGATE_CPU1] = "cpu1",
2438 [TEGRA_POWERGATE_CPU2] = "cpu2",
2439 [TEGRA_POWERGATE_CPU3] = "cpu3",
2440 [TEGRA_POWERGATE_CELP] = "celp",
2441 [TEGRA_POWERGATE_3D1] = "3d1",
2442 };
2443
2444 static const u8 tegra30_cpu_powergates[] = {
2445 TEGRA_POWERGATE_CPU,
2446 TEGRA_POWERGATE_CPU1,
2447 TEGRA_POWERGATE_CPU2,
2448 TEGRA_POWERGATE_CPU3,
2449 };
2450
2451 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2452 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2453 .powergates = tegra30_powergates,
2454 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2455 .cpu_powergates = tegra30_cpu_powergates,
2456 .has_tsense_reset = true,
2457 .has_gpu_clamps = false,
2458 .needs_mbist_war = false,
2459 .has_impl_33v_pwr = false,
2460 .maybe_tz_only = false,
2461 .num_io_pads = 0,
2462 .io_pads = NULL,
2463 .num_pin_descs = 0,
2464 .pin_descs = NULL,
2465 .regs = &tegra20_pmc_regs,
2466 .init = tegra20_pmc_init,
2467 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2468 .reset_sources = tegra30_reset_sources,
2469 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2470 .reset_levels = NULL,
2471 .num_reset_levels = 0,
2472 };
2473
2474 static const char * const tegra114_powergates[] = {
2475 [TEGRA_POWERGATE_CPU] = "crail",
2476 [TEGRA_POWERGATE_3D] = "3d",
2477 [TEGRA_POWERGATE_VENC] = "venc",
2478 [TEGRA_POWERGATE_VDEC] = "vdec",
2479 [TEGRA_POWERGATE_MPE] = "mpe",
2480 [TEGRA_POWERGATE_HEG] = "heg",
2481 [TEGRA_POWERGATE_CPU1] = "cpu1",
2482 [TEGRA_POWERGATE_CPU2] = "cpu2",
2483 [TEGRA_POWERGATE_CPU3] = "cpu3",
2484 [TEGRA_POWERGATE_CELP] = "celp",
2485 [TEGRA_POWERGATE_CPU0] = "cpu0",
2486 [TEGRA_POWERGATE_C0NC] = "c0nc",
2487 [TEGRA_POWERGATE_C1NC] = "c1nc",
2488 [TEGRA_POWERGATE_DIS] = "dis",
2489 [TEGRA_POWERGATE_DISB] = "disb",
2490 [TEGRA_POWERGATE_XUSBA] = "xusba",
2491 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2492 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2493 };
2494
2495 static const u8 tegra114_cpu_powergates[] = {
2496 TEGRA_POWERGATE_CPU0,
2497 TEGRA_POWERGATE_CPU1,
2498 TEGRA_POWERGATE_CPU2,
2499 TEGRA_POWERGATE_CPU3,
2500 };
2501
2502 static const struct tegra_pmc_soc tegra114_pmc_soc = {
2503 .num_powergates = ARRAY_SIZE(tegra114_powergates),
2504 .powergates = tegra114_powergates,
2505 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
2506 .cpu_powergates = tegra114_cpu_powergates,
2507 .has_tsense_reset = true,
2508 .has_gpu_clamps = false,
2509 .needs_mbist_war = false,
2510 .has_impl_33v_pwr = false,
2511 .maybe_tz_only = false,
2512 .num_io_pads = 0,
2513 .io_pads = NULL,
2514 .num_pin_descs = 0,
2515 .pin_descs = NULL,
2516 .regs = &tegra20_pmc_regs,
2517 .init = tegra20_pmc_init,
2518 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2519 .reset_sources = tegra30_reset_sources,
2520 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2521 .reset_levels = NULL,
2522 .num_reset_levels = 0,
2523 };
2524
2525 static const char * const tegra124_powergates[] = {
2526 [TEGRA_POWERGATE_CPU] = "crail",
2527 [TEGRA_POWERGATE_3D] = "3d",
2528 [TEGRA_POWERGATE_VENC] = "venc",
2529 [TEGRA_POWERGATE_PCIE] = "pcie",
2530 [TEGRA_POWERGATE_VDEC] = "vdec",
2531 [TEGRA_POWERGATE_MPE] = "mpe",
2532 [TEGRA_POWERGATE_HEG] = "heg",
2533 [TEGRA_POWERGATE_SATA] = "sata",
2534 [TEGRA_POWERGATE_CPU1] = "cpu1",
2535 [TEGRA_POWERGATE_CPU2] = "cpu2",
2536 [TEGRA_POWERGATE_CPU3] = "cpu3",
2537 [TEGRA_POWERGATE_CELP] = "celp",
2538 [TEGRA_POWERGATE_CPU0] = "cpu0",
2539 [TEGRA_POWERGATE_C0NC] = "c0nc",
2540 [TEGRA_POWERGATE_C1NC] = "c1nc",
2541 [TEGRA_POWERGATE_SOR] = "sor",
2542 [TEGRA_POWERGATE_DIS] = "dis",
2543 [TEGRA_POWERGATE_DISB] = "disb",
2544 [TEGRA_POWERGATE_XUSBA] = "xusba",
2545 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2546 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2547 [TEGRA_POWERGATE_VIC] = "vic",
2548 [TEGRA_POWERGATE_IRAM] = "iram",
2549 };
2550
2551 static const u8 tegra124_cpu_powergates[] = {
2552 TEGRA_POWERGATE_CPU0,
2553 TEGRA_POWERGATE_CPU1,
2554 TEGRA_POWERGATE_CPU2,
2555 TEGRA_POWERGATE_CPU3,
2556 };
2557
2558 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
2559 ((struct tegra_io_pad_soc) { \
2560 .id = (_id), \
2561 .dpd = (_dpd), \
2562 .voltage = (_voltage), \
2563 .name = (_name), \
2564 })
2565
2566 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
2567 ((struct pinctrl_pin_desc) { \
2568 .number = (_id), \
2569 .name = (_name) \
2570 })
2571
2572 #define TEGRA124_IO_PAD_TABLE(_pad) \
2573 /* .id .dpd .voltage .name */ \
2574 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2575 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
2576 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
2577 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
2578 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2579 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
2580 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
2581 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2582 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2583 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2584 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2585 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2586 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2587 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
2588 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2589 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2590 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
2591 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2592 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2593 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2594 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2595 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
2596 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
2597 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
2598 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
2599 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2600 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2601 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2602 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2603 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
2604
2605 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
2606 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
2607 };
2608
2609 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
2610 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2611 };
2612
2613 static const struct tegra_pmc_soc tegra124_pmc_soc = {
2614 .num_powergates = ARRAY_SIZE(tegra124_powergates),
2615 .powergates = tegra124_powergates,
2616 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
2617 .cpu_powergates = tegra124_cpu_powergates,
2618 .has_tsense_reset = true,
2619 .has_gpu_clamps = true,
2620 .needs_mbist_war = false,
2621 .has_impl_33v_pwr = false,
2622 .maybe_tz_only = false,
2623 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
2624 .io_pads = tegra124_io_pads,
2625 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
2626 .pin_descs = tegra124_pin_descs,
2627 .regs = &tegra20_pmc_regs,
2628 .init = tegra20_pmc_init,
2629 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2630 .reset_sources = tegra30_reset_sources,
2631 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2632 .reset_levels = NULL,
2633 .num_reset_levels = 0,
2634 };
2635
2636 static const char * const tegra210_powergates[] = {
2637 [TEGRA_POWERGATE_CPU] = "crail",
2638 [TEGRA_POWERGATE_3D] = "3d",
2639 [TEGRA_POWERGATE_VENC] = "venc",
2640 [TEGRA_POWERGATE_PCIE] = "pcie",
2641 [TEGRA_POWERGATE_MPE] = "mpe",
2642 [TEGRA_POWERGATE_SATA] = "sata",
2643 [TEGRA_POWERGATE_CPU1] = "cpu1",
2644 [TEGRA_POWERGATE_CPU2] = "cpu2",
2645 [TEGRA_POWERGATE_CPU3] = "cpu3",
2646 [TEGRA_POWERGATE_CPU0] = "cpu0",
2647 [TEGRA_POWERGATE_C0NC] = "c0nc",
2648 [TEGRA_POWERGATE_SOR] = "sor",
2649 [TEGRA_POWERGATE_DIS] = "dis",
2650 [TEGRA_POWERGATE_DISB] = "disb",
2651 [TEGRA_POWERGATE_XUSBA] = "xusba",
2652 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2653 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2654 [TEGRA_POWERGATE_VIC] = "vic",
2655 [TEGRA_POWERGATE_IRAM] = "iram",
2656 [TEGRA_POWERGATE_NVDEC] = "nvdec",
2657 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
2658 [TEGRA_POWERGATE_AUD] = "aud",
2659 [TEGRA_POWERGATE_DFD] = "dfd",
2660 [TEGRA_POWERGATE_VE2] = "ve2",
2661 };
2662
2663 static const u8 tegra210_cpu_powergates[] = {
2664 TEGRA_POWERGATE_CPU0,
2665 TEGRA_POWERGATE_CPU1,
2666 TEGRA_POWERGATE_CPU2,
2667 TEGRA_POWERGATE_CPU3,
2668 };
2669
2670 #define TEGRA210_IO_PAD_TABLE(_pad) \
2671 /* .id .dpd .voltage .name */ \
2672 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
2673 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
2674 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
2675 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2676 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2677 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
2678 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
2679 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
2680 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
2681 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
2682 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
2683 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
2684 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
2685 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2686 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2687 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2688 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2689 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
2690 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
2691 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
2692 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2693 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2694 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2695 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2696 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2697 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2698 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2699 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
2700 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
2701 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
2702 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
2703 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
2704 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
2705 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2706 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2707 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2708 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
2709 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
2710
2711 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
2712 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
2713 };
2714
2715 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
2716 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2717 };
2718
2719 static const struct tegra_wake_event tegra210_wake_events[] = {
2720 TEGRA_WAKE_IRQ("rtc", 16, 2),
2721 };
2722
2723 static const struct tegra_pmc_soc tegra210_pmc_soc = {
2724 .num_powergates = ARRAY_SIZE(tegra210_powergates),
2725 .powergates = tegra210_powergates,
2726 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
2727 .cpu_powergates = tegra210_cpu_powergates,
2728 .has_tsense_reset = true,
2729 .has_gpu_clamps = true,
2730 .needs_mbist_war = true,
2731 .has_impl_33v_pwr = false,
2732 .maybe_tz_only = true,
2733 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
2734 .io_pads = tegra210_io_pads,
2735 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
2736 .pin_descs = tegra210_pin_descs,
2737 .regs = &tegra20_pmc_regs,
2738 .init = tegra20_pmc_init,
2739 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2740 .irq_set_wake = tegra210_pmc_irq_set_wake,
2741 .irq_set_type = tegra210_pmc_irq_set_type,
2742 .reset_sources = tegra210_reset_sources,
2743 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
2744 .reset_levels = NULL,
2745 .num_reset_levels = 0,
2746 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
2747 .wake_events = tegra210_wake_events,
2748 };
2749
2750 #define TEGRA186_IO_PAD_TABLE(_pad) \
2751 /* .id .dpd .voltage .name */ \
2752 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2753 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2754 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2755 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2756 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
2757 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
2758 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2759 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
2760 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2761 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2762 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2763 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
2764 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2765 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2766 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2767 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
2768 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
2769 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
2770 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2771 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
2772 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
2773 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
2774 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
2775 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
2776 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
2777 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
2778 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
2779 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
2780 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
2781 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
2782 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
2783 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
2784 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
2785 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
2786 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
2787 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
2788 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
2789 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
2790
2791 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
2792 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
2793 };
2794
2795 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
2796 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2797 };
2798
2799 static const struct tegra_pmc_regs tegra186_pmc_regs = {
2800 .scratch0 = 0x2000,
2801 .dpd_req = 0x74,
2802 .dpd_status = 0x78,
2803 .dpd2_req = 0x7c,
2804 .dpd2_status = 0x80,
2805 .rst_status = 0x70,
2806 .rst_source_shift = 0x2,
2807 .rst_source_mask = 0x3c,
2808 .rst_level_shift = 0x0,
2809 .rst_level_mask = 0x3,
2810 };
2811
2812 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2813 struct device_node *np,
2814 bool invert)
2815 {
2816 struct resource regs;
2817 void __iomem *wake;
2818 u32 value;
2819 int index;
2820
2821 index = of_property_match_string(np, "reg-names", "wake");
2822 if (index < 0) {
2823 dev_err(pmc->dev, "failed to find PMC wake registers\n");
2824 return;
2825 }
2826
2827 of_address_to_resource(np, index, &regs);
2828
2829 wake = ioremap(regs.start, resource_size(&regs));
2830 if (!wake) {
2831 dev_err(pmc->dev, "failed to map PMC wake registers\n");
2832 return;
2833 }
2834
2835 value = readl(wake + WAKE_AOWAKE_CTRL);
2836
2837 if (invert)
2838 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
2839 else
2840 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
2841
2842 writel(value, wake + WAKE_AOWAKE_CTRL);
2843
2844 iounmap(wake);
2845 }
2846
2847 static const struct tegra_wake_event tegra186_wake_events[] = {
2848 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
2849 TEGRA_WAKE_IRQ("rtc", 73, 10),
2850 };
2851
2852 static const struct tegra_pmc_soc tegra186_pmc_soc = {
2853 .num_powergates = 0,
2854 .powergates = NULL,
2855 .num_cpu_powergates = 0,
2856 .cpu_powergates = NULL,
2857 .has_tsense_reset = false,
2858 .has_gpu_clamps = false,
2859 .needs_mbist_war = false,
2860 .has_impl_33v_pwr = true,
2861 .maybe_tz_only = false,
2862 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
2863 .io_pads = tegra186_io_pads,
2864 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
2865 .pin_descs = tegra186_pin_descs,
2866 .regs = &tegra186_pmc_regs,
2867 .init = NULL,
2868 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2869 .irq_set_wake = tegra186_pmc_irq_set_wake,
2870 .irq_set_type = tegra186_pmc_irq_set_type,
2871 .reset_sources = tegra186_reset_sources,
2872 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
2873 .reset_levels = tegra186_reset_levels,
2874 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
2875 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
2876 .wake_events = tegra186_wake_events,
2877 };
2878
2879 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
2880 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
2881 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
2882 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
2883 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
2884 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
2885 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
2886 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
2887 { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX },
2888 { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX },
2889 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX },
2890 { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX },
2891 { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX },
2892 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
2893 { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX },
2894 { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX },
2895 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
2896 { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX },
2897 { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX },
2898 { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX },
2899 { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX },
2900 { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX },
2901 { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX },
2902 { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX },
2903 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
2904 { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX },
2905 { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX },
2906 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
2907 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
2908 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
2909 { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX },
2910 { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX },
2911 { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX },
2912 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
2913 { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX },
2914 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
2915 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
2916 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
2917 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
2918 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
2919 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
2920 { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX },
2921 { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX },
2922 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
2923 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX },
2924 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX },
2925 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
2926 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
2927 };
2928
2929 static const struct tegra_pmc_regs tegra194_pmc_regs = {
2930 .scratch0 = 0x2000,
2931 .dpd_req = 0x74,
2932 .dpd_status = 0x78,
2933 .dpd2_req = 0x7c,
2934 .dpd2_status = 0x80,
2935 .rst_status = 0x70,
2936 .rst_source_shift = 0x2,
2937 .rst_source_mask = 0x7c,
2938 .rst_level_shift = 0x0,
2939 .rst_level_mask = 0x3,
2940 };
2941
2942 static const char * const tegra194_reset_sources[] = {
2943 "SYS_RESET_N",
2944 "AOWDT",
2945 "BCCPLEXWDT",
2946 "BPMPWDT",
2947 "SCEWDT",
2948 "SPEWDT",
2949 "APEWDT",
2950 "LCCPLEXWDT",
2951 "SENSOR",
2952 "AOTAG",
2953 "VFSENSOR",
2954 "MAINSWRST",
2955 "SC7",
2956 "HSM",
2957 "CSITE",
2958 "RCEWDT",
2959 "PVA0WDT",
2960 "PVA1WDT",
2961 "L1A_ASYNC",
2962 "BPMPBOOT",
2963 "FUSECRC",
2964 };
2965
2966 static const struct tegra_wake_event tegra194_wake_events[] = {
2967 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
2968 TEGRA_WAKE_IRQ("rtc", 73, 10),
2969 };
2970
2971 static const struct tegra_pmc_soc tegra194_pmc_soc = {
2972 .num_powergates = 0,
2973 .powergates = NULL,
2974 .num_cpu_powergates = 0,
2975 .cpu_powergates = NULL,
2976 .has_tsense_reset = false,
2977 .has_gpu_clamps = false,
2978 .needs_mbist_war = false,
2979 .has_impl_33v_pwr = false,
2980 .maybe_tz_only = false,
2981 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
2982 .io_pads = tegra194_io_pads,
2983 .regs = &tegra194_pmc_regs,
2984 .init = NULL,
2985 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2986 .irq_set_wake = tegra186_pmc_irq_set_wake,
2987 .irq_set_type = tegra186_pmc_irq_set_type,
2988 .reset_sources = tegra194_reset_sources,
2989 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
2990 .reset_levels = tegra186_reset_levels,
2991 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
2992 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
2993 .wake_events = tegra194_wake_events,
2994 };
2995
2996 static const struct of_device_id tegra_pmc_match[] = {
2997 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
2998 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
2999 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3000 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3001 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3002 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3003 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3004 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3005 { }
3006 };
3007
3008 static struct platform_driver tegra_pmc_driver = {
3009 .driver = {
3010 .name = "tegra-pmc",
3011 .suppress_bind_attrs = true,
3012 .of_match_table = tegra_pmc_match,
3013 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3014 .pm = &tegra_pmc_pm_ops,
3015 #endif
3016 },
3017 .probe = tegra_pmc_probe,
3018 };
3019 builtin_platform_driver(tegra_pmc_driver);
3020
3021 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3022 {
3023 u32 value, saved;
3024
3025 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3026 value = saved ^ 0xffffffff;
3027
3028 if (value == 0xffffffff)
3029 value = 0xdeadbeef;
3030
3031 /* write pattern and read it back */
3032 writel(value, pmc->base + pmc->soc->regs->scratch0);
3033 value = readl(pmc->base + pmc->soc->regs->scratch0);
3034
3035 /* if we read all-zeroes, access is restricted to TZ only */
3036 if (value == 0) {
3037 pr_info("access to PMC is restricted to TZ\n");
3038 return true;
3039 }
3040
3041 /* restore original value */
3042 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3043
3044 return false;
3045 }
3046
3047 /*
3048 * Early initialization to allow access to registers in the very early boot
3049 * process.
3050 */
3051 static int __init tegra_pmc_early_init(void)
3052 {
3053 const struct of_device_id *match;
3054 struct device_node *np;
3055 struct resource regs;
3056 unsigned int i;
3057 bool invert;
3058
3059 mutex_init(&pmc->powergates_lock);
3060
3061 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3062 if (!np) {
3063 /*
3064 * Fall back to legacy initialization for 32-bit ARM only. All
3065 * 64-bit ARM device tree files for Tegra are required to have
3066 * a PMC node.
3067 *
3068 * This is for backwards-compatibility with old device trees
3069 * that didn't contain a PMC node. Note that in this case the
3070 * SoC data can't be matched and therefore powergating is
3071 * disabled.
3072 */
3073 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3074 pr_warn("DT node not found, powergating disabled\n");
3075
3076 regs.start = 0x7000e400;
3077 regs.end = 0x7000e7ff;
3078 regs.flags = IORESOURCE_MEM;
3079
3080 pr_warn("Using memory region %pR\n", &regs);
3081 } else {
3082 /*
3083 * At this point we're not running on Tegra, so play
3084 * nice with multi-platform kernels.
3085 */
3086 return 0;
3087 }
3088 } else {
3089 /*
3090 * Extract information from the device tree if we've found a
3091 * matching node.
3092 */
3093 if (of_address_to_resource(np, 0, &regs) < 0) {
3094 pr_err("failed to get PMC registers\n");
3095 of_node_put(np);
3096 return -ENXIO;
3097 }
3098 }
3099
3100 pmc->base = ioremap(regs.start, resource_size(&regs));
3101 if (!pmc->base) {
3102 pr_err("failed to map PMC registers\n");
3103 of_node_put(np);
3104 return -ENXIO;
3105 }
3106
3107 if (np) {
3108 pmc->soc = match->data;
3109
3110 if (pmc->soc->maybe_tz_only)
3111 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3112
3113 /* Create a bitmap of the available and valid partitions */
3114 for (i = 0; i < pmc->soc->num_powergates; i++)
3115 if (pmc->soc->powergates[i])
3116 set_bit(i, pmc->powergates_available);
3117
3118 /*
3119 * Invert the interrupt polarity if a PMC device tree node
3120 * exists and contains the nvidia,invert-interrupt property.
3121 */
3122 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3123
3124 pmc->soc->setup_irq_polarity(pmc, np, invert);
3125
3126 of_node_put(np);
3127 }
3128
3129 return 0;
3130 }
3131 early_initcall(tegra_pmc_early_init);
Linux with added FPC-III support