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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / soundwire / qcom.c
blob1c6c6a2e0def551f3865f8de55d092688b4266f3
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
3
4 #include <linux/clk.h>
5 #include <linux/completion.h>
6 #include <linux/interrupt.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_irq.h>
12 #include <linux/of_device.h>
13 #include <linux/regmap.h>
14 #include <linux/slab.h>
15 #include <linux/slimbus.h>
16 #include <linux/soundwire/sdw.h>
17 #include <linux/soundwire/sdw_registers.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc.h>
20 #include "bus.h"
21
22 #define SWRM_COMP_HW_VERSION 0x00
23 #define SWRM_COMP_CFG_ADDR 0x04
24 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
25 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
26 #define SWRM_COMP_PARAMS 0x100
27 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
28 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
29 #define SWRM_INTERRUPT_STATUS 0x200
30 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
31 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
32 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
33 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
34 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
35 #define SWRM_INTERRUPT_MASK_ADDR 0x204
36 #define SWRM_INTERRUPT_CLEAR 0x208
37 #define SWRM_CMD_FIFO_WR_CMD 0x300
38 #define SWRM_CMD_FIFO_RD_CMD 0x304
39 #define SWRM_CMD_FIFO_CMD 0x308
40 #define SWRM_CMD_FIFO_STATUS 0x30C
41 #define SWRM_CMD_FIFO_CFG_ADDR 0x314
42 #define SWRM_RD_WR_CMD_RETRIES 0x7
43 #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
44 #define SWRM_ENUMERATOR_CFG_ADDR 0x500
45 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
46 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT 3
47 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
48 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
49 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT 0
50 #define SWRM_MCP_CFG_ADDR 0x1048
51 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
52 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT 0x11
53 #define SWRM_DEF_CMD_NO_PINGS 0x1f
54 #define SWRM_MCP_STATUS 0x104C
55 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
56 #define SWRM_MCP_SLV_STATUS 0x1090
57 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
58 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
59 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
60 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
61 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
62 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
63 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
64 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
65 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
66
67 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \
68 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
69
70 #define SWRM_MAX_ROW_VAL 0 /* Rows = 48 */
71 #define SWRM_DEFAULT_ROWS 48
72 #define SWRM_MIN_COL_VAL 0 /* Cols = 2 */
73 #define SWRM_DEFAULT_COL 16
74 #define SWRM_MAX_COL_VAL 7
75 #define SWRM_SPECIAL_CMD_ID 0xF
76 #define MAX_FREQ_NUM 1
77 #define TIMEOUT_MS (2 * HZ)
78 #define QCOM_SWRM_MAX_RD_LEN 0xf
79 #define QCOM_SDW_MAX_PORTS 14
80 #define DEFAULT_CLK_FREQ 9600000
81 #define SWRM_MAX_DAIS 0xF
82
83 struct qcom_swrm_port_config {
84 u8 si;
85 u8 off1;
86 u8 off2;
87 };
88
89 struct qcom_swrm_ctrl {
90 struct sdw_bus bus;
91 struct device *dev;
92 struct regmap *regmap;
93 struct completion *comp;
94 struct work_struct slave_work;
95 /* read/write lock */
96 spinlock_t comp_lock;
97 /* Port alloc/free lock */
98 struct mutex port_lock;
99 struct clk *hclk;
100 u8 wr_cmd_id;
101 u8 rd_cmd_id;
102 int irq;
103 unsigned int version;
104 int num_din_ports;
105 int num_dout_ports;
106 unsigned long dout_port_mask;
107 unsigned long din_port_mask;
108 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
109 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
110 enum sdw_slave_status status[SDW_MAX_DEVICES];
111 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
112 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
113 };
114
115 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
116
117 static int qcom_swrm_abh_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
118 u32 *val)
119 {
120 struct regmap *wcd_regmap = ctrl->regmap;
121 int ret;
122
123 /* pg register + offset */
124 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
125 (u8 *)&reg, 4);
126 if (ret < 0)
127 return SDW_CMD_FAIL;
128
129 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
130 val, 4);
131 if (ret < 0)
132 return SDW_CMD_FAIL;
133
134 return SDW_CMD_OK;
135 }
136
137 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
138 int reg, int val)
139 {
140 struct regmap *wcd_regmap = ctrl->regmap;
141 int ret;
142 /* pg register + offset */
143 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
144 (u8 *)&val, 4);
145 if (ret)
146 return SDW_CMD_FAIL;
147
148 /* write address register */
149 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
150 (u8 *)&reg, 4);
151 if (ret)
152 return SDW_CMD_FAIL;
153
154 return SDW_CMD_OK;
155 }
156
157 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
158 u8 dev_addr, u16 reg_addr)
159 {
160 DECLARE_COMPLETION_ONSTACK(comp);
161 unsigned long flags;
162 u32 val;
163 int ret;
164
165 spin_lock_irqsave(&ctrl->comp_lock, flags);
166 ctrl->comp = &comp;
167 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
168 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr,
169 SWRM_SPECIAL_CMD_ID, reg_addr);
170 ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
171 if (ret)
172 goto err;
173
174 ret = wait_for_completion_timeout(ctrl->comp,
175 msecs_to_jiffies(TIMEOUT_MS));
176
177 if (!ret)
178 ret = SDW_CMD_IGNORED;
179 else
180 ret = SDW_CMD_OK;
181 err:
182 spin_lock_irqsave(&ctrl->comp_lock, flags);
183 ctrl->comp = NULL;
184 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
185
186 return ret;
187 }
188
189 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
190 u8 dev_addr, u16 reg_addr,
191 u32 len, u8 *rval)
192 {
193 int i, ret;
194 u32 val;
195 DECLARE_COMPLETION_ONSTACK(comp);
196 unsigned long flags;
197
198 spin_lock_irqsave(&ctrl->comp_lock, flags);
199 ctrl->comp = &comp;
200 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
201
202 val = SWRM_REG_VAL_PACK(len, dev_addr, SWRM_SPECIAL_CMD_ID, reg_addr);
203 ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
204 if (ret)
205 goto err;
206
207 ret = wait_for_completion_timeout(ctrl->comp,
208 msecs_to_jiffies(TIMEOUT_MS));
209
210 if (!ret) {
211 ret = SDW_CMD_IGNORED;
212 goto err;
213 } else {
214 ret = SDW_CMD_OK;
215 }
216
217 for (i = 0; i < len; i++) {
218 ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &val);
219 rval[i] = val & 0xFF;
220 }
221
222 err:
223 spin_lock_irqsave(&ctrl->comp_lock, flags);
224 ctrl->comp = NULL;
225 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
226
227 return ret;
228 }
229
230 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
231 {
232 u32 val;
233 int i;
234
235 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
236
237 for (i = 0; i < SDW_MAX_DEVICES; i++) {
238 u32 s;
239
240 s = (val >> (i * 2));
241 s &= SWRM_MCP_SLV_STATUS_MASK;
242 ctrl->status[i] = s;
243 }
244 }
245
246 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
247 {
248 struct qcom_swrm_ctrl *ctrl = dev_id;
249 u32 sts, value;
250 unsigned long flags;
251
252 ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &sts);
253
254 if (sts & SWRM_INTERRUPT_STATUS_CMD_ERROR) {
255 ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
256 dev_err_ratelimited(ctrl->dev,
257 "CMD error, fifo status 0x%x\n",
258 value);
259 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
260 }
261
262 if ((sts & SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED) ||
263 sts & SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS)
264 schedule_work(&ctrl->slave_work);
265
266 /**
267 * clear the interrupt before complete() is called, as complete can
268 * schedule new read/writes which require interrupts, clearing the
269 * interrupt would avoid missing interrupts in such cases.
270 */
271 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);
272
273 if (sts & SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED) {
274 spin_lock_irqsave(&ctrl->comp_lock, flags);
275 if (ctrl->comp)
276 complete(ctrl->comp);
277 spin_unlock_irqrestore(&ctrl->comp_lock, flags);
278 }
279
280 return IRQ_HANDLED;
281 }
282 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
283 {
284 u32 val;
285
286 /* Clear Rows and Cols */
287 val = (SWRM_MAX_ROW_VAL << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT |
288 SWRM_MIN_COL_VAL << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT);
289
290 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
291
292 /* Disable Auto enumeration */
293 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0);
294
295 /* Mask soundwire interrupts */
296 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
297 SWRM_INTERRUPT_STATUS_RMSK);
298
299 /* Configure No pings */
300 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
301 val &= ~SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK;
302 val |= (SWRM_DEF_CMD_NO_PINGS <<
303 SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT);
304 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
305
306 /* Configure number of retries of a read/write cmd */
307 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, SWRM_RD_WR_CMD_RETRIES);
308
309 /* Set IRQ to PULSE */
310 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
311 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
312 SWRM_COMP_CFG_ENABLE_MSK);
313 return 0;
314 }
315
316 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
317 struct sdw_msg *msg)
318 {
319 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
320 int ret, i, len;
321
322 if (msg->flags == SDW_MSG_FLAG_READ) {
323 for (i = 0; i < msg->len;) {
324 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
325 len = msg->len - i;
326 else
327 len = QCOM_SWRM_MAX_RD_LEN;
328
329 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
330 msg->addr + i, len,
331 &msg->buf[i]);
332 if (ret)
333 return ret;
334
335 i = i + len;
336 }
337 } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
338 for (i = 0; i < msg->len; i++) {
339 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
340 msg->dev_num,
341 msg->addr + i);
342 if (ret)
343 return SDW_CMD_IGNORED;
344 }
345 }
346
347 return SDW_CMD_OK;
348 }
349
350 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
351 {
352 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
353 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
354 u32 val;
355
356 ctrl->reg_read(ctrl, reg, &val);
357
358 val &= ~SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK;
359 val &= ~SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK;
360
361 val |= (SWRM_MAX_ROW_VAL << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT |
362 SWRM_MAX_COL_VAL << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT);
363
364 return ctrl->reg_write(ctrl, reg, val);
365 }
366
367 static int qcom_swrm_port_params(struct sdw_bus *bus,
368 struct sdw_port_params *p_params,
369 unsigned int bank)
370 {
371 /* TBD */
372 return 0;
373 }
374
375 static int qcom_swrm_transport_params(struct sdw_bus *bus,
376 struct sdw_transport_params *params,
377 enum sdw_reg_bank bank)
378 {
379 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
380 u32 value;
381
382 value = params->offset1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
383 value |= params->offset2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
384 value |= params->sample_interval - 1;
385
386 return ctrl->reg_write(ctrl,
387 SWRM_DP_PORT_CTRL_BANK((params->port_num), bank),
388 value);
389 }
390
391 static int qcom_swrm_port_enable(struct sdw_bus *bus,
392 struct sdw_enable_ch *enable_ch,
393 unsigned int bank)
394 {
395 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
396 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
397 u32 val;
398
399 ctrl->reg_read(ctrl, reg, &val);
400
401 if (enable_ch->enable)
402 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
403 else
404 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
405
406 return ctrl->reg_write(ctrl, reg, val);
407 }
408
409 static struct sdw_master_port_ops qcom_swrm_port_ops = {
410 .dpn_set_port_params = qcom_swrm_port_params,
411 .dpn_set_port_transport_params = qcom_swrm_transport_params,
412 .dpn_port_enable_ch = qcom_swrm_port_enable,
413 };
414
415 static struct sdw_master_ops qcom_swrm_ops = {
416 .xfer_msg = qcom_swrm_xfer_msg,
417 .pre_bank_switch = qcom_swrm_pre_bank_switch,
418 };
419
420 static int qcom_swrm_compute_params(struct sdw_bus *bus)
421 {
422 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
423 struct sdw_master_runtime *m_rt;
424 struct sdw_slave_runtime *s_rt;
425 struct sdw_port_runtime *p_rt;
426 struct qcom_swrm_port_config *pcfg;
427 int i = 0;
428
429 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
430 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
431 pcfg = &ctrl->pconfig[p_rt->num - 1];
432 p_rt->transport_params.port_num = p_rt->num;
433 p_rt->transport_params.sample_interval = pcfg->si + 1;
434 p_rt->transport_params.offset1 = pcfg->off1;
435 p_rt->transport_params.offset2 = pcfg->off2;
436 }
437
438 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
439 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
440 pcfg = &ctrl->pconfig[i];
441 p_rt->transport_params.port_num = p_rt->num;
442 p_rt->transport_params.sample_interval =
443 pcfg->si + 1;
444 p_rt->transport_params.offset1 = pcfg->off1;
445 p_rt->transport_params.offset2 = pcfg->off2;
446 i++;
447 }
448 }
449 }
450
451 return 0;
452 }
453
454 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
455 DEFAULT_CLK_FREQ,
456 };
457
458 static void qcom_swrm_slave_wq(struct work_struct *work)
459 {
460 struct qcom_swrm_ctrl *ctrl =
461 container_of(work, struct qcom_swrm_ctrl, slave_work);
462
463 qcom_swrm_get_device_status(ctrl);
464 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
465 }
466
467
468 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
469 struct sdw_stream_runtime *stream)
470 {
471 struct sdw_master_runtime *m_rt;
472 struct sdw_port_runtime *p_rt;
473 unsigned long *port_mask;
474
475 mutex_lock(&ctrl->port_lock);
476
477 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
478 if (m_rt->direction == SDW_DATA_DIR_RX)
479 port_mask = &ctrl->dout_port_mask;
480 else
481 port_mask = &ctrl->din_port_mask;
482
483 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
484 clear_bit(p_rt->num - 1, port_mask);
485 }
486
487 mutex_unlock(&ctrl->port_lock);
488 }
489
490 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
491 struct sdw_stream_runtime *stream,
492 struct snd_pcm_hw_params *params,
493 int direction)
494 {
495 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
496 struct sdw_stream_config sconfig;
497 struct sdw_master_runtime *m_rt;
498 struct sdw_slave_runtime *s_rt;
499 struct sdw_port_runtime *p_rt;
500 unsigned long *port_mask;
501 int i, maxport, pn, nports = 0, ret = 0;
502
503 mutex_lock(&ctrl->port_lock);
504 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
505 if (m_rt->direction == SDW_DATA_DIR_RX) {
506 maxport = ctrl->num_dout_ports;
507 port_mask = &ctrl->dout_port_mask;
508 } else {
509 maxport = ctrl->num_din_ports;
510 port_mask = &ctrl->din_port_mask;
511 }
512
513 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
514 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
515 /* Port numbers start from 1 - 14*/
516 pn = find_first_zero_bit(port_mask, maxport);
517 if (pn > (maxport - 1)) {
518 dev_err(ctrl->dev, "All ports busy\n");
519 ret = -EBUSY;
520 goto err;
521 }
522 set_bit(pn, port_mask);
523 pconfig[nports].num = pn + 1;
524 pconfig[nports].ch_mask = p_rt->ch_mask;
525 nports++;
526 }
527 }
528 }
529
530 if (direction == SNDRV_PCM_STREAM_CAPTURE)
531 sconfig.direction = SDW_DATA_DIR_TX;
532 else
533 sconfig.direction = SDW_DATA_DIR_RX;
534
535 /* hw parameters wil be ignored as we only support PDM */
536 sconfig.ch_count = 1;
537 sconfig.frame_rate = params_rate(params);
538 sconfig.type = stream->type;
539 sconfig.bps = 1;
540 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
541 nports, stream);
542 err:
543 if (ret) {
544 for (i = 0; i < nports; i++)
545 clear_bit(pconfig[i].num - 1, port_mask);
546 }
547
548 mutex_unlock(&ctrl->port_lock);
549
550 return ret;
551 }
552
553 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
554 struct snd_pcm_hw_params *params,
555 struct snd_soc_dai *dai)
556 {
557 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
558 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
559 int ret;
560
561 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
562 substream->stream);
563 if (ret)
564 qcom_swrm_stream_free_ports(ctrl, sruntime);
565
566 return ret;
567 }
568
569 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
570 struct snd_soc_dai *dai)
571 {
572 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
573 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
574
575 qcom_swrm_stream_free_ports(ctrl, sruntime);
576 sdw_stream_remove_master(&ctrl->bus, sruntime);
577
578 return 0;
579 }
580
581 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
582 void *stream, int direction)
583 {
584 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
585
586 ctrl->sruntime[dai->id] = stream;
587
588 return 0;
589 }
590
591 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
592 struct snd_soc_dai *dai)
593 {
594 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
595 struct snd_soc_pcm_runtime *rtd = substream->private_data;
596 struct sdw_stream_runtime *sruntime;
597 int ret, i;
598
599 sruntime = sdw_alloc_stream(dai->name);
600 if (!sruntime)
601 return -ENOMEM;
602
603 ctrl->sruntime[dai->id] = sruntime;
604
605 for (i = 0; i < rtd->num_codecs; i++) {
606 ret = snd_soc_dai_set_sdw_stream(rtd->codec_dais[i], sruntime,
607 substream->stream);
608 if (ret < 0 && ret != -ENOTSUPP) {
609 dev_err(dai->dev, "Failed to set sdw stream on %s",
610 rtd->codec_dais[i]->name);
611 sdw_release_stream(sruntime);
612 return ret;
613 }
614 }
615
616 return 0;
617 }
618
619 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
620 struct snd_soc_dai *dai)
621 {
622 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
623
624 sdw_release_stream(ctrl->sruntime[dai->id]);
625 ctrl->sruntime[dai->id] = NULL;
626 }
627
628 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
629 .hw_params = qcom_swrm_hw_params,
630 .hw_free = qcom_swrm_hw_free,
631 .startup = qcom_swrm_startup,
632 .shutdown = qcom_swrm_shutdown,
633 .set_sdw_stream = qcom_swrm_set_sdw_stream,
634 };
635
636 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
637 .name = "soundwire",
638 };
639
640 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
641 {
642 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
643 struct snd_soc_dai_driver *dais;
644 struct snd_soc_pcm_stream *stream;
645 struct device *dev = ctrl->dev;
646 int i;
647
648 /* PDM dais are only tested for now */
649 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
650 if (!dais)
651 return -ENOMEM;
652
653 for (i = 0; i < num_dais; i++) {
654 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
655 if (!dais[i].name)
656 return -ENOMEM;
657
658 if (i < ctrl->num_dout_ports)
659 stream = &dais[i].playback;
660 else
661 stream = &dais[i].capture;
662
663 stream->channels_min = 1;
664 stream->channels_max = 1;
665 stream->rates = SNDRV_PCM_RATE_48000;
666 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
667
668 dais[i].ops = &qcom_swrm_pdm_dai_ops;
669 dais[i].id = i;
670 }
671
672 return devm_snd_soc_register_component(ctrl->dev,
673 &qcom_swrm_dai_component,
674 dais, num_dais);
675 }
676
677 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
678 {
679 struct device_node *np = ctrl->dev->of_node;
680 u8 off1[QCOM_SDW_MAX_PORTS];
681 u8 off2[QCOM_SDW_MAX_PORTS];
682 u8 si[QCOM_SDW_MAX_PORTS];
683 int i, ret, nports, val;
684
685 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
686
687 ctrl->num_dout_ports = val & SWRM_COMP_PARAMS_DOUT_PORTS_MASK;
688 ctrl->num_din_ports = (val & SWRM_COMP_PARAMS_DIN_PORTS_MASK) >> 5;
689
690 ret = of_property_read_u32(np, "qcom,din-ports", &val);
691 if (ret)
692 return ret;
693
694 if (val > ctrl->num_din_ports)
695 return -EINVAL;
696
697 ctrl->num_din_ports = val;
698
699 ret = of_property_read_u32(np, "qcom,dout-ports", &val);
700 if (ret)
701 return ret;
702
703 if (val > ctrl->num_dout_ports)
704 return -EINVAL;
705
706 ctrl->num_dout_ports = val;
707
708 nports = ctrl->num_dout_ports + ctrl->num_din_ports;
709
710 ret = of_property_read_u8_array(np, "qcom,ports-offset1",
711 off1, nports);
712 if (ret)
713 return ret;
714
715 ret = of_property_read_u8_array(np, "qcom,ports-offset2",
716 off2, nports);
717 if (ret)
718 return ret;
719
720 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
721 si, nports);
722 if (ret)
723 return ret;
724
725 for (i = 0; i < nports; i++) {
726 ctrl->pconfig[i].si = si[i];
727 ctrl->pconfig[i].off1 = off1[i];
728 ctrl->pconfig[i].off2 = off2[i];
729 }
730
731 return 0;
732 }
733
734 static int qcom_swrm_probe(struct platform_device *pdev)
735 {
736 struct device *dev = &pdev->dev;
737 struct sdw_master_prop *prop;
738 struct sdw_bus_params *params;
739 struct qcom_swrm_ctrl *ctrl;
740 int ret;
741 u32 val;
742
743 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
744 if (!ctrl)
745 return -ENOMEM;
746
747 if (dev->parent->bus == &slimbus_bus) {
748 ctrl->reg_read = qcom_swrm_abh_reg_read;
749 ctrl->reg_write = qcom_swrm_ahb_reg_write;
750 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
751 if (!ctrl->regmap)
752 return -EINVAL;
753 } else {
754 /* Only WCD based SoundWire controller is supported */
755 return -ENOTSUPP;
756 }
757
758 ctrl->irq = of_irq_get(dev->of_node, 0);
759 if (ctrl->irq < 0)
760 return ctrl->irq;
761
762 ctrl->hclk = devm_clk_get(dev, "iface");
763 if (IS_ERR(ctrl->hclk))
764 return PTR_ERR(ctrl->hclk);
765
766 clk_prepare_enable(ctrl->hclk);
767
768 ctrl->dev = dev;
769 dev_set_drvdata(&pdev->dev, ctrl);
770 spin_lock_init(&ctrl->comp_lock);
771 mutex_init(&ctrl->port_lock);
772 INIT_WORK(&ctrl->slave_work, qcom_swrm_slave_wq);
773
774 ctrl->bus.dev = dev;
775 ctrl->bus.ops = &qcom_swrm_ops;
776 ctrl->bus.port_ops = &qcom_swrm_port_ops;
777 ctrl->bus.compute_params = &qcom_swrm_compute_params;
778
779 ret = qcom_swrm_get_port_config(ctrl);
780 if (ret)
781 return ret;
782
783 params = &ctrl->bus.params;
784 params->max_dr_freq = DEFAULT_CLK_FREQ;
785 params->curr_dr_freq = DEFAULT_CLK_FREQ;
786 params->col = SWRM_DEFAULT_COL;
787 params->row = SWRM_DEFAULT_ROWS;
788 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
789 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
790 params->next_bank = !params->curr_bank;
791
792 prop = &ctrl->bus.prop;
793 prop->max_clk_freq = DEFAULT_CLK_FREQ;
794 prop->num_clk_gears = 0;
795 prop->num_clk_freq = MAX_FREQ_NUM;
796 prop->clk_freq = &qcom_swrm_freq_tbl[0];
797 prop->default_col = SWRM_DEFAULT_COL;
798 prop->default_row = SWRM_DEFAULT_ROWS;
799
800 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
801
802 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
803 qcom_swrm_irq_handler,
804 IRQF_TRIGGER_RISING,
805 "soundwire", ctrl);
806 if (ret) {
807 dev_err(dev, "Failed to request soundwire irq\n");
808 goto err;
809 }
810
811 ret = sdw_add_bus_master(&ctrl->bus);
812 if (ret) {
813 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
814 ret);
815 goto err;
816 }
817
818 qcom_swrm_init(ctrl);
819 ret = qcom_swrm_register_dais(ctrl);
820 if (ret)
821 goto err;
822
823 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
824 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
825 ctrl->version & 0xffff);
826
827 return 0;
828 err:
829 clk_disable_unprepare(ctrl->hclk);
830 return ret;
831 }
832
833 static int qcom_swrm_remove(struct platform_device *pdev)
834 {
835 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
836
837 sdw_delete_bus_master(&ctrl->bus);
838 clk_disable_unprepare(ctrl->hclk);
839
840 return 0;
841 }
842
843 static const struct of_device_id qcom_swrm_of_match[] = {
844 { .compatible = "qcom,soundwire-v1.3.0", },
845 {/* sentinel */},
846 };
847
848 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
849
850 static struct platform_driver qcom_swrm_driver = {
851 .probe = &qcom_swrm_probe,
852 .remove = &qcom_swrm_remove,
853 .driver = {
854 .name = "qcom-soundwire",
855 .of_match_table = qcom_swrm_of_match,
856 }
857 };
858 module_platform_driver(qcom_swrm_driver);
859
860 MODULE_DESCRIPTION("Qualcomm soundwire driver");
861 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support