drivers/spi/spi-meson-spicc.c

   1 /*
   2  * Driver for Amlogic Meson SPI communication controller (SPICC)
   3  *
   4  * Copyright (C) BayLibre, SAS
   5  * Author: Neil Armstrong <narmstrong@baylibre.com>
   6  *
   7  * SPDX-License-Identifier: GPL-2.0+
   8  */
   9
  10 #include <linux/bitfield.h>
  11 #include <linux/clk.h>
  12 #include <linux/device.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/types.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/reset.h>
  22
  23 /*
  24  * The Meson SPICC controller could support DMA based transfers, but is not
  25  * implemented by the vendor code, and while having the registers documentation
  26  * it has never worked on the GXL Hardware.
  27  * The PIO mode is the only mode implemented, and due to badly designed HW :
  28  * - all transfers are cutted in 16 words burst because the FIFO hangs on
  29  *   TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
  30  *   FIFO max size chunk only
  31  * - CS management is dumb, and goes UP between every burst, so is really a
  32  *   "Data Valid" signal than a Chip Select, GPIO link should be used instead
  33  *   to have a CS go down over the full transfer
  34  */
  35
  36 #define SPICC_MAX_FREQ  30000000
  37 #define SPICC_MAX_BURST 128
  38
  39 /* Register Map */
  40 #define SPICC_RXDATA    0x00
  41
  42 #define SPICC_TXDATA    0x04
  43
  44 #define SPICC_CONREG    0x08
  45 #define SPICC_ENABLE            BIT(0)
  46 #define SPICC_MODE_MASTER       BIT(1)
  47 #define SPICC_XCH               BIT(2)
  48 #define SPICC_SMC               BIT(3)
  49 #define SPICC_POL               BIT(4)
  50 #define SPICC_PHA               BIT(5)
  51 #define SPICC_SSCTL             BIT(6)
  52 #define SPICC_SSPOL             BIT(7)
  53 #define SPICC_DRCTL_MASK        GENMASK(9, 8)
  54 #define SPICC_DRCTL_IGNORE      0
  55 #define SPICC_DRCTL_FALLING     1
  56 #define SPICC_DRCTL_LOWLEVEL    2
  57 #define SPICC_CS_MASK           GENMASK(13, 12)
  58 #define SPICC_DATARATE_MASK     GENMASK(18, 16)
  59 #define SPICC_DATARATE_DIV4     0
  60 #define SPICC_DATARATE_DIV8     1
  61 #define SPICC_DATARATE_DIV16    2
  62 #define SPICC_DATARATE_DIV32    3
  63 #define SPICC_BITLENGTH_MASK    GENMASK(24, 19)
  64 #define SPICC_BURSTLENGTH_MASK  GENMASK(31, 25)
  65
  66 #define SPICC_INTREG    0x0c
  67 #define SPICC_TE_EN     BIT(0) /* TX FIFO Empty Interrupt */
  68 #define SPICC_TH_EN     BIT(1) /* TX FIFO Half-Full Interrupt */
  69 #define SPICC_TF_EN     BIT(2) /* TX FIFO Full Interrupt */
  70 #define SPICC_RR_EN     BIT(3) /* RX FIFO Ready Interrupt */
  71 #define SPICC_RH_EN     BIT(4) /* RX FIFO Half-Full Interrupt */
  72 #define SPICC_RF_EN     BIT(5) /* RX FIFO Full Interrupt */
  73 #define SPICC_RO_EN     BIT(6) /* RX FIFO Overflow Interrupt */
  74 #define SPICC_TC_EN     BIT(7) /* Transfert Complete Interrupt */
  75
  76 #define SPICC_DMAREG    0x10
  77 #define SPICC_DMA_ENABLE                BIT(0)
  78 #define SPICC_TXFIFO_THRESHOLD_MASK     GENMASK(5, 1)
  79 #define SPICC_RXFIFO_THRESHOLD_MASK     GENMASK(10, 6)
  80 #define SPICC_READ_BURST_MASK           GENMASK(14, 11)
  81 #define SPICC_WRITE_BURST_MASK          GENMASK(18, 15)
  82 #define SPICC_DMA_URGENT                BIT(19)
  83 #define SPICC_DMA_THREADID_MASK         GENMASK(25, 20)
  84 #define SPICC_DMA_BURSTNUM_MASK         GENMASK(31, 26)
  85
  86 #define SPICC_STATREG   0x14
  87 #define SPICC_TE        BIT(0) /* TX FIFO Empty Interrupt */
  88 #define SPICC_TH        BIT(1) /* TX FIFO Half-Full Interrupt */
  89 #define SPICC_TF        BIT(2) /* TX FIFO Full Interrupt */
  90 #define SPICC_RR        BIT(3) /* RX FIFO Ready Interrupt */
  91 #define SPICC_RH        BIT(4) /* RX FIFO Half-Full Interrupt */
  92 #define SPICC_RF        BIT(5) /* RX FIFO Full Interrupt */
  93 #define SPICC_RO        BIT(6) /* RX FIFO Overflow Interrupt */
  94 #define SPICC_TC        BIT(7) /* Transfert Complete Interrupt */
  95
  96 #define SPICC_PERIODREG 0x18
  97 #define SPICC_PERIOD    GENMASK(14, 0)  /* Wait cycles */
  98
  99 #define SPICC_TESTREG   0x1c
 100 #define SPICC_TXCNT_MASK        GENMASK(4, 0)   /* TX FIFO Counter */
 101 #define SPICC_RXCNT_MASK        GENMASK(9, 5)   /* RX FIFO Counter */
 102 #define SPICC_SMSTATUS_MASK     GENMASK(12, 10) /* State Machine Status */
 103 #define SPICC_LBC_RO            BIT(13) /* Loop Back Control Read-Only */
 104 #define SPICC_LBC_W1            BIT(14) /* Loop Back Control Write-Only */
 105 #define SPICC_SWAP_RO           BIT(14) /* RX FIFO Data Swap Read-Only */
 106 #define SPICC_SWAP_W1           BIT(15) /* RX FIFO Data Swap Write-Only */
 107 #define SPICC_DLYCTL_RO_MASK    GENMASK(20, 15) /* Delay Control Read-Only */
 108 #define SPICC_DLYCTL_W1_MASK    GENMASK(21, 16) /* Delay Control Write-Only */
 109 #define SPICC_FIFORST_RO_MASK   GENMASK(22, 21) /* FIFO Softreset Read-Only */
 110 #define SPICC_FIFORST_W1_MASK   GENMASK(23, 22) /* FIFO Softreset Write-Only */
 111
 112 #define SPICC_DRADDR    0x20    /* Read Address of DMA */
 113
 114 #define SPICC_DWADDR    0x24    /* Write Address of DMA */
 115
 116 #define writel_bits_relaxed(mask, val, addr) \
 117         writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
 118
 119 #define SPICC_BURST_MAX 16
 120 #define SPICC_FIFO_HALF 10
 121
 122 struct meson_spicc_device {
 123         struct spi_master               *master;
 124         struct platform_device          *pdev;
 125         void __iomem                    *base;
 126         struct clk                      *core;
 127         struct spi_message              *message;
 128         struct spi_transfer             *xfer;
 129         u8                              *tx_buf;
 130         u8                              *rx_buf;
 131         unsigned int                    bytes_per_word;
 132         unsigned long                   tx_remain;
 133         unsigned long                   txb_remain;
 134         unsigned long                   rx_remain;
 135         unsigned long                   rxb_remain;
 136         unsigned long                   xfer_remain;
 137         bool                            is_burst_end;
 138         bool                            is_last_burst;
 139 };
 140
 141 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
 142 {
 143         return !!FIELD_GET(SPICC_TF,
 144                            readl_relaxed(spicc->base + SPICC_STATREG));
 145 }
 146
 147 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
 148 {
 149         return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF_EN,
 150                          readl_relaxed(spicc->base + SPICC_STATREG));
 151 }
 152
 153 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
 154 {
 155         unsigned int bytes = spicc->bytes_per_word;
 156         unsigned int byte_shift = 0;
 157         u32 data = 0;
 158         u8 byte;
 159
 160         while (bytes--) {
 161                 byte = *spicc->tx_buf++;
 162                 data |= (byte & 0xff) << byte_shift;
 163                 byte_shift += 8;
 164         }
 165
 166         spicc->tx_remain--;
 167         return data;
 168 }
 169
 170 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
 171                                          u32 data)
 172 {
 173         unsigned int bytes = spicc->bytes_per_word;
 174         unsigned int byte_shift = 0;
 175         u8 byte;
 176
 177         while (bytes--) {
 178                 byte = (data >> byte_shift) & 0xff;
 179                 *spicc->rx_buf++ = byte;
 180                 byte_shift += 8;
 181         }
 182
 183         spicc->rx_remain--;
 184 }
 185
 186 static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
 187 {
 188         /* Empty RX FIFO */
 189         while (spicc->rx_remain &&
 190                meson_spicc_rxready(spicc))
 191                 meson_spicc_push_data(spicc,
 192                                 readl_relaxed(spicc->base + SPICC_RXDATA));
 193 }
 194
 195 static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
 196 {
 197         /* Fill Up TX FIFO */
 198         while (spicc->tx_remain &&
 199                !meson_spicc_txfull(spicc))
 200                 writel_relaxed(meson_spicc_pull_data(spicc),
 201                                spicc->base + SPICC_TXDATA);
 202 }
 203
 204 static inline u32 meson_spicc_setup_rx_irq(struct meson_spicc_device *spicc,
 205                                            u32 irq_ctrl)
 206 {
 207         if (spicc->rx_remain > SPICC_FIFO_HALF)
 208                 irq_ctrl |= SPICC_RH_EN;
 209         else
 210                 irq_ctrl |= SPICC_RR_EN;
 211
 212         return irq_ctrl;
 213 }
 214
 215 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc,
 216                                            unsigned int burst_len)
 217 {
 218         /* Setup Xfer variables */
 219         spicc->tx_remain = burst_len;
 220         spicc->rx_remain = burst_len;
 221         spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
 222         spicc->is_burst_end = false;
 223         if (burst_len < SPICC_BURST_MAX || !spicc->xfer_remain)
 224                 spicc->is_last_burst = true;
 225         else
 226                 spicc->is_last_burst = false;
 227
 228         /* Setup burst length */
 229         writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
 230                         FIELD_PREP(SPICC_BURSTLENGTH_MASK,
 231                                 burst_len),
 232                         spicc->base + SPICC_CONREG);
 233
 234         /* Fill TX FIFO */
 235         meson_spicc_tx(spicc);
 236 }
 237
 238 static irqreturn_t meson_spicc_irq(int irq, void *data)
 239 {
 240         struct meson_spicc_device *spicc = (void *) data;
 241         u32 ctrl = readl_relaxed(spicc->base + SPICC_INTREG);
 242         u32 stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl;
 243
 244         ctrl &= ~(SPICC_RH_EN | SPICC_RR_EN);
 245
 246         /* Empty RX FIFO */
 247         meson_spicc_rx(spicc);
 248
 249         /* Enable TC interrupt since we transferred everything */
 250         if (!spicc->tx_remain && !spicc->rx_remain) {
 251                 spicc->is_burst_end = true;
 252
 253                 /* Enable TC interrupt */
 254                 ctrl |= SPICC_TC_EN;
 255
 256                 /* Reload IRQ status */
 257                 stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl;
 258         }
 259
 260         /* Check transfer complete */
 261         if ((stat & SPICC_TC) && spicc->is_burst_end) {
 262                 unsigned int burst_len;
 263
 264                 /* Clear TC bit */
 265                 writel_relaxed(SPICC_TC, spicc->base + SPICC_STATREG);
 266
 267                 /* Disable TC interrupt */
 268                 ctrl &= ~SPICC_TC_EN;
 269
 270                 if (spicc->is_last_burst) {
 271                         /* Disable all IRQs */
 272                         writel(0, spicc->base + SPICC_INTREG);
 273
 274                         spi_finalize_current_transfer(spicc->master);
 275
 276                         return IRQ_HANDLED;
 277                 }
 278
 279                 burst_len = min_t(unsigned int,
 280                                   spicc->xfer_remain / spicc->bytes_per_word,
 281                                   SPICC_BURST_MAX);
 282
 283                 /* Setup burst */
 284                 meson_spicc_setup_burst(spicc, burst_len);
 285
 286                 /* Restart burst */
 287                 writel_bits_relaxed(SPICC_XCH, SPICC_XCH,
 288                                     spicc->base + SPICC_CONREG);
 289         }
 290
 291         /* Setup RX interrupt trigger */
 292         ctrl = meson_spicc_setup_rx_irq(spicc, ctrl);
 293
 294         /* Reconfigure interrupts */
 295         writel(ctrl, spicc->base + SPICC_INTREG);
 296
 297         return IRQ_HANDLED;
 298 }
 299
 300 static u32 meson_spicc_setup_speed(struct meson_spicc_device *spicc, u32 conf,
 301                                    u32 speed)
 302 {
 303         unsigned long parent, value;
 304         unsigned int i, div;
 305
 306         parent = clk_get_rate(spicc->core);
 307
 308         /* Find closest inferior/equal possible speed */
 309         for (i = 0 ; i < 7 ; ++i) {
 310                 /* 2^(data_rate+2) */
 311                 value = parent >> (i + 2);
 312
 313                 if (value <= speed)
 314                         break;
 315         }
 316
 317         /* If provided speed it lower than max divider, use max divider */
 318         if (i > 7) {
 319                 div = 7;
 320                 dev_warn_once(&spicc->pdev->dev, "unable to get close to speed %u\n",
 321                               speed);
 322         } else
 323                 div = i;
 324
 325         dev_dbg(&spicc->pdev->dev, "parent %lu, speed %u -> %lu (%u)\n",
 326                 parent, speed, value, div);
 327
 328         conf &= ~SPICC_DATARATE_MASK;
 329         conf |= FIELD_PREP(SPICC_DATARATE_MASK, div);
 330
 331         return conf;
 332 }
 333
 334 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 335                                    struct spi_transfer *xfer)
 336 {
 337         u32 conf, conf_orig;
 338
 339         /* Read original configuration */
 340         conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
 341
 342         /* Select closest divider */
 343         conf = meson_spicc_setup_speed(spicc, conf, xfer->speed_hz);
 344
 345         /* Setup word width */
 346         conf &= ~SPICC_BITLENGTH_MASK;
 347         conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
 348                            (spicc->bytes_per_word << 3) - 1);
 349
 350         /* Ignore if unchanged */
 351         if (conf != conf_orig)
 352                 writel_relaxed(conf, spicc->base + SPICC_CONREG);
 353 }
 354
 355 static int meson_spicc_transfer_one(struct spi_master *master,
 356                                     struct spi_device *spi,
 357                                     struct spi_transfer *xfer)
 358 {
 359         struct meson_spicc_device *spicc = spi_master_get_devdata(master);
 360         unsigned int burst_len;
 361         u32 irq = 0;
 362
 363         /* Store current transfer */
 364         spicc->xfer = xfer;
 365
 366         /* Setup transfer parameters */
 367         spicc->tx_buf = (u8 *)xfer->tx_buf;
 368         spicc->rx_buf = (u8 *)xfer->rx_buf;
 369         spicc->xfer_remain = xfer->len;
 370
 371         /* Pre-calculate word size */
 372         spicc->bytes_per_word =
 373            DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
 374
 375         /* Setup transfer parameters */
 376         meson_spicc_setup_xfer(spicc, xfer);
 377
 378         burst_len = min_t(unsigned int,
 379                           spicc->xfer_remain / spicc->bytes_per_word,
 380                           SPICC_BURST_MAX);
 381
 382         meson_spicc_setup_burst(spicc, burst_len);
 383
 384         irq = meson_spicc_setup_rx_irq(spicc, irq);
 385
 386         /* Start burst */
 387         writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
 388
 389         /* Enable interrupts */
 390         writel_relaxed(irq, spicc->base + SPICC_INTREG);
 391
 392         return 1;
 393 }
 394
 395 static int meson_spicc_prepare_message(struct spi_master *master,
 396                                        struct spi_message *message)
 397 {
 398         struct meson_spicc_device *spicc = spi_master_get_devdata(master);
 399         struct spi_device *spi = message->spi;
 400         u32 conf = 0;
 401
 402         /* Store current message */
 403         spicc->message = message;
 404
 405         /* Enable Master */
 406         conf |= SPICC_ENABLE;
 407         conf |= SPICC_MODE_MASTER;
 408
 409         /* SMC = 0 */
 410
 411         /* Setup transfer mode */
 412         if (spi->mode & SPI_CPOL)
 413                 conf |= SPICC_POL;
 414         else
 415                 conf &= ~SPICC_POL;
 416
 417         if (spi->mode & SPI_CPHA)
 418                 conf |= SPICC_PHA;
 419         else
 420                 conf &= ~SPICC_PHA;
 421
 422         /* SSCTL = 0 */
 423
 424         if (spi->mode & SPI_CS_HIGH)
 425                 conf |= SPICC_SSPOL;
 426         else
 427                 conf &= ~SPICC_SSPOL;
 428
 429         if (spi->mode & SPI_READY)
 430                 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
 431         else
 432                 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
 433
 434         /* Select CS */
 435         conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
 436
 437         /* Default Clock rate core/4 */
 438
 439         /* Default 8bit word */
 440         conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
 441
 442         writel_relaxed(conf, spicc->base + SPICC_CONREG);
 443
 444         /* Setup no wait cycles by default */
 445         writel_relaxed(0, spicc->base + SPICC_PERIODREG);
 446
 447         writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
 448
 449         return 0;
 450 }
 451
 452 static int meson_spicc_unprepare_transfer(struct spi_master *master)
 453 {
 454         struct meson_spicc_device *spicc = spi_master_get_devdata(master);
 455
 456         /* Disable all IRQs */
 457         writel(0, spicc->base + SPICC_INTREG);
 458
 459         /* Disable controller */
 460         writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG);
 461
 462         device_reset_optional(&spicc->pdev->dev);
 463
 464         return 0;
 465 }
 466
 467 static int meson_spicc_setup(struct spi_device *spi)
 468 {
 469         if (!spi->controller_state)
 470                 spi->controller_state = spi_master_get_devdata(spi->master);
 471
 472         return 0;
 473 }
 474
 475 static void meson_spicc_cleanup(struct spi_device *spi)
 476 {
 477         spi->controller_state = NULL;
 478 }
 479
 480 static int meson_spicc_probe(struct platform_device *pdev)
 481 {
 482         struct spi_master *master;
 483         struct meson_spicc_device *spicc;
 484         int ret, irq, rate;
 485
 486         master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
 487         if (!master) {
 488                 dev_err(&pdev->dev, "master allocation failed\n");
 489                 return -ENOMEM;
 490         }
 491         spicc = spi_master_get_devdata(master);
 492         spicc->master = master;
 493
 494         spicc->pdev = pdev;
 495         platform_set_drvdata(pdev, spicc);
 496
 497         spicc->base = devm_platform_ioremap_resource(pdev, 0);
 498         if (IS_ERR(spicc->base)) {
 499                 dev_err(&pdev->dev, "io resource mapping failed\n");
 500                 ret = PTR_ERR(spicc->base);
 501                 goto out_master;
 502         }
 503
 504         /* Disable all IRQs */
 505         writel_relaxed(0, spicc->base + SPICC_INTREG);
 506
 507         irq = platform_get_irq(pdev, 0);
 508         ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
 509                                0, NULL, spicc);
 510         if (ret) {
 511                 dev_err(&pdev->dev, "irq request failed\n");
 512                 goto out_master;
 513         }
 514
 515         spicc->core = devm_clk_get(&pdev->dev, "core");
 516         if (IS_ERR(spicc->core)) {
 517                 dev_err(&pdev->dev, "core clock request failed\n");
 518                 ret = PTR_ERR(spicc->core);
 519                 goto out_master;
 520         }
 521
 522         ret = clk_prepare_enable(spicc->core);
 523         if (ret) {
 524                 dev_err(&pdev->dev, "core clock enable failed\n");
 525                 goto out_master;
 526         }
 527         rate = clk_get_rate(spicc->core);
 528
 529         device_reset_optional(&pdev->dev);
 530
 531         master->num_chipselect = 4;
 532         master->dev.of_node = pdev->dev.of_node;
 533         master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
 534         master->bits_per_word_mask = SPI_BPW_MASK(32) |
 535                                      SPI_BPW_MASK(24) |
 536                                      SPI_BPW_MASK(16) |
 537                                      SPI_BPW_MASK(8);
 538         master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
 539         master->min_speed_hz = rate >> 9;
 540         master->setup = meson_spicc_setup;
 541         master->cleanup = meson_spicc_cleanup;
 542         master->prepare_message = meson_spicc_prepare_message;
 543         master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
 544         master->transfer_one = meson_spicc_transfer_one;
 545         master->use_gpio_descriptors = true;
 546
 547         /* Setup max rate according to the Meson GX datasheet */
 548         if ((rate >> 2) > SPICC_MAX_FREQ)
 549                 master->max_speed_hz = SPICC_MAX_FREQ;
 550         else
 551                 master->max_speed_hz = rate >> 2;
 552
 553         ret = devm_spi_register_master(&pdev->dev, master);
 554         if (ret) {
 555                 dev_err(&pdev->dev, "spi master registration failed\n");
 556                 goto out_clk;
 557         }
 558
 559         return 0;
 560
 561 out_clk:
 562         clk_disable_unprepare(spicc->core);
 563
 564 out_master:
 565         spi_master_put(master);
 566
 567         return ret;
 568 }
 569
 570 static int meson_spicc_remove(struct platform_device *pdev)
 571 {
 572         struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
 573
 574         /* Disable SPI */
 575         writel(0, spicc->base + SPICC_CONREG);
 576
 577         clk_disable_unprepare(spicc->core);
 578
 579         return 0;
 580 }
 581
 582 static const struct of_device_id meson_spicc_of_match[] = {
 583         { .compatible = "amlogic,meson-gx-spicc", },
 584         { .compatible = "amlogic,meson-axg-spicc", },
 585         { /* sentinel */ }
 586 };
 587 MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
 588
 589 static struct platform_driver meson_spicc_driver = {
 590         .probe   = meson_spicc_probe,
 591         .remove  = meson_spicc_remove,
 592         .driver  = {
 593                 .name = "meson-spicc",
 594                 .of_match_table = of_match_ptr(meson_spicc_of_match),
 595         },
 596 };
 597
 598 module_platform_driver(meson_spicc_driver);
 599
 600 MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
 601 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 602 MODULE_LICENSE("GPL");