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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / spi / spi-omap-100k.c
blob5c704ba6d8ea90117458117fc26fb2367ea82393
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * OMAP7xx SPI 100k controller driver
4 * Author: Fabrice Crohas <fcrohas@gmail.com>
5 * from original omap1_mcspi driver
6 *
7 * Copyright (C) 2005, 2006 Nokia Corporation
8 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
9 * Juha Yrj�l� <juha.yrjola@nokia.com>
10 */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/device.h>
16 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/gpio.h>
23 #include <linux/slab.h>
24
25 #include <linux/spi/spi.h>
26
27 #define OMAP1_SPI100K_MAX_FREQ 48000000
28
29 #define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
30
31 #define SPI_SETUP1 0x00
32 #define SPI_SETUP2 0x02
33 #define SPI_CTRL 0x04
34 #define SPI_STATUS 0x06
35 #define SPI_TX_LSB 0x08
36 #define SPI_TX_MSB 0x0a
37 #define SPI_RX_LSB 0x0c
38 #define SPI_RX_MSB 0x0e
39
40 #define SPI_SETUP1_INT_READ_ENABLE (1UL << 5)
41 #define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4)
42 #define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1)
43 #define SPI_SETUP1_CLOCK_ENABLE (1UL << 0)
44
45 #define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0)
46 #define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0)
47 #define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5)
48 #define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5)
49 #define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10)
50 #define SPI_SETUP2_EDGE_TRIGGER (1UL << 10)
51
52 #define SPI_CTRL_SEN(x) ((x) << 7)
53 #define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2)
54 #define SPI_CTRL_WR (1UL << 1)
55 #define SPI_CTRL_RD (1UL << 0)
56
57 #define SPI_STATUS_WE (1UL << 1)
58 #define SPI_STATUS_RD (1UL << 0)
59
60 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
61 * cache operations; better heuristics consider wordsize and bitrate.
62 */
63 #define DMA_MIN_BYTES 8
64
65 #define SPI_RUNNING 0
66 #define SPI_SHUTDOWN 1
67
68 struct omap1_spi100k {
69 struct clk *ick;
70 struct clk *fck;
71
72 /* Virtual base address of the controller */
73 void __iomem *base;
74 };
75
76 struct omap1_spi100k_cs {
77 void __iomem *base;
78 int word_len;
79 };
80
81 static void spi100k_enable_clock(struct spi_master *master)
82 {
83 unsigned int val;
84 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
85
86 /* enable SPI */
87 val = readw(spi100k->base + SPI_SETUP1);
88 val |= SPI_SETUP1_CLOCK_ENABLE;
89 writew(val, spi100k->base + SPI_SETUP1);
90 }
91
92 static void spi100k_disable_clock(struct spi_master *master)
93 {
94 unsigned int val;
95 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
96
97 /* disable SPI */
98 val = readw(spi100k->base + SPI_SETUP1);
99 val &= ~SPI_SETUP1_CLOCK_ENABLE;
100 writew(val, spi100k->base + SPI_SETUP1);
101 }
102
103 static void spi100k_write_data(struct spi_master *master, int len, int data)
104 {
105 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
106
107 /* write 16-bit word, shifting 8-bit data if necessary */
108 if (len <= 8) {
109 data <<= 8;
110 len = 16;
111 }
112
113 spi100k_enable_clock(master);
114 writew(data , spi100k->base + SPI_TX_MSB);
115
116 writew(SPI_CTRL_SEN(0) |
117 SPI_CTRL_WORD_SIZE(len) |
118 SPI_CTRL_WR,
119 spi100k->base + SPI_CTRL);
120
121 /* Wait for bit ack send change */
122 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
123 ;
124 udelay(1000);
125
126 spi100k_disable_clock(master);
127 }
128
129 static int spi100k_read_data(struct spi_master *master, int len)
130 {
131 int dataL;
132 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
133
134 /* Always do at least 16 bits */
135 if (len <= 8)
136 len = 16;
137
138 spi100k_enable_clock(master);
139 writew(SPI_CTRL_SEN(0) |
140 SPI_CTRL_WORD_SIZE(len) |
141 SPI_CTRL_RD,
142 spi100k->base + SPI_CTRL);
143
144 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
145 ;
146 udelay(1000);
147
148 dataL = readw(spi100k->base + SPI_RX_LSB);
149 readw(spi100k->base + SPI_RX_MSB);
150 spi100k_disable_clock(master);
151
152 return dataL;
153 }
154
155 static void spi100k_open(struct spi_master *master)
156 {
157 /* get control of SPI */
158 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
159
160 writew(SPI_SETUP1_INT_READ_ENABLE |
161 SPI_SETUP1_INT_WRITE_ENABLE |
162 SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
163
164 /* configure clock and interrupts */
165 writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
166 SPI_SETUP2_NEGATIVE_LEVEL |
167 SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
168 }
169
170 static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
171 {
172 if (enable)
173 writew(0x05fc, spi100k->base + SPI_CTRL);
174 else
175 writew(0x05fd, spi100k->base + SPI_CTRL);
176 }
177
178 static unsigned
179 omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
180 {
181 struct omap1_spi100k_cs *cs = spi->controller_state;
182 unsigned int count, c;
183 int word_len;
184
185 count = xfer->len;
186 c = count;
187 word_len = cs->word_len;
188
189 if (word_len <= 8) {
190 u8 *rx;
191 const u8 *tx;
192
193 rx = xfer->rx_buf;
194 tx = xfer->tx_buf;
195 do {
196 c -= 1;
197 if (xfer->tx_buf != NULL)
198 spi100k_write_data(spi->master, word_len, *tx++);
199 if (xfer->rx_buf != NULL)
200 *rx++ = spi100k_read_data(spi->master, word_len);
201 } while (c);
202 } else if (word_len <= 16) {
203 u16 *rx;
204 const u16 *tx;
205
206 rx = xfer->rx_buf;
207 tx = xfer->tx_buf;
208 do {
209 c -= 2;
210 if (xfer->tx_buf != NULL)
211 spi100k_write_data(spi->master, word_len, *tx++);
212 if (xfer->rx_buf != NULL)
213 *rx++ = spi100k_read_data(spi->master, word_len);
214 } while (c);
215 } else if (word_len <= 32) {
216 u32 *rx;
217 const u32 *tx;
218
219 rx = xfer->rx_buf;
220 tx = xfer->tx_buf;
221 do {
222 c -= 4;
223 if (xfer->tx_buf != NULL)
224 spi100k_write_data(spi->master, word_len, *tx);
225 if (xfer->rx_buf != NULL)
226 *rx = spi100k_read_data(spi->master, word_len);
227 } while (c);
228 }
229 return count - c;
230 }
231
232 /* called only when no transfer is active to this device */
233 static int omap1_spi100k_setup_transfer(struct spi_device *spi,
234 struct spi_transfer *t)
235 {
236 struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
237 struct omap1_spi100k_cs *cs = spi->controller_state;
238 u8 word_len;
239
240 if (t != NULL)
241 word_len = t->bits_per_word;
242 else
243 word_len = spi->bits_per_word;
244
245 if (spi->bits_per_word > 32)
246 return -EINVAL;
247 cs->word_len = word_len;
248
249 /* SPI init before transfer */
250 writew(0x3e , spi100k->base + SPI_SETUP1);
251 writew(0x00 , spi100k->base + SPI_STATUS);
252 writew(0x3e , spi100k->base + SPI_CTRL);
253
254 return 0;
255 }
256
257 /* the spi->mode bits understood by this driver: */
258 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
259
260 static int omap1_spi100k_setup(struct spi_device *spi)
261 {
262 int ret;
263 struct omap1_spi100k *spi100k;
264 struct omap1_spi100k_cs *cs = spi->controller_state;
265
266 spi100k = spi_master_get_devdata(spi->master);
267
268 if (!cs) {
269 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
270 if (!cs)
271 return -ENOMEM;
272 cs->base = spi100k->base + spi->chip_select * 0x14;
273 spi->controller_state = cs;
274 }
275
276 spi100k_open(spi->master);
277
278 clk_prepare_enable(spi100k->ick);
279 clk_prepare_enable(spi100k->fck);
280
281 ret = omap1_spi100k_setup_transfer(spi, NULL);
282
283 clk_disable_unprepare(spi100k->ick);
284 clk_disable_unprepare(spi100k->fck);
285
286 return ret;
287 }
288
289 static int omap1_spi100k_transfer_one_message(struct spi_master *master,
290 struct spi_message *m)
291 {
292 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
293 struct spi_device *spi = m->spi;
294 struct spi_transfer *t = NULL;
295 int cs_active = 0;
296 int status = 0;
297
298 list_for_each_entry(t, &m->transfers, transfer_list) {
299 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
300 status = -EINVAL;
301 break;
302 }
303 status = omap1_spi100k_setup_transfer(spi, t);
304 if (status < 0)
305 break;
306
307 if (!cs_active) {
308 omap1_spi100k_force_cs(spi100k, 1);
309 cs_active = 1;
310 }
311
312 if (t->len) {
313 unsigned count;
314
315 count = omap1_spi100k_txrx_pio(spi, t);
316 m->actual_length += count;
317
318 if (count != t->len) {
319 status = -EIO;
320 break;
321 }
322 }
323
324 spi_transfer_delay_exec(t);
325
326 /* ignore the "leave it on after last xfer" hint */
327
328 if (t->cs_change) {
329 omap1_spi100k_force_cs(spi100k, 0);
330 cs_active = 0;
331 }
332 }
333
334 status = omap1_spi100k_setup_transfer(spi, NULL);
335
336 if (cs_active)
337 omap1_spi100k_force_cs(spi100k, 0);
338
339 m->status = status;
340
341 spi_finalize_current_message(master);
342
343 return status;
344 }
345
346 static int omap1_spi100k_probe(struct platform_device *pdev)
347 {
348 struct spi_master *master;
349 struct omap1_spi100k *spi100k;
350 int status = 0;
351
352 if (!pdev->id)
353 return -EINVAL;
354
355 master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
356 if (master == NULL) {
357 dev_dbg(&pdev->dev, "master allocation failed\n");
358 return -ENOMEM;
359 }
360
361 if (pdev->id != -1)
362 master->bus_num = pdev->id;
363
364 master->setup = omap1_spi100k_setup;
365 master->transfer_one_message = omap1_spi100k_transfer_one_message;
366 master->num_chipselect = 2;
367 master->mode_bits = MODEBITS;
368 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
369 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
370 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
371 master->auto_runtime_pm = true;
372
373 spi100k = spi_master_get_devdata(master);
374
375 /*
376 * The memory region base address is taken as the platform_data.
377 * You should allocate this with ioremap() before initializing
378 * the SPI.
379 */
380 spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
381
382 spi100k->ick = devm_clk_get(&pdev->dev, "ick");
383 if (IS_ERR(spi100k->ick)) {
384 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
385 status = PTR_ERR(spi100k->ick);
386 goto err;
387 }
388
389 spi100k->fck = devm_clk_get(&pdev->dev, "fck");
390 if (IS_ERR(spi100k->fck)) {
391 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
392 status = PTR_ERR(spi100k->fck);
393 goto err;
394 }
395
396 status = clk_prepare_enable(spi100k->ick);
397 if (status != 0) {
398 dev_err(&pdev->dev, "failed to enable ick: %d\n", status);
399 goto err;
400 }
401
402 status = clk_prepare_enable(spi100k->fck);
403 if (status != 0) {
404 dev_err(&pdev->dev, "failed to enable fck: %d\n", status);
405 goto err_ick;
406 }
407
408 pm_runtime_enable(&pdev->dev);
409 pm_runtime_set_active(&pdev->dev);
410
411 status = devm_spi_register_master(&pdev->dev, master);
412 if (status < 0)
413 goto err_fck;
414
415 return status;
416
417 err_fck:
418 clk_disable_unprepare(spi100k->fck);
419 err_ick:
420 clk_disable_unprepare(spi100k->ick);
421 err:
422 spi_master_put(master);
423 return status;
424 }
425
426 static int omap1_spi100k_remove(struct platform_device *pdev)
427 {
428 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
429 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
430
431 pm_runtime_disable(&pdev->dev);
432
433 clk_disable_unprepare(spi100k->fck);
434 clk_disable_unprepare(spi100k->ick);
435
436 return 0;
437 }
438
439 #ifdef CONFIG_PM
440 static int omap1_spi100k_runtime_suspend(struct device *dev)
441 {
442 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
443 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
444
445 clk_disable_unprepare(spi100k->ick);
446 clk_disable_unprepare(spi100k->fck);
447
448 return 0;
449 }
450
451 static int omap1_spi100k_runtime_resume(struct device *dev)
452 {
453 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
454 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
455 int ret;
456
457 ret = clk_prepare_enable(spi100k->ick);
458 if (ret != 0) {
459 dev_err(dev, "Failed to enable ick: %d\n", ret);
460 return ret;
461 }
462
463 ret = clk_prepare_enable(spi100k->fck);
464 if (ret != 0) {
465 dev_err(dev, "Failed to enable fck: %d\n", ret);
466 clk_disable_unprepare(spi100k->ick);
467 return ret;
468 }
469
470 return 0;
471 }
472 #endif
473
474 static const struct dev_pm_ops omap1_spi100k_pm = {
475 SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend,
476 omap1_spi100k_runtime_resume, NULL)
477 };
478
479 static struct platform_driver omap1_spi100k_driver = {
480 .driver = {
481 .name = "omap1_spi100k",
482 .pm = &omap1_spi100k_pm,
483 },
484 .probe = omap1_spi100k_probe,
485 .remove = omap1_spi100k_remove,
486 };
487
488 module_platform_driver(omap1_spi100k_driver);
489
490 MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
491 MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
492 MODULE_LICENSE("GPL");
Linux with added FPC-III support