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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / spi / spi-omap2-mcspi.c
blob7e2292c11d120b44d904c93c7433724a0ea7371e
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * OMAP2 McSPI controller driver
4 *
5 * Copyright (C) 2005, 2006 Nokia Corporation
6 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
7 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/gcd.h>
27 #include <linux/iopoll.h>
28
29 #include <linux/spi/spi.h>
30 #include <linux/gpio.h>
31
32 #include <linux/platform_data/spi-omap2-mcspi.h>
33
34 #define OMAP2_MCSPI_MAX_FREQ 48000000
35 #define OMAP2_MCSPI_MAX_DIVIDER 4096
36 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
37 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
38 #define SPI_AUTOSUSPEND_TIMEOUT 2000
39
40 #define OMAP2_MCSPI_REVISION 0x00
41 #define OMAP2_MCSPI_SYSSTATUS 0x14
42 #define OMAP2_MCSPI_IRQSTATUS 0x18
43 #define OMAP2_MCSPI_IRQENABLE 0x1c
44 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
45 #define OMAP2_MCSPI_SYST 0x24
46 #define OMAP2_MCSPI_MODULCTRL 0x28
47 #define OMAP2_MCSPI_XFERLEVEL 0x7c
48
49 /* per-channel banks, 0x14 bytes each, first is: */
50 #define OMAP2_MCSPI_CHCONF0 0x2c
51 #define OMAP2_MCSPI_CHSTAT0 0x30
52 #define OMAP2_MCSPI_CHCTRL0 0x34
53 #define OMAP2_MCSPI_TX0 0x38
54 #define OMAP2_MCSPI_RX0 0x3c
55
56 /* per-register bitmasks: */
57 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
58
59 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
60 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
61 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
62
63 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
64 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
65 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
66 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
67 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
68 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
69 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
70 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
71 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
72 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
73 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
74 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
75 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
76 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
77 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
78 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
79 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
80 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
81
82 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
83 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
84 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
85 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
86
87 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
88 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
89
90 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
91
92 /* We have 2 DMA channels per CS, one for RX and one for TX */
93 struct omap2_mcspi_dma {
94 struct dma_chan *dma_tx;
95 struct dma_chan *dma_rx;
96
97 struct completion dma_tx_completion;
98 struct completion dma_rx_completion;
99
100 char dma_rx_ch_name[14];
101 char dma_tx_ch_name[14];
102 };
103
104 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
105 * cache operations; better heuristics consider wordsize and bitrate.
106 */
107 #define DMA_MIN_BYTES 160
108
109
110 /*
111 * Used for context save and restore, structure members to be updated whenever
112 * corresponding registers are modified.
113 */
114 struct omap2_mcspi_regs {
115 u32 modulctrl;
116 u32 wakeupenable;
117 struct list_head cs;
118 };
119
120 struct omap2_mcspi {
121 struct completion txdone;
122 struct spi_master *master;
123 /* Virtual base address of the controller */
124 void __iomem *base;
125 unsigned long phys;
126 /* SPI1 has 4 channels, while SPI2 has 2 */
127 struct omap2_mcspi_dma *dma_channels;
128 struct device *dev;
129 struct omap2_mcspi_regs ctx;
130 int fifo_depth;
131 bool slave_aborted;
132 unsigned int pin_dir:1;
133 };
134
135 struct omap2_mcspi_cs {
136 void __iomem *base;
137 unsigned long phys;
138 int word_len;
139 u16 mode;
140 struct list_head node;
141 /* Context save and restore shadow register */
142 u32 chconf0, chctrl0;
143 };
144
145 static inline void mcspi_write_reg(struct spi_master *master,
146 int idx, u32 val)
147 {
148 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
149
150 writel_relaxed(val, mcspi->base + idx);
151 }
152
153 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
154 {
155 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
156
157 return readl_relaxed(mcspi->base + idx);
158 }
159
160 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
161 int idx, u32 val)
162 {
163 struct omap2_mcspi_cs *cs = spi->controller_state;
164
165 writel_relaxed(val, cs->base + idx);
166 }
167
168 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
169 {
170 struct omap2_mcspi_cs *cs = spi->controller_state;
171
172 return readl_relaxed(cs->base + idx);
173 }
174
175 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
176 {
177 struct omap2_mcspi_cs *cs = spi->controller_state;
178
179 return cs->chconf0;
180 }
181
182 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
183 {
184 struct omap2_mcspi_cs *cs = spi->controller_state;
185
186 cs->chconf0 = val;
187 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
188 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
189 }
190
191 static inline int mcspi_bytes_per_word(int word_len)
192 {
193 if (word_len <= 8)
194 return 1;
195 else if (word_len <= 16)
196 return 2;
197 else /* word_len <= 32 */
198 return 4;
199 }
200
201 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
202 int is_read, int enable)
203 {
204 u32 l, rw;
205
206 l = mcspi_cached_chconf0(spi);
207
208 if (is_read) /* 1 is read, 0 write */
209 rw = OMAP2_MCSPI_CHCONF_DMAR;
210 else
211 rw = OMAP2_MCSPI_CHCONF_DMAW;
212
213 if (enable)
214 l |= rw;
215 else
216 l &= ~rw;
217
218 mcspi_write_chconf0(spi, l);
219 }
220
221 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
222 {
223 struct omap2_mcspi_cs *cs = spi->controller_state;
224 u32 l;
225
226 l = cs->chctrl0;
227 if (enable)
228 l |= OMAP2_MCSPI_CHCTRL_EN;
229 else
230 l &= ~OMAP2_MCSPI_CHCTRL_EN;
231 cs->chctrl0 = l;
232 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
233 /* Flash post-writes */
234 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
235 }
236
237 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
238 {
239 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
240 u32 l;
241
242 /* The controller handles the inverted chip selects
243 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
244 * the inversion from the core spi_set_cs function.
245 */
246 if (spi->mode & SPI_CS_HIGH)
247 enable = !enable;
248
249 if (spi->controller_state) {
250 int err = pm_runtime_get_sync(mcspi->dev);
251 if (err < 0) {
252 pm_runtime_put_noidle(mcspi->dev);
253 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
254 return;
255 }
256
257 l = mcspi_cached_chconf0(spi);
258
259 if (enable)
260 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
261 else
262 l |= OMAP2_MCSPI_CHCONF_FORCE;
263
264 mcspi_write_chconf0(spi, l);
265
266 pm_runtime_mark_last_busy(mcspi->dev);
267 pm_runtime_put_autosuspend(mcspi->dev);
268 }
269 }
270
271 static void omap2_mcspi_set_mode(struct spi_master *master)
272 {
273 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
274 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
275 u32 l;
276
277 /*
278 * Choose master or slave mode
279 */
280 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
281 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
282 if (spi_controller_is_slave(master)) {
283 l |= (OMAP2_MCSPI_MODULCTRL_MS);
284 } else {
285 l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
286 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
287 }
288 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
289
290 ctx->modulctrl = l;
291 }
292
293 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
294 struct spi_transfer *t, int enable)
295 {
296 struct spi_master *master = spi->master;
297 struct omap2_mcspi_cs *cs = spi->controller_state;
298 struct omap2_mcspi *mcspi;
299 unsigned int wcnt;
300 int max_fifo_depth, bytes_per_word;
301 u32 chconf, xferlevel;
302
303 mcspi = spi_master_get_devdata(master);
304
305 chconf = mcspi_cached_chconf0(spi);
306 if (enable) {
307 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
308 if (t->len % bytes_per_word != 0)
309 goto disable_fifo;
310
311 if (t->rx_buf != NULL && t->tx_buf != NULL)
312 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
313 else
314 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
315
316 wcnt = t->len / bytes_per_word;
317 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
318 goto disable_fifo;
319
320 xferlevel = wcnt << 16;
321 if (t->rx_buf != NULL) {
322 chconf |= OMAP2_MCSPI_CHCONF_FFER;
323 xferlevel |= (bytes_per_word - 1) << 8;
324 }
325
326 if (t->tx_buf != NULL) {
327 chconf |= OMAP2_MCSPI_CHCONF_FFET;
328 xferlevel |= bytes_per_word - 1;
329 }
330
331 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
332 mcspi_write_chconf0(spi, chconf);
333 mcspi->fifo_depth = max_fifo_depth;
334
335 return;
336 }
337
338 disable_fifo:
339 if (t->rx_buf != NULL)
340 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
341
342 if (t->tx_buf != NULL)
343 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
344
345 mcspi_write_chconf0(spi, chconf);
346 mcspi->fifo_depth = 0;
347 }
348
349 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
350 {
351 u32 val;
352
353 return readl_poll_timeout(reg, val, val & bit, 1, MSEC_PER_SEC);
354 }
355
356 static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi,
357 struct completion *x)
358 {
359 if (spi_controller_is_slave(mcspi->master)) {
360 if (wait_for_completion_interruptible(x) ||
361 mcspi->slave_aborted)
362 return -EINTR;
363 } else {
364 wait_for_completion(x);
365 }
366
367 return 0;
368 }
369
370 static void omap2_mcspi_rx_callback(void *data)
371 {
372 struct spi_device *spi = data;
373 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
374 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
375
376 /* We must disable the DMA RX request */
377 omap2_mcspi_set_dma_req(spi, 1, 0);
378
379 complete(&mcspi_dma->dma_rx_completion);
380 }
381
382 static void omap2_mcspi_tx_callback(void *data)
383 {
384 struct spi_device *spi = data;
385 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
386 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
387
388 /* We must disable the DMA TX request */
389 omap2_mcspi_set_dma_req(spi, 0, 0);
390
391 complete(&mcspi_dma->dma_tx_completion);
392 }
393
394 static void omap2_mcspi_tx_dma(struct spi_device *spi,
395 struct spi_transfer *xfer,
396 struct dma_slave_config cfg)
397 {
398 struct omap2_mcspi *mcspi;
399 struct omap2_mcspi_dma *mcspi_dma;
400 struct dma_async_tx_descriptor *tx;
401
402 mcspi = spi_master_get_devdata(spi->master);
403 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
404
405 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
406
407 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
408 xfer->tx_sg.nents,
409 DMA_MEM_TO_DEV,
410 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
411 if (tx) {
412 tx->callback = omap2_mcspi_tx_callback;
413 tx->callback_param = spi;
414 dmaengine_submit(tx);
415 } else {
416 /* FIXME: fall back to PIO? */
417 }
418 dma_async_issue_pending(mcspi_dma->dma_tx);
419 omap2_mcspi_set_dma_req(spi, 0, 1);
420 }
421
422 static unsigned
423 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
424 struct dma_slave_config cfg,
425 unsigned es)
426 {
427 struct omap2_mcspi *mcspi;
428 struct omap2_mcspi_dma *mcspi_dma;
429 unsigned int count, transfer_reduction = 0;
430 struct scatterlist *sg_out[2];
431 int nb_sizes = 0, out_mapped_nents[2], ret, x;
432 size_t sizes[2];
433 u32 l;
434 int elements = 0;
435 int word_len, element_count;
436 struct omap2_mcspi_cs *cs = spi->controller_state;
437 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
438 struct dma_async_tx_descriptor *tx;
439
440 mcspi = spi_master_get_devdata(spi->master);
441 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
442 count = xfer->len;
443
444 /*
445 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
446 * it mentions reducing DMA transfer length by one element in master
447 * normal mode.
448 */
449 if (mcspi->fifo_depth == 0)
450 transfer_reduction = es;
451
452 word_len = cs->word_len;
453 l = mcspi_cached_chconf0(spi);
454
455 if (word_len <= 8)
456 element_count = count;
457 else if (word_len <= 16)
458 element_count = count >> 1;
459 else /* word_len <= 32 */
460 element_count = count >> 2;
461
462
463 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
464
465 /*
466 * Reduce DMA transfer length by one more if McSPI is
467 * configured in turbo mode.
468 */
469 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
470 transfer_reduction += es;
471
472 if (transfer_reduction) {
473 /* Split sgl into two. The second sgl won't be used. */
474 sizes[0] = count - transfer_reduction;
475 sizes[1] = transfer_reduction;
476 nb_sizes = 2;
477 } else {
478 /*
479 * Don't bother splitting the sgl. This essentially
480 * clones the original sgl.
481 */
482 sizes[0] = count;
483 nb_sizes = 1;
484 }
485
486 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes,
487 sizes, sg_out, out_mapped_nents, GFP_KERNEL);
488
489 if (ret < 0) {
490 dev_err(&spi->dev, "sg_split failed\n");
491 return 0;
492 }
493
494 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0],
495 out_mapped_nents[0], DMA_DEV_TO_MEM,
496 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
497 if (tx) {
498 tx->callback = omap2_mcspi_rx_callback;
499 tx->callback_param = spi;
500 dmaengine_submit(tx);
501 } else {
502 /* FIXME: fall back to PIO? */
503 }
504
505 dma_async_issue_pending(mcspi_dma->dma_rx);
506 omap2_mcspi_set_dma_req(spi, 1, 1);
507
508 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
509 if (ret || mcspi->slave_aborted) {
510 dmaengine_terminate_sync(mcspi_dma->dma_rx);
511 omap2_mcspi_set_dma_req(spi, 1, 0);
512 return 0;
513 }
514
515 for (x = 0; x < nb_sizes; x++)
516 kfree(sg_out[x]);
517
518 if (mcspi->fifo_depth > 0)
519 return count;
520
521 /*
522 * Due to the DMA transfer length reduction the missing bytes must
523 * be read manually to receive all of the expected data.
524 */
525 omap2_mcspi_set_enable(spi, 0);
526
527 elements = element_count - 1;
528
529 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
530 elements--;
531
532 if (!mcspi_wait_for_reg_bit(chstat_reg,
533 OMAP2_MCSPI_CHSTAT_RXS)) {
534 u32 w;
535
536 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
537 if (word_len <= 8)
538 ((u8 *)xfer->rx_buf)[elements++] = w;
539 else if (word_len <= 16)
540 ((u16 *)xfer->rx_buf)[elements++] = w;
541 else /* word_len <= 32 */
542 ((u32 *)xfer->rx_buf)[elements++] = w;
543 } else {
544 int bytes_per_word = mcspi_bytes_per_word(word_len);
545 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
546 count -= (bytes_per_word << 1);
547 omap2_mcspi_set_enable(spi, 1);
548 return count;
549 }
550 }
551 if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
552 u32 w;
553
554 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
555 if (word_len <= 8)
556 ((u8 *)xfer->rx_buf)[elements] = w;
557 else if (word_len <= 16)
558 ((u16 *)xfer->rx_buf)[elements] = w;
559 else /* word_len <= 32 */
560 ((u32 *)xfer->rx_buf)[elements] = w;
561 } else {
562 dev_err(&spi->dev, "DMA RX last word empty\n");
563 count -= mcspi_bytes_per_word(word_len);
564 }
565 omap2_mcspi_set_enable(spi, 1);
566 return count;
567 }
568
569 static unsigned
570 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
571 {
572 struct omap2_mcspi *mcspi;
573 struct omap2_mcspi_cs *cs = spi->controller_state;
574 struct omap2_mcspi_dma *mcspi_dma;
575 unsigned int count;
576 u8 *rx;
577 const u8 *tx;
578 struct dma_slave_config cfg;
579 enum dma_slave_buswidth width;
580 unsigned es;
581 void __iomem *chstat_reg;
582 void __iomem *irqstat_reg;
583 int wait_res;
584
585 mcspi = spi_master_get_devdata(spi->master);
586 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
587
588 if (cs->word_len <= 8) {
589 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
590 es = 1;
591 } else if (cs->word_len <= 16) {
592 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
593 es = 2;
594 } else {
595 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
596 es = 4;
597 }
598
599 count = xfer->len;
600
601 memset(&cfg, 0, sizeof(cfg));
602 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
603 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
604 cfg.src_addr_width = width;
605 cfg.dst_addr_width = width;
606 cfg.src_maxburst = 1;
607 cfg.dst_maxburst = 1;
608
609 rx = xfer->rx_buf;
610 tx = xfer->tx_buf;
611
612 mcspi->slave_aborted = false;
613 reinit_completion(&mcspi_dma->dma_tx_completion);
614 reinit_completion(&mcspi_dma->dma_rx_completion);
615 reinit_completion(&mcspi->txdone);
616 if (tx) {
617 /* Enable EOW IRQ to know end of tx in slave mode */
618 if (spi_controller_is_slave(spi->master))
619 mcspi_write_reg(spi->master,
620 OMAP2_MCSPI_IRQENABLE,
621 OMAP2_MCSPI_IRQSTATUS_EOW);
622 omap2_mcspi_tx_dma(spi, xfer, cfg);
623 }
624
625 if (rx != NULL)
626 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
627
628 if (tx != NULL) {
629 int ret;
630
631 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
632 if (ret || mcspi->slave_aborted) {
633 dmaengine_terminate_sync(mcspi_dma->dma_tx);
634 omap2_mcspi_set_dma_req(spi, 0, 0);
635 return 0;
636 }
637
638 if (spi_controller_is_slave(mcspi->master)) {
639 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
640 if (ret || mcspi->slave_aborted)
641 return 0;
642 }
643
644 if (mcspi->fifo_depth > 0) {
645 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
646
647 if (mcspi_wait_for_reg_bit(irqstat_reg,
648 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
649 dev_err(&spi->dev, "EOW timed out\n");
650
651 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
652 OMAP2_MCSPI_IRQSTATUS_EOW);
653 }
654
655 /* for TX_ONLY mode, be sure all words have shifted out */
656 if (rx == NULL) {
657 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
658 if (mcspi->fifo_depth > 0) {
659 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
660 OMAP2_MCSPI_CHSTAT_TXFFE);
661 if (wait_res < 0)
662 dev_err(&spi->dev, "TXFFE timed out\n");
663 } else {
664 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
665 OMAP2_MCSPI_CHSTAT_TXS);
666 if (wait_res < 0)
667 dev_err(&spi->dev, "TXS timed out\n");
668 }
669 if (wait_res >= 0 &&
670 (mcspi_wait_for_reg_bit(chstat_reg,
671 OMAP2_MCSPI_CHSTAT_EOT) < 0))
672 dev_err(&spi->dev, "EOT timed out\n");
673 }
674 }
675 return count;
676 }
677
678 static unsigned
679 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
680 {
681 struct omap2_mcspi_cs *cs = spi->controller_state;
682 unsigned int count, c;
683 u32 l;
684 void __iomem *base = cs->base;
685 void __iomem *tx_reg;
686 void __iomem *rx_reg;
687 void __iomem *chstat_reg;
688 int word_len;
689
690 count = xfer->len;
691 c = count;
692 word_len = cs->word_len;
693
694 l = mcspi_cached_chconf0(spi);
695
696 /* We store the pre-calculated register addresses on stack to speed
697 * up the transfer loop. */
698 tx_reg = base + OMAP2_MCSPI_TX0;
699 rx_reg = base + OMAP2_MCSPI_RX0;
700 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
701
702 if (c < (word_len>>3))
703 return 0;
704
705 if (word_len <= 8) {
706 u8 *rx;
707 const u8 *tx;
708
709 rx = xfer->rx_buf;
710 tx = xfer->tx_buf;
711
712 do {
713 c -= 1;
714 if (tx != NULL) {
715 if (mcspi_wait_for_reg_bit(chstat_reg,
716 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
717 dev_err(&spi->dev, "TXS timed out\n");
718 goto out;
719 }
720 dev_vdbg(&spi->dev, "write-%d %02x\n",
721 word_len, *tx);
722 writel_relaxed(*tx++, tx_reg);
723 }
724 if (rx != NULL) {
725 if (mcspi_wait_for_reg_bit(chstat_reg,
726 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
727 dev_err(&spi->dev, "RXS timed out\n");
728 goto out;
729 }
730
731 if (c == 1 && tx == NULL &&
732 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
733 omap2_mcspi_set_enable(spi, 0);
734 *rx++ = readl_relaxed(rx_reg);
735 dev_vdbg(&spi->dev, "read-%d %02x\n",
736 word_len, *(rx - 1));
737 if (mcspi_wait_for_reg_bit(chstat_reg,
738 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
739 dev_err(&spi->dev,
740 "RXS timed out\n");
741 goto out;
742 }
743 c = 0;
744 } else if (c == 0 && tx == NULL) {
745 omap2_mcspi_set_enable(spi, 0);
746 }
747
748 *rx++ = readl_relaxed(rx_reg);
749 dev_vdbg(&spi->dev, "read-%d %02x\n",
750 word_len, *(rx - 1));
751 }
752 } while (c);
753 } else if (word_len <= 16) {
754 u16 *rx;
755 const u16 *tx;
756
757 rx = xfer->rx_buf;
758 tx = xfer->tx_buf;
759 do {
760 c -= 2;
761 if (tx != NULL) {
762 if (mcspi_wait_for_reg_bit(chstat_reg,
763 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
764 dev_err(&spi->dev, "TXS timed out\n");
765 goto out;
766 }
767 dev_vdbg(&spi->dev, "write-%d %04x\n",
768 word_len, *tx);
769 writel_relaxed(*tx++, tx_reg);
770 }
771 if (rx != NULL) {
772 if (mcspi_wait_for_reg_bit(chstat_reg,
773 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
774 dev_err(&spi->dev, "RXS timed out\n");
775 goto out;
776 }
777
778 if (c == 2 && tx == NULL &&
779 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
780 omap2_mcspi_set_enable(spi, 0);
781 *rx++ = readl_relaxed(rx_reg);
782 dev_vdbg(&spi->dev, "read-%d %04x\n",
783 word_len, *(rx - 1));
784 if (mcspi_wait_for_reg_bit(chstat_reg,
785 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
786 dev_err(&spi->dev,
787 "RXS timed out\n");
788 goto out;
789 }
790 c = 0;
791 } else if (c == 0 && tx == NULL) {
792 omap2_mcspi_set_enable(spi, 0);
793 }
794
795 *rx++ = readl_relaxed(rx_reg);
796 dev_vdbg(&spi->dev, "read-%d %04x\n",
797 word_len, *(rx - 1));
798 }
799 } while (c >= 2);
800 } else if (word_len <= 32) {
801 u32 *rx;
802 const u32 *tx;
803
804 rx = xfer->rx_buf;
805 tx = xfer->tx_buf;
806 do {
807 c -= 4;
808 if (tx != NULL) {
809 if (mcspi_wait_for_reg_bit(chstat_reg,
810 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
811 dev_err(&spi->dev, "TXS timed out\n");
812 goto out;
813 }
814 dev_vdbg(&spi->dev, "write-%d %08x\n",
815 word_len, *tx);
816 writel_relaxed(*tx++, tx_reg);
817 }
818 if (rx != NULL) {
819 if (mcspi_wait_for_reg_bit(chstat_reg,
820 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
821 dev_err(&spi->dev, "RXS timed out\n");
822 goto out;
823 }
824
825 if (c == 4 && tx == NULL &&
826 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
827 omap2_mcspi_set_enable(spi, 0);
828 *rx++ = readl_relaxed(rx_reg);
829 dev_vdbg(&spi->dev, "read-%d %08x\n",
830 word_len, *(rx - 1));
831 if (mcspi_wait_for_reg_bit(chstat_reg,
832 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
833 dev_err(&spi->dev,
834 "RXS timed out\n");
835 goto out;
836 }
837 c = 0;
838 } else if (c == 0 && tx == NULL) {
839 omap2_mcspi_set_enable(spi, 0);
840 }
841
842 *rx++ = readl_relaxed(rx_reg);
843 dev_vdbg(&spi->dev, "read-%d %08x\n",
844 word_len, *(rx - 1));
845 }
846 } while (c >= 4);
847 }
848
849 /* for TX_ONLY mode, be sure all words have shifted out */
850 if (xfer->rx_buf == NULL) {
851 if (mcspi_wait_for_reg_bit(chstat_reg,
852 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
853 dev_err(&spi->dev, "TXS timed out\n");
854 } else if (mcspi_wait_for_reg_bit(chstat_reg,
855 OMAP2_MCSPI_CHSTAT_EOT) < 0)
856 dev_err(&spi->dev, "EOT timed out\n");
857
858 /* disable chan to purge rx datas received in TX_ONLY transfer,
859 * otherwise these rx datas will affect the direct following
860 * RX_ONLY transfer.
861 */
862 omap2_mcspi_set_enable(spi, 0);
863 }
864 out:
865 omap2_mcspi_set_enable(spi, 1);
866 return count - c;
867 }
868
869 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
870 {
871 u32 div;
872
873 for (div = 0; div < 15; div++)
874 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
875 return div;
876
877 return 15;
878 }
879
880 /* called only when no transfer is active to this device */
881 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
882 struct spi_transfer *t)
883 {
884 struct omap2_mcspi_cs *cs = spi->controller_state;
885 struct omap2_mcspi *mcspi;
886 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
887 u8 word_len = spi->bits_per_word;
888 u32 speed_hz = spi->max_speed_hz;
889
890 mcspi = spi_master_get_devdata(spi->master);
891
892 if (t != NULL && t->bits_per_word)
893 word_len = t->bits_per_word;
894
895 cs->word_len = word_len;
896
897 if (t && t->speed_hz)
898 speed_hz = t->speed_hz;
899
900 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
901 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
902 clkd = omap2_mcspi_calc_divisor(speed_hz);
903 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
904 clkg = 0;
905 } else {
906 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
907 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
908 clkd = (div - 1) & 0xf;
909 extclk = (div - 1) >> 4;
910 clkg = OMAP2_MCSPI_CHCONF_CLKG;
911 }
912
913 l = mcspi_cached_chconf0(spi);
914
915 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
916 * REVISIT: this controller could support SPI_3WIRE mode.
917 */
918 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
919 l &= ~OMAP2_MCSPI_CHCONF_IS;
920 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
921 l |= OMAP2_MCSPI_CHCONF_DPE0;
922 } else {
923 l |= OMAP2_MCSPI_CHCONF_IS;
924 l |= OMAP2_MCSPI_CHCONF_DPE1;
925 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
926 }
927
928 /* wordlength */
929 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
930 l |= (word_len - 1) << 7;
931
932 /* set chipselect polarity; manage with FORCE */
933 if (!(spi->mode & SPI_CS_HIGH))
934 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
935 else
936 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
937
938 /* set clock divisor */
939 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
940 l |= clkd << 2;
941
942 /* set clock granularity */
943 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
944 l |= clkg;
945 if (clkg) {
946 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
947 cs->chctrl0 |= extclk << 8;
948 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
949 }
950
951 /* set SPI mode 0..3 */
952 if (spi->mode & SPI_CPOL)
953 l |= OMAP2_MCSPI_CHCONF_POL;
954 else
955 l &= ~OMAP2_MCSPI_CHCONF_POL;
956 if (spi->mode & SPI_CPHA)
957 l |= OMAP2_MCSPI_CHCONF_PHA;
958 else
959 l &= ~OMAP2_MCSPI_CHCONF_PHA;
960
961 mcspi_write_chconf0(spi, l);
962
963 cs->mode = spi->mode;
964
965 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
966 speed_hz,
967 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
968 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
969
970 return 0;
971 }
972
973 /*
974 * Note that we currently allow DMA only if we get a channel
975 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
976 */
977 static int omap2_mcspi_request_dma(struct spi_device *spi)
978 {
979 struct spi_master *master = spi->master;
980 struct omap2_mcspi *mcspi;
981 struct omap2_mcspi_dma *mcspi_dma;
982 int ret = 0;
983
984 mcspi = spi_master_get_devdata(master);
985 mcspi_dma = mcspi->dma_channels + spi->chip_select;
986
987 init_completion(&mcspi_dma->dma_rx_completion);
988 init_completion(&mcspi_dma->dma_tx_completion);
989
990 mcspi_dma->dma_rx = dma_request_chan(&master->dev,
991 mcspi_dma->dma_rx_ch_name);
992 if (IS_ERR(mcspi_dma->dma_rx)) {
993 ret = PTR_ERR(mcspi_dma->dma_rx);
994 mcspi_dma->dma_rx = NULL;
995 goto no_dma;
996 }
997
998 mcspi_dma->dma_tx = dma_request_chan(&master->dev,
999 mcspi_dma->dma_tx_ch_name);
1000 if (IS_ERR(mcspi_dma->dma_tx)) {
1001 ret = PTR_ERR(mcspi_dma->dma_tx);
1002 mcspi_dma->dma_tx = NULL;
1003 dma_release_channel(mcspi_dma->dma_rx);
1004 mcspi_dma->dma_rx = NULL;
1005 }
1006
1007 no_dma:
1008 return ret;
1009 }
1010
1011 static int omap2_mcspi_setup(struct spi_device *spi)
1012 {
1013 int ret;
1014 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1015 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1016 struct omap2_mcspi_dma *mcspi_dma;
1017 struct omap2_mcspi_cs *cs = spi->controller_state;
1018
1019 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1020
1021 if (!cs) {
1022 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1023 if (!cs)
1024 return -ENOMEM;
1025 cs->base = mcspi->base + spi->chip_select * 0x14;
1026 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1027 cs->mode = 0;
1028 cs->chconf0 = 0;
1029 cs->chctrl0 = 0;
1030 spi->controller_state = cs;
1031 /* Link this to context save list */
1032 list_add_tail(&cs->node, &ctx->cs);
1033
1034 if (gpio_is_valid(spi->cs_gpio)) {
1035 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1036 if (ret) {
1037 dev_err(&spi->dev, "failed to request gpio\n");
1038 return ret;
1039 }
1040 gpio_direction_output(spi->cs_gpio,
1041 !(spi->mode & SPI_CS_HIGH));
1042 }
1043 }
1044
1045 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1046 ret = omap2_mcspi_request_dma(spi);
1047 if (ret)
1048 dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1049 ret);
1050 }
1051
1052 ret = pm_runtime_get_sync(mcspi->dev);
1053 if (ret < 0) {
1054 pm_runtime_put_noidle(mcspi->dev);
1055
1056 return ret;
1057 }
1058
1059 ret = omap2_mcspi_setup_transfer(spi, NULL);
1060 pm_runtime_mark_last_busy(mcspi->dev);
1061 pm_runtime_put_autosuspend(mcspi->dev);
1062
1063 return ret;
1064 }
1065
1066 static void omap2_mcspi_cleanup(struct spi_device *spi)
1067 {
1068 struct omap2_mcspi *mcspi;
1069 struct omap2_mcspi_dma *mcspi_dma;
1070 struct omap2_mcspi_cs *cs;
1071
1072 mcspi = spi_master_get_devdata(spi->master);
1073
1074 if (spi->controller_state) {
1075 /* Unlink controller state from context save list */
1076 cs = spi->controller_state;
1077 list_del(&cs->node);
1078
1079 kfree(cs);
1080 }
1081
1082 if (spi->chip_select < spi->master->num_chipselect) {
1083 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1084
1085 if (mcspi_dma->dma_rx) {
1086 dma_release_channel(mcspi_dma->dma_rx);
1087 mcspi_dma->dma_rx = NULL;
1088 }
1089 if (mcspi_dma->dma_tx) {
1090 dma_release_channel(mcspi_dma->dma_tx);
1091 mcspi_dma->dma_tx = NULL;
1092 }
1093 }
1094
1095 if (gpio_is_valid(spi->cs_gpio))
1096 gpio_free(spi->cs_gpio);
1097 }
1098
1099 static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
1100 {
1101 struct omap2_mcspi *mcspi = data;
1102 u32 irqstat;
1103
1104 irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
1105 if (!irqstat)
1106 return IRQ_NONE;
1107
1108 /* Disable IRQ and wakeup slave xfer task */
1109 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0);
1110 if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
1111 complete(&mcspi->txdone);
1112
1113 return IRQ_HANDLED;
1114 }
1115
1116 static int omap2_mcspi_slave_abort(struct spi_master *master)
1117 {
1118 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1119 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
1120
1121 mcspi->slave_aborted = true;
1122 complete(&mcspi_dma->dma_rx_completion);
1123 complete(&mcspi_dma->dma_tx_completion);
1124 complete(&mcspi->txdone);
1125
1126 return 0;
1127 }
1128
1129 static int omap2_mcspi_transfer_one(struct spi_master *master,
1130 struct spi_device *spi,
1131 struct spi_transfer *t)
1132 {
1133
1134 /* We only enable one channel at a time -- the one whose message is
1135 * -- although this controller would gladly
1136 * arbitrate among multiple channels. This corresponds to "single
1137 * channel" master mode. As a side effect, we need to manage the
1138 * chipselect with the FORCE bit ... CS != channel enable.
1139 */
1140
1141 struct omap2_mcspi *mcspi;
1142 struct omap2_mcspi_dma *mcspi_dma;
1143 struct omap2_mcspi_cs *cs;
1144 struct omap2_mcspi_device_config *cd;
1145 int par_override = 0;
1146 int status = 0;
1147 u32 chconf;
1148
1149 mcspi = spi_master_get_devdata(master);
1150 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1151 cs = spi->controller_state;
1152 cd = spi->controller_data;
1153
1154 /*
1155 * The slave driver could have changed spi->mode in which case
1156 * it will be different from cs->mode (the current hardware setup).
1157 * If so, set par_override (even though its not a parity issue) so
1158 * omap2_mcspi_setup_transfer will be called to configure the hardware
1159 * with the correct mode on the first iteration of the loop below.
1160 */
1161 if (spi->mode != cs->mode)
1162 par_override = 1;
1163
1164 omap2_mcspi_set_enable(spi, 0);
1165
1166 if (gpio_is_valid(spi->cs_gpio))
1167 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1168
1169 if (par_override ||
1170 (t->speed_hz != spi->max_speed_hz) ||
1171 (t->bits_per_word != spi->bits_per_word)) {
1172 par_override = 1;
1173 status = omap2_mcspi_setup_transfer(spi, t);
1174 if (status < 0)
1175 goto out;
1176 if (t->speed_hz == spi->max_speed_hz &&
1177 t->bits_per_word == spi->bits_per_word)
1178 par_override = 0;
1179 }
1180 if (cd && cd->cs_per_word) {
1181 chconf = mcspi->ctx.modulctrl;
1182 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1183 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1184 mcspi->ctx.modulctrl =
1185 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1186 }
1187
1188 chconf = mcspi_cached_chconf0(spi);
1189 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1190 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1191
1192 if (t->tx_buf == NULL)
1193 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1194 else if (t->rx_buf == NULL)
1195 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1196
1197 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1198 /* Turbo mode is for more than one word */
1199 if (t->len > ((cs->word_len + 7) >> 3))
1200 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1201 }
1202
1203 mcspi_write_chconf0(spi, chconf);
1204
1205 if (t->len) {
1206 unsigned count;
1207
1208 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1209 master->cur_msg_mapped &&
1210 master->can_dma(master, spi, t))
1211 omap2_mcspi_set_fifo(spi, t, 1);
1212
1213 omap2_mcspi_set_enable(spi, 1);
1214
1215 /* RX_ONLY mode needs dummy data in TX reg */
1216 if (t->tx_buf == NULL)
1217 writel_relaxed(0, cs->base
1218 + OMAP2_MCSPI_TX0);
1219
1220 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1221 master->cur_msg_mapped &&
1222 master->can_dma(master, spi, t))
1223 count = omap2_mcspi_txrx_dma(spi, t);
1224 else
1225 count = omap2_mcspi_txrx_pio(spi, t);
1226
1227 if (count != t->len) {
1228 status = -EIO;
1229 goto out;
1230 }
1231 }
1232
1233 omap2_mcspi_set_enable(spi, 0);
1234
1235 if (mcspi->fifo_depth > 0)
1236 omap2_mcspi_set_fifo(spi, t, 0);
1237
1238 out:
1239 /* Restore defaults if they were overriden */
1240 if (par_override) {
1241 par_override = 0;
1242 status = omap2_mcspi_setup_transfer(spi, NULL);
1243 }
1244
1245 if (cd && cd->cs_per_word) {
1246 chconf = mcspi->ctx.modulctrl;
1247 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1248 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1249 mcspi->ctx.modulctrl =
1250 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1251 }
1252
1253 omap2_mcspi_set_enable(spi, 0);
1254
1255 if (gpio_is_valid(spi->cs_gpio))
1256 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1257
1258 if (mcspi->fifo_depth > 0 && t)
1259 omap2_mcspi_set_fifo(spi, t, 0);
1260
1261 return status;
1262 }
1263
1264 static int omap2_mcspi_prepare_message(struct spi_master *master,
1265 struct spi_message *msg)
1266 {
1267 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1268 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1269 struct omap2_mcspi_cs *cs;
1270
1271 /* Only a single channel can have the FORCE bit enabled
1272 * in its chconf0 register.
1273 * Scan all channels and disable them except the current one.
1274 * A FORCE can remain from a last transfer having cs_change enabled
1275 */
1276 list_for_each_entry(cs, &ctx->cs, node) {
1277 if (msg->spi->controller_state == cs)
1278 continue;
1279
1280 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1281 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1282 writel_relaxed(cs->chconf0,
1283 cs->base + OMAP2_MCSPI_CHCONF0);
1284 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1285 }
1286 }
1287
1288 return 0;
1289 }
1290
1291 static bool omap2_mcspi_can_dma(struct spi_master *master,
1292 struct spi_device *spi,
1293 struct spi_transfer *xfer)
1294 {
1295 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1296 struct omap2_mcspi_dma *mcspi_dma =
1297 &mcspi->dma_channels[spi->chip_select];
1298
1299 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
1300 return false;
1301
1302 if (spi_controller_is_slave(master))
1303 return true;
1304
1305 return (xfer->len >= DMA_MIN_BYTES);
1306 }
1307
1308 static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
1309 {
1310 struct spi_master *master = mcspi->master;
1311 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1312 int ret = 0;
1313
1314 ret = pm_runtime_get_sync(mcspi->dev);
1315 if (ret < 0) {
1316 pm_runtime_put_noidle(mcspi->dev);
1317
1318 return ret;
1319 }
1320
1321 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1322 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1323 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1324
1325 omap2_mcspi_set_mode(master);
1326 pm_runtime_mark_last_busy(mcspi->dev);
1327 pm_runtime_put_autosuspend(mcspi->dev);
1328 return 0;
1329 }
1330
1331 /*
1332 * When SPI wake up from off-mode, CS is in activate state. If it was in
1333 * inactive state when driver was suspend, then force it to inactive state at
1334 * wake up.
1335 */
1336 static int omap_mcspi_runtime_resume(struct device *dev)
1337 {
1338 struct spi_master *master = dev_get_drvdata(dev);
1339 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1340 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1341 struct omap2_mcspi_cs *cs;
1342
1343 /* McSPI: context restore */
1344 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
1345 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
1346
1347 list_for_each_entry(cs, &ctx->cs, node) {
1348 /*
1349 * We need to toggle CS state for OMAP take this
1350 * change in account.
1351 */
1352 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1353 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1354 writel_relaxed(cs->chconf0,
1355 cs->base + OMAP2_MCSPI_CHCONF0);
1356 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1357 writel_relaxed(cs->chconf0,
1358 cs->base + OMAP2_MCSPI_CHCONF0);
1359 } else {
1360 writel_relaxed(cs->chconf0,
1361 cs->base + OMAP2_MCSPI_CHCONF0);
1362 }
1363 }
1364
1365 return 0;
1366 }
1367
1368 static struct omap2_mcspi_platform_config omap2_pdata = {
1369 .regs_offset = 0,
1370 };
1371
1372 static struct omap2_mcspi_platform_config omap4_pdata = {
1373 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1374 };
1375
1376 static const struct of_device_id omap_mcspi_of_match[] = {
1377 {
1378 .compatible = "ti,omap2-mcspi",
1379 .data = &omap2_pdata,
1380 },
1381 {
1382 .compatible = "ti,omap4-mcspi",
1383 .data = &omap4_pdata,
1384 },
1385 { },
1386 };
1387 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1388
1389 static int omap2_mcspi_probe(struct platform_device *pdev)
1390 {
1391 struct spi_master *master;
1392 const struct omap2_mcspi_platform_config *pdata;
1393 struct omap2_mcspi *mcspi;
1394 struct resource *r;
1395 int status = 0, i;
1396 u32 regs_offset = 0;
1397 struct device_node *node = pdev->dev.of_node;
1398 const struct of_device_id *match;
1399
1400 if (of_property_read_bool(node, "spi-slave"))
1401 master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi));
1402 else
1403 master = spi_alloc_master(&pdev->dev, sizeof(*mcspi));
1404 if (!master)
1405 return -ENOMEM;
1406
1407 /* the spi->mode bits understood by this driver: */
1408 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1409 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1410 master->setup = omap2_mcspi_setup;
1411 master->auto_runtime_pm = true;
1412 master->prepare_message = omap2_mcspi_prepare_message;
1413 master->can_dma = omap2_mcspi_can_dma;
1414 master->transfer_one = omap2_mcspi_transfer_one;
1415 master->set_cs = omap2_mcspi_set_cs;
1416 master->cleanup = omap2_mcspi_cleanup;
1417 master->slave_abort = omap2_mcspi_slave_abort;
1418 master->dev.of_node = node;
1419 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1420 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1421
1422 platform_set_drvdata(pdev, master);
1423
1424 mcspi = spi_master_get_devdata(master);
1425 mcspi->master = master;
1426
1427 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1428 if (match) {
1429 u32 num_cs = 1; /* default number of chipselect */
1430 pdata = match->data;
1431
1432 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1433 master->num_chipselect = num_cs;
1434 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1435 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1436 } else {
1437 pdata = dev_get_platdata(&pdev->dev);
1438 master->num_chipselect = pdata->num_cs;
1439 mcspi->pin_dir = pdata->pin_dir;
1440 }
1441 regs_offset = pdata->regs_offset;
1442
1443 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1444 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1445 if (IS_ERR(mcspi->base)) {
1446 status = PTR_ERR(mcspi->base);
1447 goto free_master;
1448 }
1449 mcspi->phys = r->start + regs_offset;
1450 mcspi->base += regs_offset;
1451
1452 mcspi->dev = &pdev->dev;
1453
1454 INIT_LIST_HEAD(&mcspi->ctx.cs);
1455
1456 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1457 sizeof(struct omap2_mcspi_dma),
1458 GFP_KERNEL);
1459 if (mcspi->dma_channels == NULL) {
1460 status = -ENOMEM;
1461 goto free_master;
1462 }
1463
1464 for (i = 0; i < master->num_chipselect; i++) {
1465 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1466 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1467 }
1468
1469 status = platform_get_irq(pdev, 0);
1470 if (status == -EPROBE_DEFER)
1471 goto free_master;
1472 if (status < 0) {
1473 dev_err(&pdev->dev, "no irq resource found\n");
1474 goto free_master;
1475 }
1476 init_completion(&mcspi->txdone);
1477 status = devm_request_irq(&pdev->dev, status,
1478 omap2_mcspi_irq_handler, 0, pdev->name,
1479 mcspi);
1480 if (status) {
1481 dev_err(&pdev->dev, "Cannot request IRQ");
1482 goto free_master;
1483 }
1484
1485 pm_runtime_use_autosuspend(&pdev->dev);
1486 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1487 pm_runtime_enable(&pdev->dev);
1488
1489 status = omap2_mcspi_controller_setup(mcspi);
1490 if (status < 0)
1491 goto disable_pm;
1492
1493 status = devm_spi_register_controller(&pdev->dev, master);
1494 if (status < 0)
1495 goto disable_pm;
1496
1497 return status;
1498
1499 disable_pm:
1500 pm_runtime_dont_use_autosuspend(&pdev->dev);
1501 pm_runtime_put_sync(&pdev->dev);
1502 pm_runtime_disable(&pdev->dev);
1503 free_master:
1504 spi_master_put(master);
1505 return status;
1506 }
1507
1508 static int omap2_mcspi_remove(struct platform_device *pdev)
1509 {
1510 struct spi_master *master = platform_get_drvdata(pdev);
1511 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1512
1513 pm_runtime_dont_use_autosuspend(mcspi->dev);
1514 pm_runtime_put_sync(mcspi->dev);
1515 pm_runtime_disable(&pdev->dev);
1516
1517 return 0;
1518 }
1519
1520 /* work with hotplug and coldplug */
1521 MODULE_ALIAS("platform:omap2_mcspi");
1522
1523 static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
1524 {
1525 struct spi_master *master = dev_get_drvdata(dev);
1526 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1527 int error;
1528
1529 error = pinctrl_pm_select_sleep_state(dev);
1530 if (error)
1531 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1532 __func__, error);
1533
1534 error = spi_master_suspend(master);
1535 if (error)
1536 dev_warn(mcspi->dev, "%s: master suspend failed: %i\n",
1537 __func__, error);
1538
1539 return pm_runtime_force_suspend(dev);
1540 }
1541
1542 static int __maybe_unused omap2_mcspi_resume(struct device *dev)
1543 {
1544 struct spi_master *master = dev_get_drvdata(dev);
1545 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1546 int error;
1547
1548 error = pinctrl_pm_select_default_state(dev);
1549 if (error)
1550 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1551 __func__, error);
1552
1553 error = spi_master_resume(master);
1554 if (error)
1555 dev_warn(mcspi->dev, "%s: master resume failed: %i\n",
1556 __func__, error);
1557
1558 return pm_runtime_force_resume(dev);
1559 }
1560
1561 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1562 SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
1563 omap2_mcspi_resume)
1564 .runtime_resume = omap_mcspi_runtime_resume,
1565 };
1566
1567 static struct platform_driver omap2_mcspi_driver = {
1568 .driver = {
1569 .name = "omap2_mcspi",
1570 .pm = &omap2_mcspi_pm_ops,
1571 .of_match_table = omap_mcspi_of_match,
1572 },
1573 .probe = omap2_mcspi_probe,
1574 .remove = omap2_mcspi_remove,
1575 };
1576
1577 module_platform_driver(omap2_mcspi_driver);
1578 MODULE_LICENSE("GPL");
Linux with added FPC-III support