drivers/staging/rtl8192u/r8192U.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * This is part of rtl8187 OpenSource driver.
   4  * Copyright (C) Andrea Merello 2004-2005  <andrea.merello@gmail.com>
   5  * Released under the terms of GPL (General Public Licence)
   6  *
   7  * Parts of this driver are based on the GPL part of the
   8  * official realtek driver
   9  *
  10  * Parts of this driver are based on the rtl8192 driver skeleton
  11  * from Patric Schenke & Andres Salomon
  12  *
  13  * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  14  *
  15  * We want to thank the Authors of those projects and the Ndiswrapper
  16  * project Authors.
  17  */
  18
  19 #ifndef R8192U_H
  20 #define R8192U_H
  21
  22 #include <linux/compiler.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/ioport.h>
  26 #include <linux/sched.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/usb.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/delay.h>
  33 #include <linux/rtnetlink.h>
  34 #include <linux/wireless.h>
  35 #include <linux/timer.h>
  36 #include <linux/proc_fs.h>
  37 #include <linux/if_arp.h>
  38 #include <linux/random.h>
  39 #include <linux/io.h>
  40 #include "ieee80211/ieee80211.h"
  41
  42 #define RTL8192U
  43 #define RTL819XU_MODULE_NAME "rtl819xU"
  44 /* HW security */
  45 #define MAX_KEY_LEN     61
  46 #define KEY_BUF_SIZE    5
  47
  48 #define RX_SMOOTH_FACTOR                20
  49 #define DMESG(x, a...)
  50 #define DMESGW(x, a...)
  51 #define DMESGE(x, a...)
  52 extern u32 rt_global_debug_component;
  53 #define RT_TRACE(component, x, args...) \
  54         do {                                                    \
  55                 if (rt_global_debug_component & (component))    \
  56                         pr_debug("RTL8192U: " x "\n", ##args);  \
  57         } while (0)
  58
  59 #define COMP_TRACE              BIT(0)  /* Function call tracing. */
  60 #define COMP_DBG                BIT(1)
  61 #define COMP_INIT               BIT(2)  /* Driver initialization/halt/reset. */
  62
  63 #define COMP_RECV               BIT(3)  /* Receive data path. */
  64 #define COMP_SEND               BIT(4)  /* Send data path. */
  65 #define COMP_IO                 BIT(5)
  66 /* 802.11 Power Save mode or System/Device Power state. */
  67 #define COMP_POWER              BIT(6)
  68 /* 802.11 link related: join/start BSS, leave BSS. */
  69 #define COMP_EPROM              BIT(7)
  70 #define COMP_SWBW               BIT(8)  /* Bandwidth switch. */
  71 #define COMP_POWER_TRACKING     BIT(9)  /* 8190 TX Power Tracking */
  72 #define COMP_TURBO              BIT(10) /* Turbo Mode */
  73 #define COMP_QOS                BIT(11)
  74 #define COMP_RATE               BIT(12) /* Rate Adaptive mechanism */
  75 #define COMP_RM                 BIT(13) /* Radio Measurement */
  76 #define COMP_DIG                BIT(14)
  77 #define COMP_PHY                BIT(15)
  78 #define COMP_CH                 BIT(16) /* Channel setting debug */
  79 #define COMP_TXAGC              BIT(17) /* Tx power */
  80 #define COMP_HIPWR              BIT(18) /* High Power Mechanism */
  81 #define COMP_HALDM              BIT(19) /* HW Dynamic Mechanism */
  82 #define COMP_SEC                BIT(20) /* Event handling */
  83 #define COMP_LED                BIT(21)
  84 #define COMP_RF                 BIT(22)
  85 #define COMP_RXDESC             BIT(23) /* Rx desc information for SD3 debug */
  86
  87 /* 11n or 8190 specific code */
  88
  89 #define COMP_FIRMWARE           BIT(24) /* Firmware downloading */
  90 #define COMP_HT                 BIT(25) /* 802.11n HT related information */
  91 #define COMP_AMSDU              BIT(26) /* A-MSDU Debugging */
  92 #define COMP_SCAN               BIT(27)
  93 #define COMP_DOWN               BIT(29) /* rm driver module */
  94 #define COMP_RESET              BIT(30) /* Silent reset */
  95 #define COMP_ERR                BIT(31) /* Error out, always on */
  96
  97 #define RTL819x_DEBUG
  98 #ifdef RTL819x_DEBUG
  99 #define RTL8192U_ASSERT(expr) \
 100         do {                                                            \
 101                 if (!(expr)) {                                          \
 102                         pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \
 103                                  #expr, __FILE__, __func__, __LINE__);  \
 104                 }                                                       \
 105         } while (0)
 106 /*
 107  * Debug out data buf.
 108  * If you want to print DATA buffer related BA,
 109  * please set ieee80211_debug_level to DATA|BA
 110  */
 111 #define RT_DEBUG_DATA(level, data, datalen) \
 112         do {                                                            \
 113                 if ((rt_global_debug_component & (level)) == (level)) { \
 114                         int i;                                          \
 115                         u8 *pdata = (u8 *)data;                         \
 116                         pr_debug("RTL8192U: %s()\n", __func__);         \
 117                         for (i = 0; i < (int)(datalen); i++) {          \
 118                                 printk("%2x ", pdata[i]);               \
 119                                 if ((i+1)%16 == 0)                      \
 120                                         printk("\n");                   \
 121                         }                                               \
 122                         printk("\n");                                   \
 123                 }                                                       \
 124         } while (0)
 125 #else
 126 #define RTL8192U_ASSERT(expr) do {} while (0)
 127 #define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
 128 #endif /* RTL8169_DEBUG */
 129
 130 /* Queue Select Value in TxDesc */
 131 #define QSLT_BK                                 0x1
 132 #define QSLT_BE                                 0x0
 133 #define QSLT_VI                                 0x4
 134 #define QSLT_VO                                 0x6
 135 #define QSLT_BEACON                             0x10
 136 #define QSLT_HIGH                               0x11
 137 #define QSLT_MGNT                               0x12
 138 #define QSLT_CMD                                0x13
 139
 140 #define DESC90_RATE1M                           0x00
 141 #define DESC90_RATE2M                           0x01
 142 #define DESC90_RATE5_5M                         0x02
 143 #define DESC90_RATE11M                          0x03
 144 #define DESC90_RATE6M                           0x04
 145 #define DESC90_RATE9M                           0x05
 146 #define DESC90_RATE12M                          0x06
 147 #define DESC90_RATE18M                          0x07
 148 #define DESC90_RATE24M                          0x08
 149 #define DESC90_RATE36M                          0x09
 150 #define DESC90_RATE48M                          0x0a
 151 #define DESC90_RATE54M                          0x0b
 152 #define DESC90_RATEMCS0                         0x00
 153 #define DESC90_RATEMCS1                         0x01
 154 #define DESC90_RATEMCS2                         0x02
 155 #define DESC90_RATEMCS3                         0x03
 156 #define DESC90_RATEMCS4                         0x04
 157 #define DESC90_RATEMCS5                         0x05
 158 #define DESC90_RATEMCS6                         0x06
 159 #define DESC90_RATEMCS7                         0x07
 160 #define DESC90_RATEMCS8                         0x08
 161 #define DESC90_RATEMCS9                         0x09
 162 #define DESC90_RATEMCS10                        0x0a
 163 #define DESC90_RATEMCS11                        0x0b
 164 #define DESC90_RATEMCS12                        0x0c
 165 #define DESC90_RATEMCS13                        0x0d
 166 #define DESC90_RATEMCS14                        0x0e
 167 #define DESC90_RATEMCS15                        0x0f
 168 #define DESC90_RATEMCS32                        0x20
 169
 170 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 171
 172 #define IEEE80211_WATCH_DOG_TIME    2000
 173 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 174 /* For Tx Power Tracking */
 175 #define         OFDM_Table_Length       19
 176 #define CCK_Table_length        12
 177
 178 /* For rtl819x */
 179 struct tx_desc_819x_usb {
 180         /* DWORD 0 */
 181         u16     PktSize;
 182         u8      Offset;
 183         u8      Reserved0:3;
 184         u8      CmdInit:1;
 185         u8      LastSeg:1;
 186         u8      FirstSeg:1;
 187         u8      LINIP:1;
 188         u8      OWN:1;
 189
 190         /* DWORD 1 */
 191         u8      TxFWInfoSize;
 192         u8      RATid:3;
 193         u8      DISFB:1;
 194         u8      USERATE:1;
 195         u8      MOREFRAG:1;
 196         u8      NoEnc:1;
 197         u8      PIFS:1;
 198         u8      QueueSelect:5;
 199         u8      NoACM:1;
 200         u8      Reserved1:2;
 201         u8      SecCAMID:5;
 202         u8      SecDescAssign:1;
 203         u8      SecType:2;
 204
 205         /* DWORD 2 */
 206         u16     TxBufferSize;
 207         u8      ResvForPaddingLen:7;
 208         u8      Reserved3:1;
 209         u8      Reserved4;
 210
 211         /* DWORD 3, 4, 5 */
 212         u32     Reserved5;
 213         u32     Reserved6;
 214         u32     Reserved7;
 215 };
 216
 217 struct tx_desc_cmd_819x_usb {
 218         /* DWORD 0 */
 219         u16     Reserved0;
 220         u8      Reserved1;
 221         u8      Reserved2:3;
 222         u8      CmdInit:1;
 223         u8      LastSeg:1;
 224         u8      FirstSeg:1;
 225         u8      LINIP:1;
 226         u8      OWN:1;
 227
 228         /* DOWRD 1 */
 229         u8      TxFWInfoSize;
 230         u8      Reserved3;
 231         u8      QueueSelect;
 232         u8      Reserved4;
 233
 234         /* DOWRD 2 */
 235         u16     TxBufferSize;
 236         u16     Reserved5;
 237
 238         /* DWORD 3, 4, 5 */
 239         u32     Reserved6;
 240         u32     Reserved7;
 241         u32     Reserved8;
 242 };
 243
 244 struct tx_fwinfo_819x_usb {
 245         /* DOWRD 0 */
 246         u8      TxRate:7;
 247         u8      CtsEnable:1;
 248         u8      RtsRate:7;
 249         u8      RtsEnable:1;
 250         u8      TxHT:1;
 251         u8      Short:1;        /* Error out, always on */
 252         u8      TxBandwidth:1;  /* Used for HT MCS rate only */
 253         u8      TxSubCarrier:2; /* Used for legacy OFDM rate only */
 254         u8      STBC:2;
 255         u8      AllowAggregation:1;
 256         /* Interpret RtsRate field as high throughput data rate */
 257         u8      RtsHT:1;
 258         u8      RtsShort:1;     /* Short PLCP for CCK or short GI for 11n MCS */
 259         u8      RtsBandwidth:1; /* Used for HT MCS rate only */
 260         u8      RtsSubcarrier:2;/* Used for legacy OFDM rate only */
 261         u8      RtsSTBC:2;
 262         /* Enable firmware to recalculate and assign packet duration */
 263         u8      EnableCPUDur:1;
 264
 265         /* DWORD 1 */
 266         u32     RxMF:2;
 267         u32     RxAMD:3;
 268         /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
 269         u32     TxPerPktInfoFeedback:1;
 270         u32     Reserved1:2;
 271         u32     TxAGCOffSet:4;
 272         u32     TxAGCSign:1;
 273         u32     Tx_INFO_RSVD:6;
 274         u32     PacketID:13;
 275 };
 276
 277 struct rtl8192_rx_info {
 278         struct urb *urb;
 279         struct net_device *dev;
 280         u8 out_pipe;
 281 };
 282
 283 struct rx_desc_819x_usb {
 284         /* DOWRD 0 */
 285         u16                 Length:14;
 286         u16                 CRC32:1;
 287         u16                 ICV:1;
 288         u8                  RxDrvInfoSize;
 289         u8                  Shift:2;
 290         u8                  PHYStatus:1;
 291         u8                  SWDec:1;
 292         u8                  Reserved1:4;
 293
 294         /* DWORD 1 */
 295         u32                 Reserved2;
 296 };
 297
 298 struct rx_drvinfo_819x_usb {
 299         /* DWORD 0 */
 300         u16                 Reserved1:12;
 301         u16                 PartAggr:1;
 302         u16                 FirstAGGR:1;
 303         u16                 Reserved2:2;
 304
 305         u8                  RxRate:7;
 306         u8                  RxHT:1;
 307
 308         u8                  BW:1;
 309         u8                  SPLCP:1;
 310         u8                  Reserved3:2;
 311         u8                  PAM:1;
 312         u8                  Mcast:1;
 313         u8                  Bcast:1;
 314         u8                  Reserved4:1;
 315
 316         /* DWORD 1 */
 317         u32                  TSFL;
 318
 319 };
 320
 321 /* Support till 64 bit bus width OS */
 322 #define MAX_DEV_ADDR_SIZE               8
 323 /* For RTL8190 */
 324 #define MAX_FIRMWARE_INFORMATION_SIZE   32
 325 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 326 #define ENCRYPTION_MAX_OVERHEAD         128
 327 #define USB_HWDESC_HEADER_LEN           sizeof(struct tx_desc_819x_usb)
 328 #define TX_PACKET_SHIFT_BYTES           (USB_HWDESC_HEADER_LEN + sizeof(struct tx_fwinfo_819x_usb))
 329 #define MAX_FRAGMENT_COUNT              8
 330 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 331 #define MAX_TRANSMIT_BUFFER_SIZE                        32000
 332 #else
 333 #define MAX_TRANSMIT_BUFFER_SIZE                        8000
 334 #endif
 335 /* Octets for crc32 (FCS, ICV) */
 336 #define scrclng                                 4
 337
 338 enum rf_op_type {
 339         RF_OP_By_SW_3wire = 0,
 340         RF_OP_By_FW,
 341         RF_OP_MAX
 342 };
 343
 344 /* 8190 Loopback Mode definition */
 345 typedef enum _rtl819xUsb_loopback {
 346         RTL819xU_NO_LOOPBACK = 0,
 347         RTL819xU_MAC_LOOPBACK = 1,
 348         RTL819xU_DMA_LOOPBACK = 2,
 349         RTL819xU_CCK_LOOPBACK = 3,
 350 } rtl819xUsb_loopback_e;
 351
 352 /* due to rtl8192 firmware */
 353 typedef enum _desc_packet_type_e {
 354         DESC_PACKET_TYPE_INIT = 0,
 355         DESC_PACKET_TYPE_NORMAL = 1,
 356 } desc_packet_type_e;
 357
 358 typedef enum _firmware_status {
 359         FW_STATUS_0_INIT = 0,
 360         FW_STATUS_1_MOVE_BOOT_CODE = 1,
 361         FW_STATUS_2_MOVE_MAIN_CODE = 2,
 362         FW_STATUS_3_TURNON_CPU = 3,
 363         FW_STATUS_4_MOVE_DATA_CODE = 4,
 364         FW_STATUS_5_READY = 5,
 365 } firmware_status_e;
 366
 367 typedef struct _fw_seg_container {
 368         u16     seg_size;
 369         u8      *seg_ptr;
 370 } fw_seg_container, *pfw_seg_container;
 371 typedef struct _rt_firmware {
 372         firmware_status_e firmware_status;
 373         u16               cmdpacket_frag_threshold;
 374 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000
 375         u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
 376         u16               firmware_buf_size;
 377 } rt_firmware, *prt_firmware;
 378
 379 /* Add this to 9100 bytes to receive A-MSDU from RT-AP */
 380 #define MAX_RECEIVE_BUFFER_SIZE 9100
 381
 382 typedef struct _rt_firmware_info_819xUsb {
 383         u8              sz_info[16];
 384 } rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
 385
 386 /* Firmware Queue Layout */
 387 #define NUM_OF_FIRMWARE_QUEUE           10
 388 #define NUM_OF_PAGES_IN_FW              0x100
 389
 390 #ifdef USE_ONE_PIPE
 391 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x000
 392 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x000
 393 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x0ff
 394 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x000
 395 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 396 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x0
 397 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
 398 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 399 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x0
 400 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x00
 401 #else
 402
 403 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
 404 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
 405 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
 406 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
 407 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 408 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
 409 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
 410 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 411 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 412 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
 413
 414 #endif
 415
 416 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 417 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 418 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 419 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 420 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 421 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 422 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 423 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 424 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 425
 426 /*
 427  * =================================================================
 428  * =================================================================
 429  */
 430
 431 #define EPROM_93c46 0
 432 #define EPROM_93c56 1
 433
 434 #define DEFAULT_FRAG_THRESHOLD 2342U
 435 #define MIN_FRAG_THRESHOLD     256U
 436 #define DEFAULT_BEACONINTERVAL 0x64U
 437 #define DEFAULT_BEACON_ESSID "Rtl819xU"
 438
 439 #define DEFAULT_SSID ""
 440 #define DEFAULT_RETRY_RTS 7
 441 #define DEFAULT_RETRY_DATA 7
 442 #define PRISM_HDR_SIZE 64
 443
 444 #define         PHY_RSSI_SLID_WIN_MAX                           100
 445
 446 typedef enum _WIRELESS_MODE {
 447         WIRELESS_MODE_UNKNOWN = 0x00,
 448         WIRELESS_MODE_A = 0x01,
 449         WIRELESS_MODE_B = 0x02,
 450         WIRELESS_MODE_G = 0x04,
 451         WIRELESS_MODE_AUTO = 0x08,
 452         WIRELESS_MODE_N_24G = 0x10,
 453         WIRELESS_MODE_N_5G = 0x20
 454 } WIRELESS_MODE;
 455
 456 #define RTL_IOCTL_WPA_SUPPLICANT                (SIOCIWFIRSTPRIV + 30)
 457
 458 typedef struct buffer {
 459         struct buffer *next;
 460         u32 *buf;
 461
 462 } buffer;
 463
 464 typedef struct rtl_reg_debug {
 465         unsigned int  cmd;
 466         struct {
 467                 unsigned char type;
 468                 unsigned char addr;
 469                 unsigned char page;
 470                 unsigned char length;
 471         } head;
 472         unsigned char buf[0xff];
 473 } rtl_reg_debug;
 474
 475 typedef struct _rt_9x_tx_rate_history {
 476         u32             cck[4];
 477         u32             ofdm[8];
 478         u32             ht_mcs[4][16];
 479 } rt_tx_rahis_t, *prt_tx_rahis_t;
 480 typedef struct _RT_SMOOTH_DATA_4RF {
 481         s8    elements[4][100]; /* array to store values */
 482         u32     index;            /* index to current array to store */
 483         u32     TotalNum;         /* num of valid elements */
 484         u32     TotalVal[4];      /* sum of valid elements */
 485 } RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 486
 487 /* This maybe changed for D-cut larger aggregation size */
 488 #define MAX_8192U_RX_SIZE                       8192
 489 /* Stats seems messed up, clean it ASAP */
 490 typedef struct Stats {
 491         unsigned long txrdu;
 492         unsigned long rxok;
 493         unsigned long rxframgment;
 494         unsigned long rxurberr;
 495         unsigned long rxstaterr;
 496         /* 0: Total, 1: OK, 2: CRC, 3: ICV */
 497         unsigned long received_rate_histogram[4][32];
 498         /* 0: Long preamble/GI, 1: Short preamble/GI */
 499         unsigned long received_preamble_GI[2][32];
 500         /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
 501         unsigned long rx_AMPDUsize_histogram[5];
 502         /* level: (<5), (5~10), (10~20), (20~40), (>40) */
 503         unsigned long rx_AMPDUnum_histogram[5];
 504         unsigned long numpacket_matchbssid;
 505         unsigned long numpacket_toself;
 506         unsigned long num_process_phyinfo;
 507         unsigned long numqry_phystatus;
 508         unsigned long numqry_phystatusCCK;
 509         unsigned long numqry_phystatusHT;
 510         /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
 511         unsigned long received_bwtype[5];
 512         unsigned long txnperr;
 513         unsigned long txnpdrop;
 514         unsigned long txresumed;
 515         unsigned long txnpokint;
 516         unsigned long txoverflow;
 517         unsigned long txlpokint;
 518         unsigned long txlpdrop;
 519         unsigned long txlperr;
 520         unsigned long txbeokint;
 521         unsigned long txbedrop;
 522         unsigned long txbeerr;
 523         unsigned long txbkokint;
 524         unsigned long txbkdrop;
 525         unsigned long txbkerr;
 526         unsigned long txviokint;
 527         unsigned long txvidrop;
 528         unsigned long txvierr;
 529         unsigned long txvookint;
 530         unsigned long txvodrop;
 531         unsigned long txvoerr;
 532         unsigned long txbeaconokint;
 533         unsigned long txbeacondrop;
 534         unsigned long txbeaconerr;
 535         unsigned long txmanageokint;
 536         unsigned long txmanagedrop;
 537         unsigned long txmanageerr;
 538         unsigned long txdatapkt;
 539         unsigned long txfeedback;
 540         unsigned long txfeedbackok;
 541
 542         unsigned long txoktotal;
 543         unsigned long txokbytestotal;
 544         unsigned long txokinperiod;
 545         unsigned long txmulticast;
 546         unsigned long txbytesmulticast;
 547         unsigned long txbroadcast;
 548         unsigned long txbytesbroadcast;
 549         unsigned long txunicast;
 550         unsigned long txbytesunicast;
 551
 552         unsigned long rxoktotal;
 553         unsigned long rxbytesunicast;
 554         unsigned long txfeedbackfail;
 555         unsigned long txerrtotal;
 556         unsigned long txerrbytestotal;
 557         unsigned long txerrmulticast;
 558         unsigned long txerrbroadcast;
 559         unsigned long txerrunicast;
 560         unsigned long txretrycount;
 561         unsigned long txfeedbackretry;
 562         u8            last_packet_rate;
 563         unsigned long slide_signal_strength[100];
 564         unsigned long slide_evm[100];
 565         /* For recording sliding window's RSSI value */
 566         unsigned long slide_rssi_total;
 567         /* For recording sliding window's EVM value */
 568         unsigned long slide_evm_total;
 569         /* Transformed in dbm. Beautified signal strength for UI, not correct */
 570         long signal_strength;
 571         long signal_quality;
 572         long last_signal_strength_inpercent;
 573         /* Correct smoothed ss in dbm, only used in driver
 574          * to report real power now
 575          */
 576         long recv_signal_power;
 577         u8 rx_rssi_percentage[4];
 578         u8 rx_evm_percentage[2];
 579         long rxSNRdB[4];
 580         rt_tx_rahis_t txrate;
 581         /* For beacon RSSI */
 582         u32 Slide_Beacon_pwdb[100];
 583         u32 Slide_Beacon_Total;
 584         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 585
 586         u32     CurrentShowTxate;
 587 } Stats;
 588
 589 /* Bandwidth Offset */
 590 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 591 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 592 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 593
 594 typedef struct  ChnlAccessSetting {
 595         u16 SIFS_Timer;
 596         u16 DIFS_Timer;
 597         u16 SlotTimeTimer;
 598         u16 EIFS_Timer;
 599         u16 CWminIndex;
 600         u16 CWmaxIndex;
 601 } *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING;
 602
 603 typedef struct _BB_REGISTER_DEFINITION {
 604         /* set software control:        0x870~0x877 [8 bytes]  */
 605         u32 rfintfs;
 606         /* readback data:               0x8e0~0x8e7 [8 bytes]  */
 607         u32 rfintfi;
 608         /* output data:                 0x860~0x86f [16 bytes] */
 609         u32 rfintfo;
 610         /* output enable:               0x860~0x86f [16 bytes] */
 611         u32 rfintfe;
 612         /* LSSI data:                   0x840~0x84f [16 bytes] */
 613         u32 rf3wireOffset;
 614         /* BB Band Select:              0x878~0x87f [8 bytes]  */
 615         u32 rfLSSI_Select;
 616         /* Tx gain stage:               0x80c~0x80f [4 bytes]  */
 617         u32 rfTxGainStage;
 618         /* wire parameter control1:     0x820~0x823, 0x828~0x82b,
 619          *                              0x830~0x833, 0x838~0x83b [16 bytes]
 620          */
 621         u32 rfHSSIPara1;
 622         /* wire parameter control2:     0x824~0x827, 0x82c~0x82f,
 623          *                              0x834~0x837, 0x83c~0x83f [16 bytes]
 624          */
 625         u32 rfHSSIPara2;
 626         /* Tx Rx antenna control:       0x858~0x85f [16 bytes] */
 627         u32 rfSwitchControl;
 628         /* AGC parameter control1:      0xc50~0xc53, 0xc58~0xc5b,
 629          *                              0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 630          */
 631         u32 rfAGCControl1;
 632         /* AGC parameter control2:      0xc54~0xc57, 0xc5c~0xc5f,
 633          *                              0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 634          */
 635         u32 rfAGCControl2;
 636         /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
 637          *                              0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 638          */
 639         u32 rfRxIQImbalance;
 640         /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
 641          *                              0xc10~0xc13, 0xc18~0xc1b,
 642          *                              0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 643          */
 644         u32 rfRxAFE;
 645         /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
 646          *                              0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 647          */
 648         u32 rfTxIQImbalance;
 649         /* Tx IQ DC Offset and Tx DFIR type:
 650          *                              0xc84~0xc87, 0xc8c~0xc8f,
 651          *                              0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 652          */
 653         u32 rfTxAFE;
 654         /* LSSI RF readback data:       0x8a0~0x8af [16 bytes] */
 655         u32 rfLSSIReadBack;
 656 } BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 657
 658 typedef enum _RT_RF_TYPE_819xU {
 659         RF_TYPE_MIN = 0,
 660         RF_8225,
 661         RF_8256,
 662         RF_8258,
 663         RF_PSEUDO_11N = 4,
 664 } RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
 665
 666 /* 2007/10/08 MH Define RATR state. */
 667 enum dynamic_ratr_state {
 668         DM_RATR_STA_HIGH = 0,
 669         DM_RATR_STA_MIDDLE = 1,
 670         DM_RATR_STA_LOW = 2,
 671         DM_RATR_STA_MAX
 672 };
 673
 674 typedef struct _rate_adaptive {
 675         u8                              rate_adaptive_disabled;
 676         enum dynamic_ratr_state         ratr_state;
 677         u16                             reserve;
 678
 679         u32                             high_rssi_thresh_for_ra;
 680         u32                             high2low_rssi_thresh_for_ra;
 681         u8                              low2high_rssi_thresh_for_ra40M;
 682         u32                             low_rssi_thresh_for_ra40M;
 683         u8                              low2high_rssi_thresh_for_ra20M;
 684         u32                             low_rssi_thresh_for_ra20M;
 685         u32                             upper_rssi_threshold_ratr;
 686         u32                             middle_rssi_threshold_ratr;
 687         u32                             low_rssi_threshold_ratr;
 688         u32                             low_rssi_threshold_ratr_40M;
 689         u32                             low_rssi_threshold_ratr_20M;
 690         u8                              ping_rssi_enable;
 691         u32                             ping_rssi_ratr;
 692         u32                             ping_rssi_thresh_for_ra;
 693         u32                             last_ratr;
 694
 695 } rate_adaptive, *prate_adaptive;
 696
 697 #define TxBBGainTableLength 37
 698 #define CCKTxBBGainTableLength 23
 699
 700 typedef struct _txbbgain_struct {
 701         long    txbb_iq_amplifygain;
 702         u32     txbbgain_value;
 703 } txbbgain_struct, *ptxbbgain_struct;
 704
 705 typedef struct _ccktxbbgain_struct {
 706         /* The value is from a22 to a29, one byte one time is much safer */
 707         u8      ccktxbb_valuearray[8];
 708 } ccktxbbgain_struct, *pccktxbbgain_struct;
 709
 710 typedef struct _init_gain {
 711         u8                              xaagccore1;
 712         u8                              xbagccore1;
 713         u8                              xcagccore1;
 714         u8                              xdagccore1;
 715         u8                              cca;
 716
 717 } init_gain, *pinit_gain;
 718
 719 typedef struct _phy_ofdm_rx_status_report_819xusb {
 720         u8      trsw_gain_X[4];
 721         u8      pwdb_all;
 722         u8      cfosho_X[4];
 723         u8      cfotail_X[4];
 724         u8      rxevm_X[2];
 725         u8      rxsnr_X[4];
 726         u8      pdsnr_X[2];
 727         u8      csi_current_X[2];
 728         u8      csi_target_X[2];
 729         u8      sigevm;
 730         u8      max_ex_pwr;
 731         u8      sgi_en;
 732         u8  rxsc_sgien_exflg;
 733 } phy_sts_ofdm_819xusb_t;
 734
 735 typedef struct _phy_cck_rx_status_report_819xusb {
 736         /* For CCK rate descriptor. This is an unsigned 8:1 variable.
 737          * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
 738          * Range from -64~+63.5.
 739          */
 740         u8      adc_pwdb_X[4];
 741         u8      sq_rpt;
 742         u8      cck_agc_rpt;
 743 } phy_sts_cck_819xusb_t;
 744
 745 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
 746         u8                      reserved:4;
 747         u8                      rxsc:2;
 748         u8                      sgi_en:1;
 749         u8                      ex_intf_flag:1;
 750 };
 751
 752 typedef enum _RT_CUSTOMER_ID {
 753         RT_CID_DEFAULT = 0,
 754         RT_CID_8187_ALPHA0 = 1,
 755         RT_CID_8187_SERCOMM_PS = 2,
 756         RT_CID_8187_HW_LED = 3,
 757         RT_CID_8187_NETGEAR = 4,
 758         RT_CID_WHQL = 5,
 759         RT_CID_819x_CAMEO  = 6,
 760         RT_CID_819x_RUNTOP = 7,
 761         RT_CID_819x_Senao = 8,
 762         RT_CID_TOSHIBA = 9,
 763         RT_CID_819x_Netcore = 10,
 764         RT_CID_Nettronix = 11,
 765         RT_CID_DLINK = 12,
 766         RT_CID_PRONET = 13,
 767 } RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 768
 769 /*
 770  * ==========================================================================
 771  * LED customization.
 772  * ==========================================================================
 773  */
 774
 775 typedef enum _LED_STRATEGY_8190 {
 776         SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
 777         SW_LED_MODE1, /* SW control for PCI Express */
 778         SW_LED_MODE2, /* SW control for Cameo. */
 779         SW_LED_MODE3, /* SW control for RunTop. */
 780         SW_LED_MODE4, /* SW control for Netcore. */
 781         /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
 782         HW_LED,
 783 } LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 784
 785 typedef enum _RESET_TYPE {
 786         RESET_TYPE_NORESET = 0x00,
 787         RESET_TYPE_NORMAL = 0x01,
 788         RESET_TYPE_SILENT = 0x02
 789 } RESET_TYPE;
 790
 791 /* The simple tx command OP code. */
 792 typedef enum _tag_TxCmd_Config_Index {
 793         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 794         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 795         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 796         TXCMD_SET_TX_DURATION                           = 0xFF900003,
 797         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 798         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 799         TXCMD_XXXX_CTRL,
 800 } DCMD_TXCMD_OP;
 801
 802 enum version_819xu {
 803         VERSION_819XU_A, // A-cut
 804         VERSION_819XU_B, // B-cut
 805         VERSION_819XU_C,// C-cut
 806 };
 807
 808 //added for different RF type
 809 enum rt_rf_type {
 810         RF_1T2R = 0,
 811         RF_2T4R,
 812 };
 813
 814 typedef struct r8192_priv {
 815         struct usb_device *udev;
 816         /* For maintain info from eeprom */
 817         short epromtype;
 818         u16 eeprom_vid;
 819         u16 eeprom_pid;
 820         u8  eeprom_CustomerID;
 821         u8  eeprom_ChannelPlan;
 822         RT_CUSTOMER_ID CustomerID;
 823         LED_STRATEGY_8190       LedStrategy;
 824         u8  txqueue_to_outpipemap[9];
 825         int irq;
 826         struct ieee80211_device *ieee80211;
 827
 828         /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
 829         short card_8192;
 830         /* If TCR reports card V B/C, this discriminates */
 831         enum version_819xu card_8192_version;
 832         short enable_gpio0;
 833         enum card_type {
 834                 PCI, MINIPCI, CARDBUS, USB
 835         } card_type;
 836         short hw_plcp_len;
 837         short plcp_preamble_mode;
 838
 839         spinlock_t irq_lock;
 840         spinlock_t tx_lock;
 841         struct mutex mutex;
 842
 843         u16 irq_mask;
 844         short chan;
 845         short sens;
 846         short max_sens;
 847
 848         short up;
 849         /* If 1, allow bad crc frame, reception in monitor mode */
 850         short crcmon;
 851
 852         struct mutex wx_mutex;
 853
 854         enum rt_rf_type   rf_type;          /* 0: 1T2R, 1: 2T4R */
 855         RT_RF_TYPE_819xU rf_chip;
 856
 857         short (*rf_set_sens)(struct net_device *dev, short sens);
 858         u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
 859         void (*rf_close)(struct net_device *dev);
 860         void (*rf_init)(struct net_device *dev);
 861         short promisc;
 862         /* Stats */
 863         struct Stats stats;
 864         struct iw_statistics wstats;
 865
 866         /* RX stuff */
 867         struct urb **rx_urb;
 868         struct urb **rx_cmd_urb;
 869 #ifdef THOMAS_BEACON
 870         u32 *oldaddr;
 871 #endif
 872 #ifdef THOMAS_TASKLET
 873         atomic_t irt_counter; /* count for irq_rx_tasklet */
 874 #endif
 875 #ifdef JACKSON_NEW_RX
 876         struct sk_buff **pp_rxskb;
 877         int     rx_inx;
 878 #endif
 879
 880         struct sk_buff_head rx_queue;
 881         struct sk_buff_head skb_queue;
 882         struct work_struct qos_activate;
 883         short  tx_urb_index;
 884         atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
 885
 886         struct tasklet_struct irq_rx_tasklet;
 887         struct urb *rxurb_task;
 888
 889         /* Tx Related variables */
 890         u16     ShortRetryLimit;
 891         u16     LongRetryLimit;
 892         u32     TransmitConfig;
 893         u8      RegCWinMin;     /* For turbo mode CW adaptive */
 894
 895         u32     LastRxDescTSFHigh;
 896         u32     LastRxDescTSFLow;
 897
 898         /* Rx Related variables */
 899         u16     EarlyRxThreshold;
 900         u32     ReceiveConfig;
 901         u8      AcmControl;
 902
 903         u8      RFProgType;
 904
 905         u8 retry_data;
 906         u8 retry_rts;
 907         u16 rts;
 908
 909         struct  ChnlAccessSetting  ChannelAccessSetting;
 910         struct work_struct reset_wq;
 911
 912 /**********************************************************/
 913         /* For rtl819xUsb */
 914         u16     basic_rate;
 915         u8      short_preamble;
 916         u8      slot_time;
 917         bool    bDcut;
 918         bool bCurrentRxAggrEnable;
 919         enum rf_op_type Rf_Mode;        /* For Firmware RF -R/W switch */
 920         prt_firmware            pFirmware;
 921         rtl819xUsb_loopback_e   LoopbackMode;
 922         u16 EEPROMTxPowerDiff;
 923         u8 EEPROMThermalMeter;
 924         u8 EEPROMPwDiff;
 925         u8 EEPROMCrystalCap;
 926         u8 EEPROM_Def_Ver;
 927         u8 EEPROMTxPowerLevelCCK;               /* CCK channel 1~14 */
 928         u8 EEPROMTxPowerLevelCCK_V1[3];
 929         u8 EEPROMTxPowerLevelOFDM24G[3];        /* OFDM 2.4G channel 1~14 */
 930         u8 EEPROMTxPowerLevelOFDM5G[24];        /* OFDM 5G */
 931
 932         /* PHY related */
 933         BB_REGISTER_DEFINITION_T PHYRegDef[4];  /* Radio A/B/C/D */
 934         /* Read/write are allow for following hardware information variables */
 935         u32     MCSTxPowerLevelOriginalOffset[6];
 936         u32     CCKTxPowerLevelOriginalOffset;
 937         u8      TxPowerLevelCCK[14];            /* CCK channel 1~14 */
 938         u8      TxPowerLevelOFDM24G[14];        /* OFDM 2.4G channel 1~14 */
 939         u8      TxPowerLevelOFDM5G[14];         /* OFDM 5G */
 940         u32     Pwr_Track;
 941         u8      TxPowerDiff;
 942         u8      AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
 943         u8      CrystalCap;
 944         u8      ThermalMeter[2];    /* index 0: RFIC0, index 1: RFIC1 */
 945
 946         u8      CckPwEnl;
 947         /* Use to calculate PWBD */
 948         u8      bCckHighPower;
 949         long    undecorated_smoothed_pwdb;
 950
 951         /* For set channel */
 952         u8      SwChnlInProgress;
 953         u8      SwChnlStage;
 954         u8      SwChnlStep;
 955         u8      SetBWModeInProgress;
 956         enum ht_channel_width   CurrentChannelBW;
 957         u8      ChannelPlan;
 958         /* 8190 40MHz mode */
 959         /* Control channel sub-carrier */
 960         u8      nCur40MhzPrimeSC;
 961         /* Test for shorten RF configuration time.
 962          * We save RF reg0 in this variable to reduce RF reading.
 963          */
 964         u32                                     RfReg0Value[4];
 965         u8                                      NumTotalRFPath;
 966         bool                            brfpath_rxenable[4];
 967         /* RF set related */
 968         bool                            SetRFPowerStateInProgress;
 969         struct timer_list watch_dog_timer;
 970
 971         /* For dynamic mechanism */
 972         /* Tx Power Control for Near/Far Range */
 973         bool    bdynamic_txpower;
 974         bool    bDynamicTxHighPower;
 975         bool    bDynamicTxLowPower;
 976         bool    bLastDTPFlag_High;
 977         bool    bLastDTPFlag_Low;
 978
 979         bool    bstore_last_dtpflag;
 980         /* Define to discriminate on High power State or
 981          * on sitesurvey to change Tx gain index
 982          */
 983         bool    bstart_txctrl_bydtp;
 984         rate_adaptive rate_adaptive;
 985         /* TX power tracking
 986          * OPEN/CLOSE TX POWER TRACKING
 987          */
 988         txbbgain_struct txbbgain_table[TxBBGainTableLength];
 989         u8              txpower_count; /* For 6 sec do tracking again */
 990         bool            btxpower_trackingInit;
 991         u8              OFDM_index;
 992         u8              CCK_index;
 993         /* CCK TX Power Tracking */
 994         ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
 995         ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
 996         u8 rfa_txpowertrackingindex;
 997         u8 rfa_txpowertrackingindex_real;
 998         u8 rfa_txpowertracking_default;
 999         u8 rfc_txpowertrackingindex;
1000         u8 rfc_txpowertrackingindex_real;
1001
1002         s8 cck_present_attenuation;
1003         u8 cck_present_attenuation_20Mdefault;
1004         u8 cck_present_attenuation_40Mdefault;
1005         s8 cck_present_attenuation_difference;
1006         bool btxpower_tracking;
1007         bool bcck_in_ch14;
1008         bool btxpowerdata_readfromEEPORM;
1009         u16     TSSI_13dBm;
1010         init_gain initgain_backup;
1011         u8 DefaultInitialGain[4];
1012         /* For EDCA Turbo mode */
1013         bool            bis_any_nonbepkts;
1014         bool            bcurrent_turbo_EDCA;
1015         bool            bis_cur_rdlstate;
1016         struct timer_list fsync_timer;
1017         bool bfsync_processing; /* 500ms Fsync timer is active or not */
1018         u32     rate_record;
1019         u32     rateCountDiffRecord;
1020         u32     ContinueDiffCount;
1021         bool bswitch_fsync;
1022
1023         u8      framesync;
1024         u32     framesyncC34;
1025         u8      framesyncMonitor;
1026         u16     nrxAMPDU_size;
1027         u8      nrxAMPDU_aggr_num;
1028
1029         /* For gpio */
1030         bool bHwRadioOff;
1031
1032         u32 reset_count;
1033         bool bpbc_pressed;
1034         u32 txpower_checkcnt;
1035         u32 txpower_tracking_callback_cnt;
1036         u8 thermal_read_val[40];
1037         u8 thermal_readback_index;
1038         u32 ccktxpower_adjustcnt_not_ch14;
1039         u32 ccktxpower_adjustcnt_ch14;
1040         u8 tx_fwinfo_force_subcarriermode;
1041         u8 tx_fwinfo_force_subcarrierval;
1042         /* For silent reset */
1043         RESET_TYPE      ResetProgress;
1044         bool            bForcedSilentReset;
1045         bool            bDisableNormalResetCheck;
1046         u16             TxCounter;
1047         u16             RxCounter;
1048         int             IrpPendingCount;
1049         bool            bResetInProgress;
1050         bool            force_reset;
1051         u8              InitialGainOperateType;
1052
1053         u16             SifsTime;
1054
1055         /* Define work item */
1056
1057         struct delayed_work update_beacon_wq;
1058         struct delayed_work watch_dog_wq;
1059         struct delayed_work txpower_tracking_wq;
1060         struct delayed_work rfpath_check_wq;
1061         struct delayed_work gpio_change_rf_wq;
1062         struct delayed_work initialgain_operate_wq;
1063         struct workqueue_struct *priv_wq;
1064 } r8192_priv;
1065
1066 /* For rtl8187B */
1067 typedef enum{
1068         BULK_PRIORITY = 0x01,
1069         LOW_PRIORITY,
1070         NORM_PRIORITY,
1071         VO_PRIORITY,
1072         VI_PRIORITY,
1073         BE_PRIORITY,
1074         BK_PRIORITY,
1075         RSVD2,
1076         RSVD3,
1077         BEACON_PRIORITY,
1078         HIGH_PRIORITY,
1079         MANAGE_PRIORITY,
1080         RSVD4,
1081         RSVD5,
1082         UART_PRIORITY
1083 } priority_t;
1084
1085 typedef enum {
1086         NIC_8192U = 1,
1087         NIC_8190P = 2,
1088         NIC_8192E = 3,
1089 } nic_t;
1090
1091 bool init_firmware(struct net_device *dev);
1092 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1093 short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1094
1095 int read_nic_byte(struct net_device *dev, int x, u8 *data);
1096 int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1097 int read_nic_dword(struct net_device *dev, int x, u32 *data);
1098 int read_nic_word(struct net_device *dev, int x, u16 *data);
1099 int write_nic_byte(struct net_device *dev, int x, u8 y);
1100 int write_nic_byte_E(struct net_device *dev, int x, u8 y);
1101 int write_nic_word(struct net_device *dev, int x, u16 y);
1102 int write_nic_dword(struct net_device *dev, int x, u32 y);
1103 void force_pci_posting(struct net_device *dev);
1104
1105 void rtl8192_rtx_disable(struct net_device *dev);
1106 void rtl8192_rx_enable(struct net_device *dev);
1107
1108 void rtl8192_update_msr(struct net_device *dev);
1109 int rtl8192_down(struct net_device *dev);
1110 int rtl8192_up(struct net_device *dev);
1111 void rtl8192_commit(struct net_device *dev);
1112 void rtl8192_set_chan(struct net_device *dev, short ch);
1113 void rtl8192_set_rxconf(struct net_device *dev);
1114 void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate);
1115
1116 void EnableHWSecurityConfig8192(struct net_device *dev);
1117 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1118
1119 #endif