drivers/staging/wilc1000/spi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
   4  * All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/spi/spi.h>
   9
  10 #include "netdev.h"
  11 #include "cfg80211.h"
  12
  13 struct wilc_spi {
  14         int crc_off;
  15         int nint;
  16 };
  17
  18 static const struct wilc_hif_func wilc_hif_spi;
  19
  20 /********************************************
  21  *
  22  *      Crc7
  23  *
  24  ********************************************/
  25
  26 static const u8 crc7_syndrome_table[256] = {
  27         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  28         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  29         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  30         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  31         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  32         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  33         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  34         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  35         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  36         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  37         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  38         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  39         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  40         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  41         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  42         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  43         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  44         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  45         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  46         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  47         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  48         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  49         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  50         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  51         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  52         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  53         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  54         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  55         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  56         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  57         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  58         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  59 };
  60
  61 static u8 crc7_byte(u8 crc, u8 data)
  62 {
  63         return crc7_syndrome_table[(crc << 1) ^ data];
  64 }
  65
  66 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
  67 {
  68         while (len--)
  69                 crc = crc7_byte(crc, *buffer++);
  70         return crc;
  71 }
  72
  73 /********************************************
  74  *
  75  *      Spi protocol Function
  76  *
  77  ********************************************/
  78
  79 #define CMD_DMA_WRITE                           0xc1
  80 #define CMD_DMA_READ                            0xc2
  81 #define CMD_INTERNAL_WRITE                      0xc3
  82 #define CMD_INTERNAL_READ                       0xc4
  83 #define CMD_TERMINATE                           0xc5
  84 #define CMD_REPEAT                              0xc6
  85 #define CMD_DMA_EXT_WRITE                       0xc7
  86 #define CMD_DMA_EXT_READ                        0xc8
  87 #define CMD_SINGLE_WRITE                        0xc9
  88 #define CMD_SINGLE_READ                         0xca
  89 #define CMD_RESET                               0xcf
  90
  91 #define DATA_PKT_SZ_256                         256
  92 #define DATA_PKT_SZ_512                         512
  93 #define DATA_PKT_SZ_1K                          1024
  94 #define DATA_PKT_SZ_4K                          (4 * 1024)
  95 #define DATA_PKT_SZ_8K                          (8 * 1024)
  96 #define DATA_PKT_SZ                             DATA_PKT_SZ_8K
  97
  98 #define USE_SPI_DMA                             0
  99
 100 static int wilc_bus_probe(struct spi_device *spi)
 101 {
 102         int ret;
 103         struct wilc *wilc;
 104         struct gpio_desc *gpio;
 105         struct wilc_spi *spi_priv;
 106
 107         spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
 108         if (!spi_priv)
 109                 return -ENOMEM;
 110
 111         gpio = gpiod_get(&spi->dev, "irq", GPIOD_IN);
 112         if (IS_ERR(gpio)) {
 113                 /* get the GPIO descriptor from hardcode GPIO number */
 114                 gpio = gpio_to_desc(GPIO_NUM);
 115                 if (!gpio)
 116                         dev_err(&spi->dev, "failed to get the irq gpio\n");
 117         }
 118
 119         ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
 120         if (ret) {
 121                 kfree(spi_priv);
 122                 return ret;
 123         }
 124
 125         spi_set_drvdata(spi, wilc);
 126         wilc->dev = &spi->dev;
 127         wilc->bus_data = spi_priv;
 128         wilc->gpio_irq = gpio;
 129
 130         wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk");
 131         if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER)
 132                 return -EPROBE_DEFER;
 133         else if (!IS_ERR(wilc->rtc_clk))
 134                 clk_prepare_enable(wilc->rtc_clk);
 135
 136         return 0;
 137 }
 138
 139 static int wilc_bus_remove(struct spi_device *spi)
 140 {
 141         struct wilc *wilc = spi_get_drvdata(spi);
 142
 143         /* free the GPIO in module remove */
 144         if (wilc->gpio_irq)
 145                 gpiod_put(wilc->gpio_irq);
 146
 147         if (!IS_ERR(wilc->rtc_clk))
 148                 clk_disable_unprepare(wilc->rtc_clk);
 149
 150         wilc_netdev_cleanup(wilc);
 151         return 0;
 152 }
 153
 154 static const struct of_device_id wilc_of_match[] = {
 155         { .compatible = "microchip,wilc1000-spi", },
 156         { /* sentinel */ }
 157 };
 158 MODULE_DEVICE_TABLE(of, wilc_of_match);
 159
 160 static struct spi_driver wilc_spi_driver = {
 161         .driver = {
 162                 .name = MODALIAS,
 163                 .of_match_table = wilc_of_match,
 164         },
 165         .probe =  wilc_bus_probe,
 166         .remove = wilc_bus_remove,
 167 };
 168 module_spi_driver(wilc_spi_driver);
 169 MODULE_LICENSE("GPL");
 170
 171 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
 172 {
 173         struct spi_device *spi = to_spi_device(wilc->dev);
 174         int ret;
 175         struct spi_message msg;
 176
 177         if (len > 0 && b) {
 178                 struct spi_transfer tr = {
 179                         .tx_buf = b,
 180                         .len = len,
 181                         .delay_usecs = 0,
 182                 };
 183                 char *r_buffer = kzalloc(len, GFP_KERNEL);
 184
 185                 if (!r_buffer)
 186                         return -ENOMEM;
 187
 188                 tr.rx_buf = r_buffer;
 189                 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
 190
 191                 memset(&msg, 0, sizeof(msg));
 192                 spi_message_init(&msg);
 193                 msg.spi = spi;
 194                 msg.is_dma_mapped = USE_SPI_DMA;
 195                 spi_message_add_tail(&tr, &msg);
 196
 197                 ret = spi_sync(spi, &msg);
 198                 if (ret < 0)
 199                         dev_err(&spi->dev, "SPI transaction failed\n");
 200
 201                 kfree(r_buffer);
 202         } else {
 203                 dev_err(&spi->dev,
 204                         "can't write data with the following length: %d\n",
 205                         len);
 206                 ret = -EINVAL;
 207         }
 208
 209         return ret;
 210 }
 211
 212 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
 213 {
 214         struct spi_device *spi = to_spi_device(wilc->dev);
 215         int ret;
 216
 217         if (rlen > 0) {
 218                 struct spi_message msg;
 219                 struct spi_transfer tr = {
 220                         .rx_buf = rb,
 221                         .len = rlen,
 222                         .delay_usecs = 0,
 223
 224                 };
 225                 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
 226
 227                 if (!t_buffer)
 228                         return -ENOMEM;
 229
 230                 tr.tx_buf = t_buffer;
 231
 232                 memset(&msg, 0, sizeof(msg));
 233                 spi_message_init(&msg);
 234                 msg.spi = spi;
 235                 msg.is_dma_mapped = USE_SPI_DMA;
 236                 spi_message_add_tail(&tr, &msg);
 237
 238                 ret = spi_sync(spi, &msg);
 239                 if (ret < 0)
 240                         dev_err(&spi->dev, "SPI transaction failed\n");
 241                 kfree(t_buffer);
 242         } else {
 243                 dev_err(&spi->dev,
 244                         "can't read data with the following length: %u\n",
 245                         rlen);
 246                 ret = -EINVAL;
 247         }
 248
 249         return ret;
 250 }
 251
 252 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
 253 {
 254         struct spi_device *spi = to_spi_device(wilc->dev);
 255         int ret;
 256
 257         if (rlen > 0) {
 258                 struct spi_message msg;
 259                 struct spi_transfer tr = {
 260                         .rx_buf = rb,
 261                         .tx_buf = wb,
 262                         .len = rlen,
 263                         .bits_per_word = 8,
 264                         .delay_usecs = 0,
 265
 266                 };
 267
 268                 memset(&msg, 0, sizeof(msg));
 269                 spi_message_init(&msg);
 270                 msg.spi = spi;
 271                 msg.is_dma_mapped = USE_SPI_DMA;
 272
 273                 spi_message_add_tail(&tr, &msg);
 274                 ret = spi_sync(spi, &msg);
 275                 if (ret < 0)
 276                         dev_err(&spi->dev, "SPI transaction failed\n");
 277         } else {
 278                 dev_err(&spi->dev,
 279                         "can't read data with the following length: %u\n",
 280                         rlen);
 281                 ret = -EINVAL;
 282         }
 283
 284         return ret;
 285 }
 286
 287 static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
 288                             u8 clockless)
 289 {
 290         struct spi_device *spi = to_spi_device(wilc->dev);
 291         struct wilc_spi *spi_priv = wilc->bus_data;
 292         u8 wb[32], rb[32];
 293         u8 wix, rix;
 294         u32 len2;
 295         u8 rsp;
 296         int len = 0;
 297         int result = 0;
 298         int retry;
 299         u8 crc[2];
 300
 301         wb[0] = cmd;
 302         switch (cmd) {
 303         case CMD_SINGLE_READ: /* single word (4 bytes) read */
 304                 wb[1] = (u8)(adr >> 16);
 305                 wb[2] = (u8)(adr >> 8);
 306                 wb[3] = (u8)adr;
 307                 len = 5;
 308                 break;
 309
 310         case CMD_INTERNAL_READ: /* internal register read */
 311                 wb[1] = (u8)(adr >> 8);
 312                 if (clockless == 1)
 313                         wb[1] |= BIT(7);
 314                 wb[2] = (u8)adr;
 315                 wb[3] = 0x00;
 316                 len = 5;
 317                 break;
 318
 319         case CMD_TERMINATE:
 320                 wb[1] = 0x00;
 321                 wb[2] = 0x00;
 322                 wb[3] = 0x00;
 323                 len = 5;
 324                 break;
 325
 326         case CMD_REPEAT:
 327                 wb[1] = 0x00;
 328                 wb[2] = 0x00;
 329                 wb[3] = 0x00;
 330                 len = 5;
 331                 break;
 332
 333         case CMD_RESET:
 334                 wb[1] = 0xff;
 335                 wb[2] = 0xff;
 336                 wb[3] = 0xff;
 337                 len = 5;
 338                 break;
 339
 340         case CMD_DMA_WRITE: /* dma write */
 341         case CMD_DMA_READ:  /* dma read */
 342                 wb[1] = (u8)(adr >> 16);
 343                 wb[2] = (u8)(adr >> 8);
 344                 wb[3] = (u8)adr;
 345                 wb[4] = (u8)(sz >> 8);
 346                 wb[5] = (u8)(sz);
 347                 len = 7;
 348                 break;
 349
 350         case CMD_DMA_EXT_WRITE: /* dma extended write */
 351         case CMD_DMA_EXT_READ:  /* dma extended read */
 352                 wb[1] = (u8)(adr >> 16);
 353                 wb[2] = (u8)(adr >> 8);
 354                 wb[3] = (u8)adr;
 355                 wb[4] = (u8)(sz >> 16);
 356                 wb[5] = (u8)(sz >> 8);
 357                 wb[6] = (u8)(sz);
 358                 len = 8;
 359                 break;
 360
 361         case CMD_INTERNAL_WRITE: /* internal register write */
 362                 wb[1] = (u8)(adr >> 8);
 363                 if (clockless == 1)
 364                         wb[1] |= BIT(7);
 365                 wb[2] = (u8)(adr);
 366                 wb[3] = b[3];
 367                 wb[4] = b[2];
 368                 wb[5] = b[1];
 369                 wb[6] = b[0];
 370                 len = 8;
 371                 break;
 372
 373         case CMD_SINGLE_WRITE: /* single word write */
 374                 wb[1] = (u8)(adr >> 16);
 375                 wb[2] = (u8)(adr >> 8);
 376                 wb[3] = (u8)(adr);
 377                 wb[4] = b[3];
 378                 wb[5] = b[2];
 379                 wb[6] = b[1];
 380                 wb[7] = b[0];
 381                 len = 9;
 382                 break;
 383
 384         default:
 385                 result = -EINVAL;
 386                 break;
 387         }
 388
 389         if (result)
 390                 return result;
 391
 392         if (!spi_priv->crc_off)
 393                 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
 394         else
 395                 len -= 1;
 396
 397 #define NUM_SKIP_BYTES (1)
 398 #define NUM_RSP_BYTES (2)
 399 #define NUM_DATA_HDR_BYTES (1)
 400 #define NUM_DATA_BYTES (4)
 401 #define NUM_CRC_BYTES (2)
 402 #define NUM_DUMMY_BYTES (3)
 403         if (cmd == CMD_RESET ||
 404             cmd == CMD_TERMINATE ||
 405             cmd == CMD_REPEAT) {
 406                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 407         } else if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
 408                 int tmp = NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 409                         + NUM_DUMMY_BYTES;
 410                 if (!spi_priv->crc_off)
 411                         len2 = len + tmp + NUM_CRC_BYTES;
 412                 else
 413                         len2 = len + tmp;
 414         } else {
 415                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 416         }
 417 #undef NUM_DUMMY_BYTES
 418
 419         if (len2 > ARRAY_SIZE(wb)) {
 420                 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
 421                         len2, ARRAY_SIZE(wb));
 422                 return -EINVAL;
 423         }
 424         /* zero spi write buffers. */
 425         for (wix = len; wix < len2; wix++)
 426                 wb[wix] = 0;
 427         rix = len;
 428
 429         if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
 430                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 431                 return -EINVAL;
 432         }
 433
 434         /*
 435          * Command/Control response
 436          */
 437         if (cmd == CMD_RESET || cmd == CMD_TERMINATE || cmd == CMD_REPEAT)
 438                 rix++; /* skip 1 byte */
 439
 440         rsp = rb[rix++];
 441
 442         if (rsp != cmd) {
 443                 dev_err(&spi->dev,
 444                         "Failed cmd response, cmd (%02x), resp (%02x)\n",
 445                         cmd, rsp);
 446                 return -EINVAL;
 447         }
 448
 449         /*
 450          * State response
 451          */
 452         rsp = rb[rix++];
 453         if (rsp != 0x00) {
 454                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 455                         rsp);
 456                 return -EINVAL;
 457         }
 458
 459         if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ ||
 460             cmd == CMD_DMA_READ || cmd == CMD_DMA_EXT_READ) {
 461                 /*
 462                  * Data Respnose header
 463                  */
 464                 retry = 100;
 465                 do {
 466                         /*
 467                          * ensure there is room in buffer later
 468                          * to read data and crc
 469                          */
 470                         if (rix < len2) {
 471                                 rsp = rb[rix++];
 472                         } else {
 473                                 retry = 0;
 474                                 break;
 475                         }
 476                         if (((rsp >> 4) & 0xf) == 0xf)
 477                                 break;
 478                 } while (retry--);
 479
 480                 if (retry <= 0) {
 481                         dev_err(&spi->dev,
 482                                 "Error, data read response (%02x)\n", rsp);
 483                         return -EAGAIN;
 484                 }
 485         }
 486
 487         if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
 488                 /*
 489                  * Read bytes
 490                  */
 491                 if ((rix + 3) < len2) {
 492                         b[0] = rb[rix++];
 493                         b[1] = rb[rix++];
 494                         b[2] = rb[rix++];
 495                         b[3] = rb[rix++];
 496                 } else {
 497                         dev_err(&spi->dev,
 498                                 "buffer overrun when reading data.\n");
 499                         return -EINVAL;
 500                 }
 501
 502                 if (!spi_priv->crc_off) {
 503                         /*
 504                          * Read Crc
 505                          */
 506                         if ((rix + 1) < len2) {
 507                                 crc[0] = rb[rix++];
 508                                 crc[1] = rb[rix++];
 509                         } else {
 510                                 dev_err(&spi->dev,
 511                                         "buffer overrun when reading crc.\n");
 512                                 return -EINVAL;
 513                         }
 514                 }
 515         } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 516                 int ix;
 517
 518                 /* some data may be read in response to dummy bytes. */
 519                 for (ix = 0; (rix < len2) && (ix < sz); )
 520                         b[ix++] = rb[rix++];
 521
 522                 sz -= ix;
 523
 524                 if (sz > 0) {
 525                         int nbytes;
 526
 527                         if (sz <= (DATA_PKT_SZ - ix))
 528                                 nbytes = sz;
 529                         else
 530                                 nbytes = DATA_PKT_SZ - ix;
 531
 532                         /*
 533                          * Read bytes
 534                          */
 535                         if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 536                                 dev_err(&spi->dev,
 537                                         "Failed block read, bus err\n");
 538                                 return -EINVAL;
 539                         }
 540
 541                         /*
 542                          * Read Crc
 543                          */
 544                         if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
 545                                 dev_err(&spi->dev,
 546                                         "Failed block crc read, bus err\n");
 547                                 return -EINVAL;
 548                         }
 549
 550                         ix += nbytes;
 551                         sz -= nbytes;
 552                 }
 553
 554                 /*
 555                  * if any data in left unread,
 556                  * then read the rest using normal DMA code.
 557                  */
 558                 while (sz > 0) {
 559                         int nbytes;
 560
 561                         if (sz <= DATA_PKT_SZ)
 562                                 nbytes = sz;
 563                         else
 564                                 nbytes = DATA_PKT_SZ;
 565
 566                         /*
 567                          * read data response only on the next DMA cycles not
 568                          * the first DMA since data response header is already
 569                          * handled above for the first DMA.
 570                          */
 571                         /*
 572                          * Data Respnose header
 573                          */
 574                         retry = 10;
 575                         do {
 576                                 if (wilc_spi_rx(wilc, &rsp, 1)) {
 577                                         dev_err(&spi->dev,
 578                                                 "Failed resp read, bus err\n");
 579                                         result = -EINVAL;
 580                                         break;
 581                                 }
 582                                 if (((rsp >> 4) & 0xf) == 0xf)
 583                                         break;
 584                         } while (retry--);
 585
 586                         if (result)
 587                                 break;
 588
 589                         /*
 590                          * Read bytes
 591                          */
 592                         if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 593                                 dev_err(&spi->dev,
 594                                         "Failed block read, bus err\n");
 595                                 result = -EINVAL;
 596                                 break;
 597                         }
 598
 599                         /*
 600                          * Read Crc
 601                          */
 602                         if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
 603                                 dev_err(&spi->dev,
 604                                         "Failed block crc read, bus err\n");
 605                                 result = -EINVAL;
 606                                 break;
 607                         }
 608
 609                         ix += nbytes;
 610                         sz -= nbytes;
 611                 }
 612         }
 613         return result;
 614 }
 615
 616 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
 617 {
 618         struct spi_device *spi = to_spi_device(wilc->dev);
 619         struct wilc_spi *spi_priv = wilc->bus_data;
 620         int ix, nbytes;
 621         int result = 0;
 622         u8 cmd, order, crc[2] = {0};
 623
 624         /*
 625          * Data
 626          */
 627         ix = 0;
 628         do {
 629                 if (sz <= DATA_PKT_SZ) {
 630                         nbytes = sz;
 631                         order = 0x3;
 632                 } else {
 633                         nbytes = DATA_PKT_SZ;
 634                         if (ix == 0)
 635                                 order = 0x1;
 636                         else
 637                                 order = 0x02;
 638                 }
 639
 640                 /*
 641                  * Write command
 642                  */
 643                 cmd = 0xf0;
 644                 cmd |= order;
 645
 646                 if (wilc_spi_tx(wilc, &cmd, 1)) {
 647                         dev_err(&spi->dev,
 648                                 "Failed data block cmd write, bus error...\n");
 649                         result = -EINVAL;
 650                         break;
 651                 }
 652
 653                 /*
 654                  * Write data
 655                  */
 656                 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
 657                         dev_err(&spi->dev,
 658                                 "Failed data block write, bus error...\n");
 659                         result = -EINVAL;
 660                         break;
 661                 }
 662
 663                 /*
 664                  * Write Crc
 665                  */
 666                 if (!spi_priv->crc_off) {
 667                         if (wilc_spi_tx(wilc, crc, 2)) {
 668                                 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
 669                                 result = -EINVAL;
 670                                 break;
 671                         }
 672                 }
 673
 674                 /*
 675                  * No need to wait for response
 676                  */
 677                 ix += nbytes;
 678                 sz -= nbytes;
 679         } while (sz);
 680
 681         return result;
 682 }
 683
 684 /********************************************
 685  *
 686  *      Spi Internal Read/Write Function
 687  *
 688  ********************************************/
 689
 690 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
 691 {
 692         struct spi_device *spi = to_spi_device(wilc->dev);
 693         int result;
 694
 695         cpu_to_le32s(&dat);
 696         result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
 697                                   0);
 698         if (result)
 699                 dev_err(&spi->dev, "Failed internal write cmd...\n");
 700
 701         return result;
 702 }
 703
 704 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
 705 {
 706         struct spi_device *spi = to_spi_device(wilc->dev);
 707         int result;
 708
 709         result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
 710                                   0);
 711         if (result) {
 712                 dev_err(&spi->dev, "Failed internal read cmd...\n");
 713                 return result;
 714         }
 715
 716         le32_to_cpus(data);
 717
 718         return result;
 719 }
 720
 721 /********************************************
 722  *
 723  *      Spi interfaces
 724  *
 725  ********************************************/
 726
 727 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
 728 {
 729         struct spi_device *spi = to_spi_device(wilc->dev);
 730         int result;
 731         u8 cmd = CMD_SINGLE_WRITE;
 732         u8 clockless = 0;
 733
 734         cpu_to_le32s(&data);
 735         if (addr < 0x30) {
 736                 /* Clockless register */
 737                 cmd = CMD_INTERNAL_WRITE;
 738                 clockless = 1;
 739         }
 740
 741         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
 742         if (result)
 743                 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
 744
 745         return result;
 746 }
 747
 748 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 749 {
 750         struct spi_device *spi = to_spi_device(wilc->dev);
 751         int result;
 752
 753         /*
 754          * has to be greated than 4
 755          */
 756         if (size <= 4)
 757                 return -EINVAL;
 758
 759         result = spi_cmd_complete(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size, 0);
 760         if (result) {
 761                 dev_err(&spi->dev,
 762                         "Failed cmd, write block (%08x)...\n", addr);
 763                 return result;
 764         }
 765
 766         /*
 767          * Data
 768          */
 769         result = spi_data_write(wilc, buf, size);
 770         if (result)
 771                 dev_err(&spi->dev, "Failed block data write...\n");
 772
 773         return result;
 774 }
 775
 776 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
 777 {
 778         struct spi_device *spi = to_spi_device(wilc->dev);
 779         int result;
 780         u8 cmd = CMD_SINGLE_READ;
 781         u8 clockless = 0;
 782
 783         if (addr < 0x30) {
 784                 /* Clockless register */
 785                 cmd = CMD_INTERNAL_READ;
 786                 clockless = 1;
 787         }
 788
 789         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
 790         if (result) {
 791                 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
 792                 return result;
 793         }
 794
 795         le32_to_cpus(data);
 796
 797         return 0;
 798 }
 799
 800 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 801 {
 802         struct spi_device *spi = to_spi_device(wilc->dev);
 803         int result;
 804
 805         if (size <= 4)
 806                 return -EINVAL;
 807
 808         result = spi_cmd_complete(wilc, CMD_DMA_EXT_READ, addr, buf, size, 0);
 809         if (result)
 810                 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
 811
 812         return result;
 813 }
 814
 815 /********************************************
 816  *
 817  *      Bus interfaces
 818  *
 819  ********************************************/
 820
 821 static int wilc_spi_deinit(struct wilc *wilc)
 822 {
 823         /*
 824          * TODO:
 825          */
 826         return 0;
 827 }
 828
 829 static int wilc_spi_init(struct wilc *wilc, bool resume)
 830 {
 831         struct spi_device *spi = to_spi_device(wilc->dev);
 832         struct wilc_spi *spi_priv = wilc->bus_data;
 833         u32 reg;
 834         u32 chipid;
 835         static int isinit;
 836         int ret;
 837
 838         if (isinit) {
 839                 ret = wilc_spi_read_reg(wilc, 0x1000, &chipid);
 840                 if (ret)
 841                         dev_err(&spi->dev, "Fail cmd read chip id...\n");
 842
 843                 return ret;
 844         }
 845
 846         /*
 847          * configure protocol
 848          */
 849
 850         /*
 851          * TODO: We can remove the CRC trials if there is a definite
 852          * way to reset
 853          */
 854         /* the SPI to it's initial value. */
 855         ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg);
 856         if (ret) {
 857                 /*
 858                  * Read failed. Try with CRC off. This might happen when module
 859                  * is removed but chip isn't reset
 860                  */
 861                 spi_priv->crc_off = 1;
 862                 dev_err(&spi->dev,
 863                         "Failed read with CRC on, retrying with CRC off\n");
 864                 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg);
 865                 if (ret) {
 866                         /*
 867                          * Read failed with both CRC on and off,
 868                          * something went bad
 869                          */
 870                         dev_err(&spi->dev, "Failed internal read protocol\n");
 871                         return ret;
 872                 }
 873         }
 874         if (spi_priv->crc_off == 0) {
 875                 reg &= ~0xc; /* disable crc checking */
 876                 reg &= ~0x70;
 877                 reg |= (0x5 << 4);
 878                 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg);
 879                 if (ret) {
 880                         dev_err(&spi->dev,
 881                                 "[wilc spi %d]: Failed internal write reg\n",
 882                                 __LINE__);
 883                         return ret;
 884                 }
 885                 spi_priv->crc_off = 1;
 886         }
 887
 888         /*
 889          * make sure can read back chip id correctly
 890          */
 891         ret = wilc_spi_read_reg(wilc, 0x1000, &chipid);
 892         if (ret) {
 893                 dev_err(&spi->dev, "Fail cmd read chip id...\n");
 894                 return ret;
 895         }
 896
 897         isinit = 1;
 898
 899         return 0;
 900 }
 901
 902 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
 903 {
 904         int ret;
 905
 906         ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, size);
 907         *size = *size & IRQ_DMA_WD_CNT_MASK;
 908
 909         return ret;
 910 }
 911
 912 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
 913 {
 914         return spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, int_status);
 915 }
 916
 917 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
 918 {
 919         return spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE, val);
 920 }
 921
 922 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
 923 {
 924         struct spi_device *spi = to_spi_device(wilc->dev);
 925         struct wilc_spi *spi_priv = wilc->bus_data;
 926         u32 reg;
 927         int ret, i;
 928
 929         if (nint > MAX_NUM_INT) {
 930                 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
 931                 return -EINVAL;
 932         }
 933
 934         spi_priv->nint = nint;
 935
 936         /*
 937          * interrupt pin mux select
 938          */
 939         ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
 940         if (ret) {
 941                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
 942                         WILC_PIN_MUX_0);
 943                 return ret;
 944         }
 945         reg |= BIT(8);
 946         ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
 947         if (ret) {
 948                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
 949                         WILC_PIN_MUX_0);
 950                 return ret;
 951         }
 952
 953         /*
 954          * interrupt enable
 955          */
 956         ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
 957         if (ret) {
 958                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
 959                         WILC_INTR_ENABLE);
 960                 return ret;
 961         }
 962
 963         for (i = 0; (i < 5) && (nint > 0); i++, nint--)
 964                 reg |= (BIT((27 + i)));
 965
 966         ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
 967         if (ret) {
 968                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
 969                         WILC_INTR_ENABLE);
 970                 return ret;
 971         }
 972         if (nint) {
 973                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
 974                 if (ret) {
 975                         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
 976                                 WILC_INTR2_ENABLE);
 977                         return ret;
 978                 }
 979
 980                 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
 981                         reg |= BIT(i);
 982
 983                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
 984                 if (ret) {
 985                         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
 986                                 WILC_INTR2_ENABLE);
 987                         return ret;
 988                 }
 989         }
 990
 991         return 0;
 992 }
 993
 994 /* Global spi HIF function table */
 995 static const struct wilc_hif_func wilc_hif_spi = {
 996         .hif_init = wilc_spi_init,
 997         .hif_deinit = wilc_spi_deinit,
 998         .hif_read_reg = wilc_spi_read_reg,
 999         .hif_write_reg = wilc_spi_write_reg,
1000         .hif_block_rx = wilc_spi_read,
1001         .hif_block_tx = wilc_spi_write,
1002         .hif_read_int = wilc_spi_read_int,
1003         .hif_clear_int_ext = wilc_spi_clear_int_ext,
1004         .hif_read_size = wilc_spi_read_size,
1005         .hif_block_tx_ext = wilc_spi_write,
1006         .hif_block_rx_ext = wilc_spi_read,
1007         .hif_sync_ext = wilc_spi_sync_ext,
1008 };