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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_exar.c
blob91e9b070d36d1d44d94b0408747412538e1e05f8
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/8250_pci.h>
22 #include <linux/delay.h>
23
24 #include <asm/byteorder.h>
25
26 #include "8250.h"
27
28 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
29 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
30 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
31 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
32 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
33 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
34 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
35 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
36 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
37
38 #define UART_EXAR_INT0 0x80
39 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
40 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
41 #define UART_EXAR_DVID 0x8d /* Device identification */
42
43 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
44 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
45 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
46 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
47 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
48 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
49 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
50
51 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
52 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
53
54 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
55 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
56 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
57 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
58 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
59 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
60 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
61 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
62 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
63 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
64 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
65 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
66
67 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
68
69 /*
70 * IOT2040 MPIO wiring semantics:
71 *
72 * MPIO Port Function
73 * ---- ---- --------
74 * 0 2 Mode bit 0
75 * 1 2 Mode bit 1
76 * 2 2 Terminate bus
77 * 3 - <reserved>
78 * 4 3 Mode bit 0
79 * 5 3 Mode bit 1
80 * 6 3 Terminate bus
81 * 7 - <reserved>
82 * 8 2 Enable
83 * 9 3 Enable
84 * 10 - Red LED
85 * 11..15 - <unused>
86 */
87
88 /* IOT2040 MPIOs 0..7 */
89 #define IOT2040_UART_MODE_RS232 0x01
90 #define IOT2040_UART_MODE_RS485 0x02
91 #define IOT2040_UART_MODE_RS422 0x03
92 #define IOT2040_UART_TERMINATE_BUS 0x04
93
94 #define IOT2040_UART1_MASK 0x0f
95 #define IOT2040_UART2_SHIFT 4
96
97 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
98 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
99
100 /* IOT2040 MPIOs 8..15 */
101 #define IOT2040_UARTS_ENABLE 0x03
102 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
103
104 struct exar8250;
105
106 struct exar8250_platform {
107 int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
108 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
109 };
110
111 /**
112 * struct exar8250_board - board information
113 * @num_ports: number of serial ports
114 * @reg_shift: describes UART register mapping in PCI memory
115 * @setup: quirk run at ->probe() stage
116 * @exit: quirk run at ->remove() stage
117 */
118 struct exar8250_board {
119 unsigned int num_ports;
120 unsigned int reg_shift;
121 int (*setup)(struct exar8250 *, struct pci_dev *,
122 struct uart_8250_port *, int);
123 void (*exit)(struct pci_dev *pcidev);
124 };
125
126 struct exar8250 {
127 unsigned int nr;
128 struct exar8250_board *board;
129 void __iomem *virt;
130 int line[0];
131 };
132
133 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
134 {
135 /*
136 * Exar UARTs have a SLEEP register that enables or disables each UART
137 * to enter sleep mode separately. On the XR17V35x the register
138 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
139 * the UART channel may only write to the corresponding bit.
140 */
141 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
142 }
143
144 /*
145 * XR17V35x UARTs have an extra fractional divisor register (DLD)
146 * Calculate divisor with extra 4-bit fractional portion
147 */
148 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
149 unsigned int *frac)
150 {
151 unsigned int quot_16;
152
153 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
154 *frac = quot_16 & 0x0f;
155
156 return quot_16 >> 4;
157 }
158
159 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
160 unsigned int quot, unsigned int quot_frac)
161 {
162 serial8250_do_set_divisor(p, baud, quot, quot_frac);
163
164 /* Preserve bits not related to baudrate; DLD[7:4]. */
165 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
166 serial_port_out(p, 0x2, quot_frac);
167 }
168
169 static int xr17v35x_startup(struct uart_port *port)
170 {
171 /*
172 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
173 * MCR [7:5] and MSR [7:0]
174 */
175 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
176
177 /*
178 * Make sure all interrups are masked until initialization is
179 * complete and the FIFOs are cleared
180 */
181 serial_port_out(port, UART_IER, 0);
182
183 return serial8250_do_startup(port);
184 }
185
186 static void exar_shutdown(struct uart_port *port)
187 {
188 unsigned char lsr;
189 bool tx_complete = false;
190 struct uart_8250_port *up = up_to_u8250p(port);
191 struct circ_buf *xmit = &port->state->xmit;
192 int i = 0;
193
194 do {
195 lsr = serial_in(up, UART_LSR);
196 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
197 tx_complete = true;
198 else
199 tx_complete = false;
200 usleep_range(1000, 1100);
201 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
202
203 serial8250_do_shutdown(port);
204 }
205
206 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
207 int idx, unsigned int offset,
208 struct uart_8250_port *port)
209 {
210 const struct exar8250_board *board = priv->board;
211 unsigned int bar = 0;
212 unsigned char status;
213
214 port->port.iotype = UPIO_MEM;
215 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
216 port->port.membase = priv->virt + offset;
217 port->port.regshift = board->reg_shift;
218
219 /*
220 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
221 * with when DLAB is set which will cause the device to incorrectly match
222 * and assign port type to PORT_16650. The EFR for this UART is found
223 * at offset 0x09. Instead check the Deice ID (DVID) register
224 * for a 2, 4 or 8 port UART.
225 */
226 status = readb(port->port.membase + UART_EXAR_DVID);
227 if (status == 0x82 || status == 0x84 || status == 0x88) {
228 port->port.type = PORT_XR17V35X;
229
230 port->port.get_divisor = xr17v35x_get_divisor;
231 port->port.set_divisor = xr17v35x_set_divisor;
232
233 port->port.startup = xr17v35x_startup;
234 } else {
235 port->port.type = PORT_XR17D15X;
236 }
237
238 port->port.pm = exar_pm;
239 port->port.shutdown = exar_shutdown;
240
241 return 0;
242 }
243
244 static int
245 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
246 struct uart_8250_port *port, int idx)
247 {
248 unsigned int offset = idx * 0x200;
249 unsigned int baud = 1843200;
250 u8 __iomem *p;
251 int err;
252
253 port->port.uartclk = baud * 16;
254
255 err = default_setup(priv, pcidev, idx, offset, port);
256 if (err)
257 return err;
258
259 p = port->port.membase;
260
261 writeb(0x00, p + UART_EXAR_8XMODE);
262 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
263 writeb(32, p + UART_EXAR_TXTRG);
264 writeb(32, p + UART_EXAR_RXTRG);
265
266 /*
267 * Setup Multipurpose Input/Output pins.
268 */
269 if (idx == 0) {
270 switch (pcidev->device) {
271 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
272 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
273 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
274 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
275 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
276 break;
277 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
278 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
279 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
280 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
281 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
282 break;
283 }
284 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
285 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
286 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
287 }
288
289 return 0;
290 }
291
292 static int
293 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
294 struct uart_8250_port *port, int idx)
295 {
296 unsigned int offset = idx * 0x200;
297 unsigned int baud = 1843200;
298
299 port->port.uartclk = baud * 16;
300 return default_setup(priv, pcidev, idx, offset, port);
301 }
302
303 static int
304 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
305 struct uart_8250_port *port, int idx)
306 {
307 unsigned int offset = idx * 0x200;
308 unsigned int baud = 921600;
309
310 port->port.uartclk = baud * 16;
311 return default_setup(priv, pcidev, idx, offset, port);
312 }
313
314 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
315 {
316 /*
317 * The Commtech adapters required the MPIOs to be driven low. The Exar
318 * devices will export them as GPIOs, so we pre-configure them safely
319 * as inputs.
320 */
321 u8 dir = pcidev->vendor == PCI_VENDOR_ID_EXAR ? 0xff : 0x00;
322
323 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
324 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
325 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
326 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
327 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
328 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
329 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
330 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
331 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
332 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
333 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
334 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
335 }
336
337 static void *
338 __xr17v35x_register_gpio(struct pci_dev *pcidev,
339 const struct property_entry *properties)
340 {
341 struct platform_device *pdev;
342
343 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
344 if (!pdev)
345 return NULL;
346
347 pdev->dev.parent = &pcidev->dev;
348 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
349
350 if (platform_device_add_properties(pdev, properties) < 0 ||
351 platform_device_add(pdev) < 0) {
352 platform_device_put(pdev);
353 return NULL;
354 }
355
356 return pdev;
357 }
358
359 static const struct property_entry exar_gpio_properties[] = {
360 PROPERTY_ENTRY_U32("exar,first-pin", 0),
361 PROPERTY_ENTRY_U32("ngpios", 16),
362 { }
363 };
364
365 static int xr17v35x_register_gpio(struct pci_dev *pcidev,
366 struct uart_8250_port *port)
367 {
368 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
369 port->port.private_data =
370 __xr17v35x_register_gpio(pcidev, exar_gpio_properties);
371
372 return 0;
373 }
374
375 static int generic_rs485_config(struct uart_port *port,
376 struct serial_rs485 *rs485)
377 {
378 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
379 u8 __iomem *p = port->membase;
380 u8 value;
381
382 value = readb(p + UART_EXAR_FCTR);
383 if (is_rs485)
384 value |= UART_FCTR_EXAR_485;
385 else
386 value &= ~UART_FCTR_EXAR_485;
387
388 writeb(value, p + UART_EXAR_FCTR);
389
390 if (is_rs485)
391 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
392
393 port->rs485 = *rs485;
394
395 return 0;
396 }
397
398 static const struct exar8250_platform exar8250_default_platform = {
399 .register_gpio = xr17v35x_register_gpio,
400 .rs485_config = generic_rs485_config,
401 };
402
403 static int iot2040_rs485_config(struct uart_port *port,
404 struct serial_rs485 *rs485)
405 {
406 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
407 u8 __iomem *p = port->membase;
408 u8 mask = IOT2040_UART1_MASK;
409 u8 mode, value;
410
411 if (is_rs485) {
412 if (rs485->flags & SER_RS485_RX_DURING_TX)
413 mode = IOT2040_UART_MODE_RS422;
414 else
415 mode = IOT2040_UART_MODE_RS485;
416
417 if (rs485->flags & SER_RS485_TERMINATE_BUS)
418 mode |= IOT2040_UART_TERMINATE_BUS;
419 } else {
420 mode = IOT2040_UART_MODE_RS232;
421 }
422
423 if (port->line == 3) {
424 mask <<= IOT2040_UART2_SHIFT;
425 mode <<= IOT2040_UART2_SHIFT;
426 }
427
428 value = readb(p + UART_EXAR_MPIOLVL_7_0);
429 value &= ~mask;
430 value |= mode;
431 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
432
433 return generic_rs485_config(port, rs485);
434 }
435
436 static const struct property_entry iot2040_gpio_properties[] = {
437 PROPERTY_ENTRY_U32("exar,first-pin", 10),
438 PROPERTY_ENTRY_U32("ngpios", 1),
439 { }
440 };
441
442 static int iot2040_register_gpio(struct pci_dev *pcidev,
443 struct uart_8250_port *port)
444 {
445 u8 __iomem *p = port->port.membase;
446
447 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
448 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
449 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
450 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
451
452 port->port.private_data =
453 __xr17v35x_register_gpio(pcidev, iot2040_gpio_properties);
454
455 return 0;
456 }
457
458 static const struct exar8250_platform iot2040_platform = {
459 .rs485_config = iot2040_rs485_config,
460 .register_gpio = iot2040_register_gpio,
461 };
462
463 /*
464 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
465 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
466 * board name after the device was found.
467 */
468 static const struct dmi_system_id exar_platforms[] = {
469 {
470 .matches = {
471 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
472 },
473 .driver_data = (void *)&iot2040_platform,
474 },
475 {}
476 };
477
478 static int
479 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
480 struct uart_8250_port *port, int idx)
481 {
482 const struct exar8250_platform *platform;
483 const struct dmi_system_id *dmi_match;
484 unsigned int offset = idx * 0x400;
485 unsigned int baud = 7812500;
486 u8 __iomem *p;
487 int ret;
488
489 dmi_match = dmi_first_match(exar_platforms);
490 if (dmi_match)
491 platform = dmi_match->driver_data;
492 else
493 platform = &exar8250_default_platform;
494
495 port->port.uartclk = baud * 16;
496 port->port.rs485_config = platform->rs485_config;
497
498 /*
499 * Setup the UART clock for the devices on expansion slot to
500 * half the clock speed of the main chip (which is 125MHz)
501 */
502 if (idx >= 8)
503 port->port.uartclk /= 2;
504
505 ret = default_setup(priv, pcidev, idx, offset, port);
506 if (ret)
507 return ret;
508
509 p = port->port.membase;
510
511 writeb(0x00, p + UART_EXAR_8XMODE);
512 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
513 writeb(128, p + UART_EXAR_TXTRG);
514 writeb(128, p + UART_EXAR_RXTRG);
515
516 if (idx == 0) {
517 /* Setup Multipurpose Input/Output pins. */
518 setup_gpio(pcidev, p);
519
520 ret = platform->register_gpio(pcidev, port);
521 }
522
523 return ret;
524 }
525
526 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
527 {
528 struct exar8250 *priv = pci_get_drvdata(pcidev);
529 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
530 struct platform_device *pdev = port->port.private_data;
531
532 platform_device_unregister(pdev);
533 port->port.private_data = NULL;
534 }
535
536 static inline void exar_misc_clear(struct exar8250 *priv)
537 {
538 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
539 readb(priv->virt + UART_EXAR_INT0);
540
541 /* Clear INT0 for Expansion Interface slave ports, too */
542 if (priv->board->num_ports > 8)
543 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
544 }
545
546 /*
547 * These Exar UARTs have an extra interrupt indicator that could fire for a
548 * few interrupts that are not presented/cleared through IIR. One of which is
549 * a wakeup interrupt when coming out of sleep. These interrupts are only
550 * cleared by reading global INT0 or INT1 registers as interrupts are
551 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
552 * channel's address space, but for the sake of bus efficiency we register a
553 * dedicated handler at the PCI device level to handle them.
554 */
555 static irqreturn_t exar_misc_handler(int irq, void *data)
556 {
557 exar_misc_clear(data);
558
559 return IRQ_HANDLED;
560 }
561
562 static int
563 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
564 {
565 unsigned int nr_ports, i, bar = 0, maxnr;
566 struct exar8250_board *board;
567 struct uart_8250_port uart;
568 struct exar8250 *priv;
569 int rc;
570
571 board = (struct exar8250_board *)ent->driver_data;
572 if (!board)
573 return -EINVAL;
574
575 rc = pcim_enable_device(pcidev);
576 if (rc)
577 return rc;
578
579 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
580
581 nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
582
583 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
584 if (!priv)
585 return -ENOMEM;
586
587 priv->board = board;
588 priv->virt = pcim_iomap(pcidev, bar, 0);
589 if (!priv->virt)
590 return -ENOMEM;
591
592 pci_set_master(pcidev);
593
594 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
595 if (rc < 0)
596 return rc;
597
598 memset(&uart, 0, sizeof(uart));
599 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
600 uart.port.irq = pci_irq_vector(pcidev, 0);
601 uart.port.dev = &pcidev->dev;
602
603 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
604 IRQF_SHARED, "exar_uart", priv);
605 if (rc)
606 return rc;
607
608 /* Clear interrupts */
609 exar_misc_clear(priv);
610
611 for (i = 0; i < nr_ports && i < maxnr; i++) {
612 rc = board->setup(priv, pcidev, &uart, i);
613 if (rc) {
614 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
615 break;
616 }
617
618 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
619 uart.port.iobase, uart.port.irq, uart.port.iotype);
620
621 priv->line[i] = serial8250_register_8250_port(&uart);
622 if (priv->line[i] < 0) {
623 dev_err(&pcidev->dev,
624 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
625 uart.port.iobase, uart.port.irq,
626 uart.port.iotype, priv->line[i]);
627 break;
628 }
629 }
630 priv->nr = i;
631 pci_set_drvdata(pcidev, priv);
632 return 0;
633 }
634
635 static void exar_pci_remove(struct pci_dev *pcidev)
636 {
637 struct exar8250 *priv = pci_get_drvdata(pcidev);
638 unsigned int i;
639
640 for (i = 0; i < priv->nr; i++)
641 serial8250_unregister_port(priv->line[i]);
642
643 if (priv->board->exit)
644 priv->board->exit(pcidev);
645 }
646
647 static int __maybe_unused exar_suspend(struct device *dev)
648 {
649 struct pci_dev *pcidev = to_pci_dev(dev);
650 struct exar8250 *priv = pci_get_drvdata(pcidev);
651 unsigned int i;
652
653 for (i = 0; i < priv->nr; i++)
654 if (priv->line[i] >= 0)
655 serial8250_suspend_port(priv->line[i]);
656
657 /* Ensure that every init quirk is properly torn down */
658 if (priv->board->exit)
659 priv->board->exit(pcidev);
660
661 return 0;
662 }
663
664 static int __maybe_unused exar_resume(struct device *dev)
665 {
666 struct exar8250 *priv = dev_get_drvdata(dev);
667 unsigned int i;
668
669 exar_misc_clear(priv);
670
671 for (i = 0; i < priv->nr; i++)
672 if (priv->line[i] >= 0)
673 serial8250_resume_port(priv->line[i]);
674
675 return 0;
676 }
677
678 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
679
680 static const struct exar8250_board pbn_fastcom335_2 = {
681 .num_ports = 2,
682 .setup = pci_fastcom335_setup,
683 };
684
685 static const struct exar8250_board pbn_fastcom335_4 = {
686 .num_ports = 4,
687 .setup = pci_fastcom335_setup,
688 };
689
690 static const struct exar8250_board pbn_fastcom335_8 = {
691 .num_ports = 8,
692 .setup = pci_fastcom335_setup,
693 };
694
695 static const struct exar8250_board pbn_connect = {
696 .setup = pci_connect_tech_setup,
697 };
698
699 static const struct exar8250_board pbn_exar_ibm_saturn = {
700 .num_ports = 1,
701 .setup = pci_xr17c154_setup,
702 };
703
704 static const struct exar8250_board pbn_exar_XR17C15x = {
705 .setup = pci_xr17c154_setup,
706 };
707
708 static const struct exar8250_board pbn_exar_XR17V35x = {
709 .setup = pci_xr17v35x_setup,
710 .exit = pci_xr17v35x_exit,
711 };
712
713 static const struct exar8250_board pbn_exar_XR17V4358 = {
714 .num_ports = 12,
715 .setup = pci_xr17v35x_setup,
716 .exit = pci_xr17v35x_exit,
717 };
718
719 static const struct exar8250_board pbn_exar_XR17V8358 = {
720 .num_ports = 16,
721 .setup = pci_xr17v35x_setup,
722 .exit = pci_xr17v35x_exit,
723 };
724
725 #define CONNECT_DEVICE(devid, sdevid, bd) { \
726 PCI_DEVICE_SUB( \
727 PCI_VENDOR_ID_EXAR, \
728 PCI_DEVICE_ID_EXAR_##devid, \
729 PCI_SUBVENDOR_ID_CONNECT_TECH, \
730 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
731 (kernel_ulong_t)&bd \
732 }
733
734 #define EXAR_DEVICE(vend, devid, bd) { \
735 PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd \
736 }
737
738 #define IBM_DEVICE(devid, sdevid, bd) { \
739 PCI_DEVICE_SUB( \
740 PCI_VENDOR_ID_EXAR, \
741 PCI_DEVICE_ID_EXAR_##devid, \
742 PCI_VENDOR_ID_IBM, \
743 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
744 (kernel_ulong_t)&bd \
745 }
746
747 static const struct pci_device_id exar_pci_tbl[] = {
748 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
749 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
750 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
751 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
752 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
753 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
754 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
755 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
756 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
757 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
758 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
759 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
760
761 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
762
763 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
764 EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
765 EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
766 EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
767
768 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
769 EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
770 EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
771 EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
772 EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
773 EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
774 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_exar_XR17V35x),
775 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_exar_XR17V35x),
776 EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_exar_XR17V35x),
777
778 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
779 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
780 EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
781 EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
782 { 0, }
783 };
784 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
785
786 static struct pci_driver exar_pci_driver = {
787 .name = "exar_serial",
788 .probe = exar_pci_probe,
789 .remove = exar_pci_remove,
790 .driver = {
791 .pm = &exar_pci_pm,
792 },
793 .id_table = exar_pci_tbl,
794 };
795 module_pci_driver(exar_pci_driver);
796
797 MODULE_LICENSE("GPL");
798 MODULE_DESCRIPTION("Exar Serial Driver");
799 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
Linux with added FPC-III support