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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_port.c
blob430e3467aff7bf49c221401a39b2968fb8c0e7eb
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Base port operations for 8250/16550-type serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 *
8 * A note about mapbase / membase
9 *
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/sysrq.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/tty.h>
23 #include <linux/ratelimit.h>
24 #include <linux/tty_flip.h>
25 #include <linux/serial.h>
26 #include <linux/serial_8250.h>
27 #include <linux/nmi.h>
28 #include <linux/mutex.h>
29 #include <linux/slab.h>
30 #include <linux/uaccess.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/ktime.h>
33
34 #include <asm/io.h>
35 #include <asm/irq.h>
36
37 #include "8250.h"
38
39 /* Nuvoton NPCM timeout register */
40 #define UART_NPCM_TOR 7
41 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
42
43 /*
44 * Debugging.
45 */
46 #if 0
47 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
48 #else
49 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
50 #endif
51
52 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
53
54 /*
55 * Here we define the default xmit fifo size used for each type of UART.
56 */
57 static const struct serial8250_config uart_config[] = {
58 [PORT_UNKNOWN] = {
59 .name = "unknown",
60 .fifo_size = 1,
61 .tx_loadsz = 1,
62 },
63 [PORT_8250] = {
64 .name = "8250",
65 .fifo_size = 1,
66 .tx_loadsz = 1,
67 },
68 [PORT_16450] = {
69 .name = "16450",
70 .fifo_size = 1,
71 .tx_loadsz = 1,
72 },
73 [PORT_16550] = {
74 .name = "16550",
75 .fifo_size = 1,
76 .tx_loadsz = 1,
77 },
78 [PORT_16550A] = {
79 .name = "16550A",
80 .fifo_size = 16,
81 .tx_loadsz = 16,
82 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
83 .rxtrig_bytes = {1, 4, 8, 14},
84 .flags = UART_CAP_FIFO,
85 },
86 [PORT_CIRRUS] = {
87 .name = "Cirrus",
88 .fifo_size = 1,
89 .tx_loadsz = 1,
90 },
91 [PORT_16650] = {
92 .name = "ST16650",
93 .fifo_size = 1,
94 .tx_loadsz = 1,
95 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
96 },
97 [PORT_16650V2] = {
98 .name = "ST16650V2",
99 .fifo_size = 32,
100 .tx_loadsz = 16,
101 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
102 UART_FCR_T_TRIG_00,
103 .rxtrig_bytes = {8, 16, 24, 28},
104 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
105 },
106 [PORT_16750] = {
107 .name = "TI16750",
108 .fifo_size = 64,
109 .tx_loadsz = 64,
110 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
111 UART_FCR7_64BYTE,
112 .rxtrig_bytes = {1, 16, 32, 56},
113 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
114 },
115 [PORT_STARTECH] = {
116 .name = "Startech",
117 .fifo_size = 1,
118 .tx_loadsz = 1,
119 },
120 [PORT_16C950] = {
121 .name = "16C950/954",
122 .fifo_size = 128,
123 .tx_loadsz = 128,
124 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
125 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
126 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
127 },
128 [PORT_16654] = {
129 .name = "ST16654",
130 .fifo_size = 64,
131 .tx_loadsz = 32,
132 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
133 UART_FCR_T_TRIG_10,
134 .rxtrig_bytes = {8, 16, 56, 60},
135 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
136 },
137 [PORT_16850] = {
138 .name = "XR16850",
139 .fifo_size = 128,
140 .tx_loadsz = 128,
141 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
142 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
143 },
144 [PORT_RSA] = {
145 .name = "RSA",
146 .fifo_size = 2048,
147 .tx_loadsz = 2048,
148 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
149 .flags = UART_CAP_FIFO,
150 },
151 [PORT_NS16550A] = {
152 .name = "NS16550A",
153 .fifo_size = 16,
154 .tx_loadsz = 16,
155 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
156 .flags = UART_CAP_FIFO | UART_NATSEMI,
157 },
158 [PORT_XSCALE] = {
159 .name = "XScale",
160 .fifo_size = 32,
161 .tx_loadsz = 32,
162 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
163 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
164 },
165 [PORT_OCTEON] = {
166 .name = "OCTEON",
167 .fifo_size = 64,
168 .tx_loadsz = 64,
169 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
170 .flags = UART_CAP_FIFO,
171 },
172 [PORT_AR7] = {
173 .name = "AR7",
174 .fifo_size = 16,
175 .tx_loadsz = 16,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
177 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
178 },
179 [PORT_U6_16550A] = {
180 .name = "U6_16550A",
181 .fifo_size = 64,
182 .tx_loadsz = 64,
183 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
184 .flags = UART_CAP_FIFO | UART_CAP_AFE,
185 },
186 [PORT_TEGRA] = {
187 .name = "Tegra",
188 .fifo_size = 32,
189 .tx_loadsz = 8,
190 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
191 UART_FCR_T_TRIG_01,
192 .rxtrig_bytes = {1, 4, 8, 14},
193 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
194 },
195 [PORT_XR17D15X] = {
196 .name = "XR17D15X",
197 .fifo_size = 64,
198 .tx_loadsz = 64,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
201 UART_CAP_SLEEP,
202 },
203 [PORT_XR17V35X] = {
204 .name = "XR17V35X",
205 .fifo_size = 256,
206 .tx_loadsz = 256,
207 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
208 UART_FCR_T_TRIG_11,
209 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
210 UART_CAP_SLEEP,
211 },
212 [PORT_LPC3220] = {
213 .name = "LPC3220",
214 .fifo_size = 64,
215 .tx_loadsz = 32,
216 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
217 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
218 .flags = UART_CAP_FIFO,
219 },
220 [PORT_BRCM_TRUMANAGE] = {
221 .name = "TruManage",
222 .fifo_size = 1,
223 .tx_loadsz = 1024,
224 .flags = UART_CAP_HFIFO,
225 },
226 [PORT_8250_CIR] = {
227 .name = "CIR port"
228 },
229 [PORT_ALTR_16550_F32] = {
230 .name = "Altera 16550 FIFO32",
231 .fifo_size = 32,
232 .tx_loadsz = 32,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
234 .rxtrig_bytes = {1, 8, 16, 30},
235 .flags = UART_CAP_FIFO | UART_CAP_AFE,
236 },
237 [PORT_ALTR_16550_F64] = {
238 .name = "Altera 16550 FIFO64",
239 .fifo_size = 64,
240 .tx_loadsz = 64,
241 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
242 .rxtrig_bytes = {1, 16, 32, 62},
243 .flags = UART_CAP_FIFO | UART_CAP_AFE,
244 },
245 [PORT_ALTR_16550_F128] = {
246 .name = "Altera 16550 FIFO128",
247 .fifo_size = 128,
248 .tx_loadsz = 128,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .rxtrig_bytes = {1, 32, 64, 126},
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
252 },
253 /*
254 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
255 * workaround of errata A-008006 which states that tx_loadsz should
256 * be configured less than Maximum supported fifo bytes.
257 */
258 [PORT_16550A_FSL64] = {
259 .name = "16550A_FSL64",
260 .fifo_size = 64,
261 .tx_loadsz = 63,
262 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
263 UART_FCR7_64BYTE,
264 .flags = UART_CAP_FIFO,
265 },
266 [PORT_RT2880] = {
267 .name = "Palmchip BK-3103",
268 .fifo_size = 16,
269 .tx_loadsz = 16,
270 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
271 .rxtrig_bytes = {1, 4, 8, 14},
272 .flags = UART_CAP_FIFO,
273 },
274 [PORT_DA830] = {
275 .name = "TI DA8xx/66AK2x",
276 .fifo_size = 16,
277 .tx_loadsz = 16,
278 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
279 UART_FCR_R_TRIG_10,
280 .rxtrig_bytes = {1, 4, 8, 14},
281 .flags = UART_CAP_FIFO | UART_CAP_AFE,
282 },
283 [PORT_MTK_BTIF] = {
284 .name = "MediaTek BTIF",
285 .fifo_size = 16,
286 .tx_loadsz = 16,
287 .fcr = UART_FCR_ENABLE_FIFO |
288 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
289 .flags = UART_CAP_FIFO,
290 },
291 [PORT_NPCM] = {
292 .name = "Nuvoton 16550",
293 .fifo_size = 16,
294 .tx_loadsz = 16,
295 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
296 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
297 .rxtrig_bytes = {1, 4, 8, 14},
298 .flags = UART_CAP_FIFO,
299 },
300 [PORT_SUNIX] = {
301 .name = "Sunix",
302 .fifo_size = 128,
303 .tx_loadsz = 128,
304 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
305 .rxtrig_bytes = {1, 32, 64, 112},
306 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
307 },
308 };
309
310 /* Uart divisor latch read */
311 static int default_serial_dl_read(struct uart_8250_port *up)
312 {
313 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
314 }
315
316 /* Uart divisor latch write */
317 static void default_serial_dl_write(struct uart_8250_port *up, int value)
318 {
319 serial_out(up, UART_DLL, value & 0xff);
320 serial_out(up, UART_DLM, value >> 8 & 0xff);
321 }
322
323 #ifdef CONFIG_SERIAL_8250_RT288X
324
325 /* Au1x00/RT288x UART hardware has a weird register layout */
326 static const s8 au_io_in_map[8] = {
327 0, /* UART_RX */
328 2, /* UART_IER */
329 3, /* UART_IIR */
330 5, /* UART_LCR */
331 6, /* UART_MCR */
332 7, /* UART_LSR */
333 8, /* UART_MSR */
334 -1, /* UART_SCR (unmapped) */
335 };
336
337 static const s8 au_io_out_map[8] = {
338 1, /* UART_TX */
339 2, /* UART_IER */
340 4, /* UART_FCR */
341 5, /* UART_LCR */
342 6, /* UART_MCR */
343 -1, /* UART_LSR (unmapped) */
344 -1, /* UART_MSR (unmapped) */
345 -1, /* UART_SCR (unmapped) */
346 };
347
348 unsigned int au_serial_in(struct uart_port *p, int offset)
349 {
350 if (offset >= ARRAY_SIZE(au_io_in_map))
351 return UINT_MAX;
352 offset = au_io_in_map[offset];
353 if (offset < 0)
354 return UINT_MAX;
355 return __raw_readl(p->membase + (offset << p->regshift));
356 }
357
358 void au_serial_out(struct uart_port *p, int offset, int value)
359 {
360 if (offset >= ARRAY_SIZE(au_io_out_map))
361 return;
362 offset = au_io_out_map[offset];
363 if (offset < 0)
364 return;
365 __raw_writel(value, p->membase + (offset << p->regshift));
366 }
367
368 /* Au1x00 haven't got a standard divisor latch */
369 static int au_serial_dl_read(struct uart_8250_port *up)
370 {
371 return __raw_readl(up->port.membase + 0x28);
372 }
373
374 static void au_serial_dl_write(struct uart_8250_port *up, int value)
375 {
376 __raw_writel(value, up->port.membase + 0x28);
377 }
378
379 #endif
380
381 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
382 {
383 offset = offset << p->regshift;
384 outb(p->hub6 - 1 + offset, p->iobase);
385 return inb(p->iobase + 1);
386 }
387
388 static void hub6_serial_out(struct uart_port *p, int offset, int value)
389 {
390 offset = offset << p->regshift;
391 outb(p->hub6 - 1 + offset, p->iobase);
392 outb(value, p->iobase + 1);
393 }
394
395 static unsigned int mem_serial_in(struct uart_port *p, int offset)
396 {
397 offset = offset << p->regshift;
398 return readb(p->membase + offset);
399 }
400
401 static void mem_serial_out(struct uart_port *p, int offset, int value)
402 {
403 offset = offset << p->regshift;
404 writeb(value, p->membase + offset);
405 }
406
407 static void mem16_serial_out(struct uart_port *p, int offset, int value)
408 {
409 offset = offset << p->regshift;
410 writew(value, p->membase + offset);
411 }
412
413 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
414 {
415 offset = offset << p->regshift;
416 return readw(p->membase + offset);
417 }
418
419 static void mem32_serial_out(struct uart_port *p, int offset, int value)
420 {
421 offset = offset << p->regshift;
422 writel(value, p->membase + offset);
423 }
424
425 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
426 {
427 offset = offset << p->regshift;
428 return readl(p->membase + offset);
429 }
430
431 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
432 {
433 offset = offset << p->regshift;
434 iowrite32be(value, p->membase + offset);
435 }
436
437 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
438 {
439 offset = offset << p->regshift;
440 return ioread32be(p->membase + offset);
441 }
442
443 static unsigned int io_serial_in(struct uart_port *p, int offset)
444 {
445 offset = offset << p->regshift;
446 return inb(p->iobase + offset);
447 }
448
449 static void io_serial_out(struct uart_port *p, int offset, int value)
450 {
451 offset = offset << p->regshift;
452 outb(value, p->iobase + offset);
453 }
454
455 static int serial8250_default_handle_irq(struct uart_port *port);
456
457 static void set_io_from_upio(struct uart_port *p)
458 {
459 struct uart_8250_port *up = up_to_u8250p(p);
460
461 up->dl_read = default_serial_dl_read;
462 up->dl_write = default_serial_dl_write;
463
464 switch (p->iotype) {
465 case UPIO_HUB6:
466 p->serial_in = hub6_serial_in;
467 p->serial_out = hub6_serial_out;
468 break;
469
470 case UPIO_MEM:
471 p->serial_in = mem_serial_in;
472 p->serial_out = mem_serial_out;
473 break;
474
475 case UPIO_MEM16:
476 p->serial_in = mem16_serial_in;
477 p->serial_out = mem16_serial_out;
478 break;
479
480 case UPIO_MEM32:
481 p->serial_in = mem32_serial_in;
482 p->serial_out = mem32_serial_out;
483 break;
484
485 case UPIO_MEM32BE:
486 p->serial_in = mem32be_serial_in;
487 p->serial_out = mem32be_serial_out;
488 break;
489
490 #ifdef CONFIG_SERIAL_8250_RT288X
491 case UPIO_AU:
492 p->serial_in = au_serial_in;
493 p->serial_out = au_serial_out;
494 up->dl_read = au_serial_dl_read;
495 up->dl_write = au_serial_dl_write;
496 break;
497 #endif
498
499 default:
500 p->serial_in = io_serial_in;
501 p->serial_out = io_serial_out;
502 break;
503 }
504 /* Remember loaded iotype */
505 up->cur_iotype = p->iotype;
506 p->handle_irq = serial8250_default_handle_irq;
507 }
508
509 static void
510 serial_port_out_sync(struct uart_port *p, int offset, int value)
511 {
512 switch (p->iotype) {
513 case UPIO_MEM:
514 case UPIO_MEM16:
515 case UPIO_MEM32:
516 case UPIO_MEM32BE:
517 case UPIO_AU:
518 p->serial_out(p, offset, value);
519 p->serial_in(p, UART_LCR); /* safe, no side-effects */
520 break;
521 default:
522 p->serial_out(p, offset, value);
523 }
524 }
525
526 /*
527 * For the 16C950
528 */
529 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
530 {
531 serial_out(up, UART_SCR, offset);
532 serial_out(up, UART_ICR, value);
533 }
534
535 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
536 {
537 unsigned int value;
538
539 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
540 serial_out(up, UART_SCR, offset);
541 value = serial_in(up, UART_ICR);
542 serial_icr_write(up, UART_ACR, up->acr);
543
544 return value;
545 }
546
547 /*
548 * FIFO support.
549 */
550 static void serial8250_clear_fifos(struct uart_8250_port *p)
551 {
552 if (p->capabilities & UART_CAP_FIFO) {
553 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
554 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
555 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
556 serial_out(p, UART_FCR, 0);
557 }
558 }
559
560 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
561 {
562 unsigned char mcr = serial8250_in_MCR(p);
563
564 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
565 mcr |= UART_MCR_RTS;
566 else
567 mcr &= ~UART_MCR_RTS;
568 serial8250_out_MCR(p, mcr);
569 }
570
571 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
572 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
573
574 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
575 {
576 serial8250_clear_fifos(p);
577 serial_out(p, UART_FCR, p->fcr);
578 }
579 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
580
581 void serial8250_rpm_get(struct uart_8250_port *p)
582 {
583 if (!(p->capabilities & UART_CAP_RPM))
584 return;
585 pm_runtime_get_sync(p->port.dev);
586 }
587 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
588
589 void serial8250_rpm_put(struct uart_8250_port *p)
590 {
591 if (!(p->capabilities & UART_CAP_RPM))
592 return;
593 pm_runtime_mark_last_busy(p->port.dev);
594 pm_runtime_put_autosuspend(p->port.dev);
595 }
596 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
597
598 /**
599 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
600 * @p: uart_8250_port port instance
601 *
602 * The function is used to start rs485 software emulating on the
603 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
604 * transmission. The function is idempotent, so it is safe to call it
605 * multiple times.
606 *
607 * The caller MUST enable interrupt on empty shift register before
608 * calling serial8250_em485_init(). This interrupt is not a part of
609 * 8250 standard, but implementation defined.
610 *
611 * The function is supposed to be called from .rs485_config callback
612 * or from any other callback protected with p->port.lock spinlock.
613 *
614 * See also serial8250_em485_destroy()
615 *
616 * Return 0 - success, -errno - otherwise
617 */
618 int serial8250_em485_init(struct uart_8250_port *p)
619 {
620 if (p->em485)
621 return 0;
622
623 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
624 if (!p->em485)
625 return -ENOMEM;
626
627 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
628 HRTIMER_MODE_REL);
629 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
630 HRTIMER_MODE_REL);
631 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
632 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
633 p->em485->port = p;
634 p->em485->active_timer = NULL;
635 serial8250_em485_rts_after_send(p);
636
637 return 0;
638 }
639 EXPORT_SYMBOL_GPL(serial8250_em485_init);
640
641 /**
642 * serial8250_em485_destroy() - put uart_8250_port into normal state
643 * @p: uart_8250_port port instance
644 *
645 * The function is used to stop rs485 software emulating on the
646 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
647 * call it multiple times.
648 *
649 * The function is supposed to be called from .rs485_config callback
650 * or from any other callback protected with p->port.lock spinlock.
651 *
652 * See also serial8250_em485_init()
653 */
654 void serial8250_em485_destroy(struct uart_8250_port *p)
655 {
656 if (!p->em485)
657 return;
658
659 hrtimer_cancel(&p->em485->start_tx_timer);
660 hrtimer_cancel(&p->em485->stop_tx_timer);
661
662 kfree(p->em485);
663 p->em485 = NULL;
664 }
665 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
666
667 /*
668 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
669 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
670 * empty and the HW can idle again.
671 */
672 void serial8250_rpm_get_tx(struct uart_8250_port *p)
673 {
674 unsigned char rpm_active;
675
676 if (!(p->capabilities & UART_CAP_RPM))
677 return;
678
679 rpm_active = xchg(&p->rpm_tx_active, 1);
680 if (rpm_active)
681 return;
682 pm_runtime_get_sync(p->port.dev);
683 }
684 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
685
686 void serial8250_rpm_put_tx(struct uart_8250_port *p)
687 {
688 unsigned char rpm_active;
689
690 if (!(p->capabilities & UART_CAP_RPM))
691 return;
692
693 rpm_active = xchg(&p->rpm_tx_active, 0);
694 if (!rpm_active)
695 return;
696 pm_runtime_mark_last_busy(p->port.dev);
697 pm_runtime_put_autosuspend(p->port.dev);
698 }
699 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
700
701 /*
702 * IER sleep support. UARTs which have EFRs need the "extended
703 * capability" bit enabled. Note that on XR16C850s, we need to
704 * reset LCR to write to IER.
705 */
706 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
707 {
708 unsigned char lcr = 0, efr = 0;
709
710 serial8250_rpm_get(p);
711
712 if (p->capabilities & UART_CAP_SLEEP) {
713 if (p->capabilities & UART_CAP_EFR) {
714 lcr = serial_in(p, UART_LCR);
715 efr = serial_in(p, UART_EFR);
716 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
717 serial_out(p, UART_EFR, UART_EFR_ECB);
718 serial_out(p, UART_LCR, 0);
719 }
720 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
721 if (p->capabilities & UART_CAP_EFR) {
722 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
723 serial_out(p, UART_EFR, efr);
724 serial_out(p, UART_LCR, lcr);
725 }
726 }
727
728 serial8250_rpm_put(p);
729 }
730
731 #ifdef CONFIG_SERIAL_8250_RSA
732 /*
733 * Attempts to turn on the RSA FIFO. Returns zero on failure.
734 * We set the port uart clock rate if we succeed.
735 */
736 static int __enable_rsa(struct uart_8250_port *up)
737 {
738 unsigned char mode;
739 int result;
740
741 mode = serial_in(up, UART_RSA_MSR);
742 result = mode & UART_RSA_MSR_FIFO;
743
744 if (!result) {
745 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
746 mode = serial_in(up, UART_RSA_MSR);
747 result = mode & UART_RSA_MSR_FIFO;
748 }
749
750 if (result)
751 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
752
753 return result;
754 }
755
756 static void enable_rsa(struct uart_8250_port *up)
757 {
758 if (up->port.type == PORT_RSA) {
759 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
760 spin_lock_irq(&up->port.lock);
761 __enable_rsa(up);
762 spin_unlock_irq(&up->port.lock);
763 }
764 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
765 serial_out(up, UART_RSA_FRR, 0);
766 }
767 }
768
769 /*
770 * Attempts to turn off the RSA FIFO. Returns zero on failure.
771 * It is unknown why interrupts were disabled in here. However,
772 * the caller is expected to preserve this behaviour by grabbing
773 * the spinlock before calling this function.
774 */
775 static void disable_rsa(struct uart_8250_port *up)
776 {
777 unsigned char mode;
778 int result;
779
780 if (up->port.type == PORT_RSA &&
781 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
782 spin_lock_irq(&up->port.lock);
783
784 mode = serial_in(up, UART_RSA_MSR);
785 result = !(mode & UART_RSA_MSR_FIFO);
786
787 if (!result) {
788 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
789 mode = serial_in(up, UART_RSA_MSR);
790 result = !(mode & UART_RSA_MSR_FIFO);
791 }
792
793 if (result)
794 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
795 spin_unlock_irq(&up->port.lock);
796 }
797 }
798 #endif /* CONFIG_SERIAL_8250_RSA */
799
800 /*
801 * This is a quickie test to see how big the FIFO is.
802 * It doesn't work at all the time, more's the pity.
803 */
804 static int size_fifo(struct uart_8250_port *up)
805 {
806 unsigned char old_fcr, old_mcr, old_lcr;
807 unsigned short old_dl;
808 int count;
809
810 old_lcr = serial_in(up, UART_LCR);
811 serial_out(up, UART_LCR, 0);
812 old_fcr = serial_in(up, UART_FCR);
813 old_mcr = serial8250_in_MCR(up);
814 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
815 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
816 serial8250_out_MCR(up, UART_MCR_LOOP);
817 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
818 old_dl = serial_dl_read(up);
819 serial_dl_write(up, 0x0001);
820 serial_out(up, UART_LCR, 0x03);
821 for (count = 0; count < 256; count++)
822 serial_out(up, UART_TX, count);
823 mdelay(20);/* FIXME - schedule_timeout */
824 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
825 (count < 256); count++)
826 serial_in(up, UART_RX);
827 serial_out(up, UART_FCR, old_fcr);
828 serial8250_out_MCR(up, old_mcr);
829 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
830 serial_dl_write(up, old_dl);
831 serial_out(up, UART_LCR, old_lcr);
832
833 return count;
834 }
835
836 /*
837 * Read UART ID using the divisor method - set DLL and DLM to zero
838 * and the revision will be in DLL and device type in DLM. We
839 * preserve the device state across this.
840 */
841 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
842 {
843 unsigned char old_lcr;
844 unsigned int id, old_dl;
845
846 old_lcr = serial_in(p, UART_LCR);
847 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
848 old_dl = serial_dl_read(p);
849 serial_dl_write(p, 0);
850 id = serial_dl_read(p);
851 serial_dl_write(p, old_dl);
852
853 serial_out(p, UART_LCR, old_lcr);
854
855 return id;
856 }
857
858 /*
859 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
860 * When this function is called we know it is at least a StarTech
861 * 16650 V2, but it might be one of several StarTech UARTs, or one of
862 * its clones. (We treat the broken original StarTech 16650 V1 as a
863 * 16550, and why not? Startech doesn't seem to even acknowledge its
864 * existence.)
865 *
866 * What evil have men's minds wrought...
867 */
868 static void autoconfig_has_efr(struct uart_8250_port *up)
869 {
870 unsigned int id1, id2, id3, rev;
871
872 /*
873 * Everything with an EFR has SLEEP
874 */
875 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
876
877 /*
878 * First we check to see if it's an Oxford Semiconductor UART.
879 *
880 * If we have to do this here because some non-National
881 * Semiconductor clone chips lock up if you try writing to the
882 * LSR register (which serial_icr_read does)
883 */
884
885 /*
886 * Check for Oxford Semiconductor 16C950.
887 *
888 * EFR [4] must be set else this test fails.
889 *
890 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
891 * claims that it's needed for 952 dual UART's (which are not
892 * recommended for new designs).
893 */
894 up->acr = 0;
895 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
896 serial_out(up, UART_EFR, UART_EFR_ECB);
897 serial_out(up, UART_LCR, 0x00);
898 id1 = serial_icr_read(up, UART_ID1);
899 id2 = serial_icr_read(up, UART_ID2);
900 id3 = serial_icr_read(up, UART_ID3);
901 rev = serial_icr_read(up, UART_REV);
902
903 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
904
905 if (id1 == 0x16 && id2 == 0xC9 &&
906 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
907 up->port.type = PORT_16C950;
908
909 /*
910 * Enable work around for the Oxford Semiconductor 952 rev B
911 * chip which causes it to seriously miscalculate baud rates
912 * when DLL is 0.
913 */
914 if (id3 == 0x52 && rev == 0x01)
915 up->bugs |= UART_BUG_QUOT;
916 return;
917 }
918
919 /*
920 * We check for a XR16C850 by setting DLL and DLM to 0, and then
921 * reading back DLL and DLM. The chip type depends on the DLM
922 * value read back:
923 * 0x10 - XR16C850 and the DLL contains the chip revision.
924 * 0x12 - XR16C2850.
925 * 0x14 - XR16C854.
926 */
927 id1 = autoconfig_read_divisor_id(up);
928 DEBUG_AUTOCONF("850id=%04x ", id1);
929
930 id2 = id1 >> 8;
931 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
932 up->port.type = PORT_16850;
933 return;
934 }
935
936 /*
937 * It wasn't an XR16C850.
938 *
939 * We distinguish between the '654 and the '650 by counting
940 * how many bytes are in the FIFO. I'm using this for now,
941 * since that's the technique that was sent to me in the
942 * serial driver update, but I'm not convinced this works.
943 * I've had problems doing this in the past. -TYT
944 */
945 if (size_fifo(up) == 64)
946 up->port.type = PORT_16654;
947 else
948 up->port.type = PORT_16650V2;
949 }
950
951 /*
952 * We detected a chip without a FIFO. Only two fall into
953 * this category - the original 8250 and the 16450. The
954 * 16450 has a scratch register (accessible with LCR=0)
955 */
956 static void autoconfig_8250(struct uart_8250_port *up)
957 {
958 unsigned char scratch, status1, status2;
959
960 up->port.type = PORT_8250;
961
962 scratch = serial_in(up, UART_SCR);
963 serial_out(up, UART_SCR, 0xa5);
964 status1 = serial_in(up, UART_SCR);
965 serial_out(up, UART_SCR, 0x5a);
966 status2 = serial_in(up, UART_SCR);
967 serial_out(up, UART_SCR, scratch);
968
969 if (status1 == 0xa5 && status2 == 0x5a)
970 up->port.type = PORT_16450;
971 }
972
973 static int broken_efr(struct uart_8250_port *up)
974 {
975 /*
976 * Exar ST16C2550 "A2" devices incorrectly detect as
977 * having an EFR, and report an ID of 0x0201. See
978 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
979 */
980 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
981 return 1;
982
983 return 0;
984 }
985
986 /*
987 * We know that the chip has FIFOs. Does it have an EFR? The
988 * EFR is located in the same register position as the IIR and
989 * we know the top two bits of the IIR are currently set. The
990 * EFR should contain zero. Try to read the EFR.
991 */
992 static void autoconfig_16550a(struct uart_8250_port *up)
993 {
994 unsigned char status1, status2;
995 unsigned int iersave;
996
997 up->port.type = PORT_16550A;
998 up->capabilities |= UART_CAP_FIFO;
999
1000 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1001 return;
1002
1003 /*
1004 * Check for presence of the EFR when DLAB is set.
1005 * Only ST16C650V1 UARTs pass this test.
1006 */
1007 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1008 if (serial_in(up, UART_EFR) == 0) {
1009 serial_out(up, UART_EFR, 0xA8);
1010 if (serial_in(up, UART_EFR) != 0) {
1011 DEBUG_AUTOCONF("EFRv1 ");
1012 up->port.type = PORT_16650;
1013 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1014 } else {
1015 serial_out(up, UART_LCR, 0);
1016 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1017 UART_FCR7_64BYTE);
1018 status1 = serial_in(up, UART_IIR) >> 5;
1019 serial_out(up, UART_FCR, 0);
1020 serial_out(up, UART_LCR, 0);
1021
1022 if (status1 == 7)
1023 up->port.type = PORT_16550A_FSL64;
1024 else
1025 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1026 }
1027 serial_out(up, UART_EFR, 0);
1028 return;
1029 }
1030
1031 /*
1032 * Maybe it requires 0xbf to be written to the LCR.
1033 * (other ST16C650V2 UARTs, TI16C752A, etc)
1034 */
1035 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1036 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1037 DEBUG_AUTOCONF("EFRv2 ");
1038 autoconfig_has_efr(up);
1039 return;
1040 }
1041
1042 /*
1043 * Check for a National Semiconductor SuperIO chip.
1044 * Attempt to switch to bank 2, read the value of the LOOP bit
1045 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1046 * switch back to bank 2, read it from EXCR1 again and check
1047 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1048 */
1049 serial_out(up, UART_LCR, 0);
1050 status1 = serial8250_in_MCR(up);
1051 serial_out(up, UART_LCR, 0xE0);
1052 status2 = serial_in(up, 0x02); /* EXCR1 */
1053
1054 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1055 serial_out(up, UART_LCR, 0);
1056 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1057 serial_out(up, UART_LCR, 0xE0);
1058 status2 = serial_in(up, 0x02); /* EXCR1 */
1059 serial_out(up, UART_LCR, 0);
1060 serial8250_out_MCR(up, status1);
1061
1062 if ((status2 ^ status1) & UART_MCR_LOOP) {
1063 unsigned short quot;
1064
1065 serial_out(up, UART_LCR, 0xE0);
1066
1067 quot = serial_dl_read(up);
1068 quot <<= 3;
1069
1070 if (ns16550a_goto_highspeed(up))
1071 serial_dl_write(up, quot);
1072
1073 serial_out(up, UART_LCR, 0);
1074
1075 up->port.uartclk = 921600*16;
1076 up->port.type = PORT_NS16550A;
1077 up->capabilities |= UART_NATSEMI;
1078 return;
1079 }
1080 }
1081
1082 /*
1083 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1084 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1085 * Try setting it with and without DLAB set. Cheap clones
1086 * set bit 5 without DLAB set.
1087 */
1088 serial_out(up, UART_LCR, 0);
1089 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1090 status1 = serial_in(up, UART_IIR) >> 5;
1091 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1092 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1093 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1094 status2 = serial_in(up, UART_IIR) >> 5;
1095 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1096 serial_out(up, UART_LCR, 0);
1097
1098 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1099
1100 if (status1 == 6 && status2 == 7) {
1101 up->port.type = PORT_16750;
1102 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1103 return;
1104 }
1105
1106 /*
1107 * Try writing and reading the UART_IER_UUE bit (b6).
1108 * If it works, this is probably one of the Xscale platform's
1109 * internal UARTs.
1110 * We're going to explicitly set the UUE bit to 0 before
1111 * trying to write and read a 1 just to make sure it's not
1112 * already a 1 and maybe locked there before we even start start.
1113 */
1114 iersave = serial_in(up, UART_IER);
1115 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1116 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1117 /*
1118 * OK it's in a known zero state, try writing and reading
1119 * without disturbing the current state of the other bits.
1120 */
1121 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1122 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1123 /*
1124 * It's an Xscale.
1125 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1126 */
1127 DEBUG_AUTOCONF("Xscale ");
1128 up->port.type = PORT_XSCALE;
1129 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1130 return;
1131 }
1132 } else {
1133 /*
1134 * If we got here we couldn't force the IER_UUE bit to 0.
1135 * Log it and continue.
1136 */
1137 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1138 }
1139 serial_out(up, UART_IER, iersave);
1140
1141 /*
1142 * We distinguish between 16550A and U6 16550A by counting
1143 * how many bytes are in the FIFO.
1144 */
1145 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1146 up->port.type = PORT_U6_16550A;
1147 up->capabilities |= UART_CAP_AFE;
1148 }
1149 }
1150
1151 /*
1152 * This routine is called by rs_init() to initialize a specific serial
1153 * port. It determines what type of UART chip this serial port is
1154 * using: 8250, 16450, 16550, 16550A. The important question is
1155 * whether or not this UART is a 16550A or not, since this will
1156 * determine whether or not we can use its FIFO features or not.
1157 */
1158 static void autoconfig(struct uart_8250_port *up)
1159 {
1160 unsigned char status1, scratch, scratch2, scratch3;
1161 unsigned char save_lcr, save_mcr;
1162 struct uart_port *port = &up->port;
1163 unsigned long flags;
1164 unsigned int old_capabilities;
1165
1166 if (!port->iobase && !port->mapbase && !port->membase)
1167 return;
1168
1169 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1170 port->name, port->iobase, port->membase);
1171
1172 /*
1173 * We really do need global IRQs disabled here - we're going to
1174 * be frobbing the chips IRQ enable register to see if it exists.
1175 */
1176 spin_lock_irqsave(&port->lock, flags);
1177
1178 up->capabilities = 0;
1179 up->bugs = 0;
1180
1181 if (!(port->flags & UPF_BUGGY_UART)) {
1182 /*
1183 * Do a simple existence test first; if we fail this,
1184 * there's no point trying anything else.
1185 *
1186 * 0x80 is used as a nonsense port to prevent against
1187 * false positives due to ISA bus float. The
1188 * assumption is that 0x80 is a non-existent port;
1189 * which should be safe since include/asm/io.h also
1190 * makes this assumption.
1191 *
1192 * Note: this is safe as long as MCR bit 4 is clear
1193 * and the device is in "PC" mode.
1194 */
1195 scratch = serial_in(up, UART_IER);
1196 serial_out(up, UART_IER, 0);
1197 #ifdef __i386__
1198 outb(0xff, 0x080);
1199 #endif
1200 /*
1201 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1202 * 16C754B) allow only to modify them if an EFR bit is set.
1203 */
1204 scratch2 = serial_in(up, UART_IER) & 0x0f;
1205 serial_out(up, UART_IER, 0x0F);
1206 #ifdef __i386__
1207 outb(0, 0x080);
1208 #endif
1209 scratch3 = serial_in(up, UART_IER) & 0x0f;
1210 serial_out(up, UART_IER, scratch);
1211 if (scratch2 != 0 || scratch3 != 0x0F) {
1212 /*
1213 * We failed; there's nothing here
1214 */
1215 spin_unlock_irqrestore(&port->lock, flags);
1216 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1217 scratch2, scratch3);
1218 goto out;
1219 }
1220 }
1221
1222 save_mcr = serial8250_in_MCR(up);
1223 save_lcr = serial_in(up, UART_LCR);
1224
1225 /*
1226 * Check to see if a UART is really there. Certain broken
1227 * internal modems based on the Rockwell chipset fail this
1228 * test, because they apparently don't implement the loopback
1229 * test mode. So this test is skipped on the COM 1 through
1230 * COM 4 ports. This *should* be safe, since no board
1231 * manufacturer would be stupid enough to design a board
1232 * that conflicts with COM 1-4 --- we hope!
1233 */
1234 if (!(port->flags & UPF_SKIP_TEST)) {
1235 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1236 status1 = serial_in(up, UART_MSR) & 0xF0;
1237 serial8250_out_MCR(up, save_mcr);
1238 if (status1 != 0x90) {
1239 spin_unlock_irqrestore(&port->lock, flags);
1240 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1241 status1);
1242 goto out;
1243 }
1244 }
1245
1246 /*
1247 * We're pretty sure there's a port here. Lets find out what
1248 * type of port it is. The IIR top two bits allows us to find
1249 * out if it's 8250 or 16450, 16550, 16550A or later. This
1250 * determines what we test for next.
1251 *
1252 * We also initialise the EFR (if any) to zero for later. The
1253 * EFR occupies the same register location as the FCR and IIR.
1254 */
1255 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1256 serial_out(up, UART_EFR, 0);
1257 serial_out(up, UART_LCR, 0);
1258
1259 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1260 scratch = serial_in(up, UART_IIR) >> 6;
1261
1262 switch (scratch) {
1263 case 0:
1264 autoconfig_8250(up);
1265 break;
1266 case 1:
1267 port->type = PORT_UNKNOWN;
1268 break;
1269 case 2:
1270 port->type = PORT_16550;
1271 break;
1272 case 3:
1273 autoconfig_16550a(up);
1274 break;
1275 }
1276
1277 #ifdef CONFIG_SERIAL_8250_RSA
1278 /*
1279 * Only probe for RSA ports if we got the region.
1280 */
1281 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1282 __enable_rsa(up))
1283 port->type = PORT_RSA;
1284 #endif
1285
1286 serial_out(up, UART_LCR, save_lcr);
1287
1288 port->fifosize = uart_config[up->port.type].fifo_size;
1289 old_capabilities = up->capabilities;
1290 up->capabilities = uart_config[port->type].flags;
1291 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1292
1293 if (port->type == PORT_UNKNOWN)
1294 goto out_lock;
1295
1296 /*
1297 * Reset the UART.
1298 */
1299 #ifdef CONFIG_SERIAL_8250_RSA
1300 if (port->type == PORT_RSA)
1301 serial_out(up, UART_RSA_FRR, 0);
1302 #endif
1303 serial8250_out_MCR(up, save_mcr);
1304 serial8250_clear_fifos(up);
1305 serial_in(up, UART_RX);
1306 if (up->capabilities & UART_CAP_UUE)
1307 serial_out(up, UART_IER, UART_IER_UUE);
1308 else
1309 serial_out(up, UART_IER, 0);
1310
1311 out_lock:
1312 spin_unlock_irqrestore(&port->lock, flags);
1313
1314 /*
1315 * Check if the device is a Fintek F81216A
1316 */
1317 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1318 fintek_8250_probe(up);
1319
1320 if (up->capabilities != old_capabilities) {
1321 pr_warn("%s: detected caps %08x should be %08x\n",
1322 port->name, old_capabilities, up->capabilities);
1323 }
1324 out:
1325 DEBUG_AUTOCONF("iir=%d ", scratch);
1326 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1327 }
1328
1329 static void autoconfig_irq(struct uart_8250_port *up)
1330 {
1331 struct uart_port *port = &up->port;
1332 unsigned char save_mcr, save_ier;
1333 unsigned char save_ICP = 0;
1334 unsigned int ICP = 0;
1335 unsigned long irqs;
1336 int irq;
1337
1338 if (port->flags & UPF_FOURPORT) {
1339 ICP = (port->iobase & 0xfe0) | 0x1f;
1340 save_ICP = inb_p(ICP);
1341 outb_p(0x80, ICP);
1342 inb_p(ICP);
1343 }
1344
1345 if (uart_console(port))
1346 console_lock();
1347
1348 /* forget possible initially masked and pending IRQ */
1349 probe_irq_off(probe_irq_on());
1350 save_mcr = serial8250_in_MCR(up);
1351 save_ier = serial_in(up, UART_IER);
1352 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1353
1354 irqs = probe_irq_on();
1355 serial8250_out_MCR(up, 0);
1356 udelay(10);
1357 if (port->flags & UPF_FOURPORT) {
1358 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1359 } else {
1360 serial8250_out_MCR(up,
1361 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1362 }
1363 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1364 serial_in(up, UART_LSR);
1365 serial_in(up, UART_RX);
1366 serial_in(up, UART_IIR);
1367 serial_in(up, UART_MSR);
1368 serial_out(up, UART_TX, 0xFF);
1369 udelay(20);
1370 irq = probe_irq_off(irqs);
1371
1372 serial8250_out_MCR(up, save_mcr);
1373 serial_out(up, UART_IER, save_ier);
1374
1375 if (port->flags & UPF_FOURPORT)
1376 outb_p(save_ICP, ICP);
1377
1378 if (uart_console(port))
1379 console_unlock();
1380
1381 port->irq = (irq > 0) ? irq : 0;
1382 }
1383
1384 static void serial8250_stop_rx(struct uart_port *port)
1385 {
1386 struct uart_8250_port *up = up_to_u8250p(port);
1387
1388 serial8250_rpm_get(up);
1389
1390 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1391 up->port.read_status_mask &= ~UART_LSR_DR;
1392 serial_port_out(port, UART_IER, up->ier);
1393
1394 serial8250_rpm_put(up);
1395 }
1396
1397 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1398 {
1399 serial8250_em485_rts_after_send(p);
1400
1401 /*
1402 * Empty the RX FIFO, we are not interested in anything
1403 * received during the half-duplex transmission.
1404 * Enable previously disabled RX interrupts.
1405 */
1406 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1407 serial8250_clear_and_reinit_fifos(p);
1408
1409 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1410 serial_port_out(&p->port, UART_IER, p->ier);
1411 }
1412 }
1413 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1414 {
1415 struct uart_8250_em485 *em485;
1416 struct uart_8250_port *p;
1417 unsigned long flags;
1418
1419 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1420 p = em485->port;
1421
1422 serial8250_rpm_get(p);
1423 spin_lock_irqsave(&p->port.lock, flags);
1424 if (em485->active_timer == &em485->stop_tx_timer) {
1425 __do_stop_tx_rs485(p);
1426 em485->active_timer = NULL;
1427 }
1428 spin_unlock_irqrestore(&p->port.lock, flags);
1429 serial8250_rpm_put(p);
1430 return HRTIMER_NORESTART;
1431 }
1432
1433 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1434 {
1435 long sec = msec / 1000;
1436 long nsec = (msec % 1000) * 1000000;
1437 ktime_t t = ktime_set(sec, nsec);
1438
1439 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1440 }
1441
1442 static void __stop_tx_rs485(struct uart_8250_port *p)
1443 {
1444 struct uart_8250_em485 *em485 = p->em485;
1445
1446 /*
1447 * __do_stop_tx_rs485 is going to set RTS according to config
1448 * AND flush RX FIFO if required.
1449 */
1450 if (p->port.rs485.delay_rts_after_send > 0) {
1451 em485->active_timer = &em485->stop_tx_timer;
1452 start_hrtimer_ms(&em485->stop_tx_timer,
1453 p->port.rs485.delay_rts_after_send);
1454 } else {
1455 __do_stop_tx_rs485(p);
1456 }
1457 }
1458
1459 static inline void __do_stop_tx(struct uart_8250_port *p)
1460 {
1461 if (serial8250_clear_THRI(p))
1462 serial8250_rpm_put_tx(p);
1463 }
1464
1465 static inline void __stop_tx(struct uart_8250_port *p)
1466 {
1467 struct uart_8250_em485 *em485 = p->em485;
1468
1469 if (em485) {
1470 unsigned char lsr = serial_in(p, UART_LSR);
1471 /*
1472 * To provide required timeing and allow FIFO transfer,
1473 * __stop_tx_rs485() must be called only when both FIFO and
1474 * shift register are empty. It is for device driver to enable
1475 * interrupt on TEMT.
1476 */
1477 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1478 return;
1479
1480 em485->active_timer = NULL;
1481
1482 __stop_tx_rs485(p);
1483 }
1484 __do_stop_tx(p);
1485 }
1486
1487 static void serial8250_stop_tx(struct uart_port *port)
1488 {
1489 struct uart_8250_port *up = up_to_u8250p(port);
1490
1491 serial8250_rpm_get(up);
1492 __stop_tx(up);
1493
1494 /*
1495 * We really want to stop the transmitter from sending.
1496 */
1497 if (port->type == PORT_16C950) {
1498 up->acr |= UART_ACR_TXDIS;
1499 serial_icr_write(up, UART_ACR, up->acr);
1500 }
1501 serial8250_rpm_put(up);
1502 }
1503
1504 static inline void __start_tx(struct uart_port *port)
1505 {
1506 struct uart_8250_port *up = up_to_u8250p(port);
1507
1508 if (up->dma && !up->dma->tx_dma(up))
1509 return;
1510
1511 if (serial8250_set_THRI(up)) {
1512 if (up->bugs & UART_BUG_TXEN) {
1513 unsigned char lsr;
1514
1515 lsr = serial_in(up, UART_LSR);
1516 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1517 if (lsr & UART_LSR_THRE)
1518 serial8250_tx_chars(up);
1519 }
1520 }
1521
1522 /*
1523 * Re-enable the transmitter if we disabled it.
1524 */
1525 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1526 up->acr &= ~UART_ACR_TXDIS;
1527 serial_icr_write(up, UART_ACR, up->acr);
1528 }
1529 }
1530
1531 static inline void start_tx_rs485(struct uart_port *port)
1532 {
1533 struct uart_8250_port *up = up_to_u8250p(port);
1534 struct uart_8250_em485 *em485 = up->em485;
1535 unsigned char mcr;
1536
1537 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1538 serial8250_stop_rx(&up->port);
1539
1540 em485->active_timer = NULL;
1541
1542 mcr = serial8250_in_MCR(up);
1543 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1544 !!(mcr & UART_MCR_RTS)) {
1545 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1546 mcr |= UART_MCR_RTS;
1547 else
1548 mcr &= ~UART_MCR_RTS;
1549 serial8250_out_MCR(up, mcr);
1550
1551 if (up->port.rs485.delay_rts_before_send > 0) {
1552 em485->active_timer = &em485->start_tx_timer;
1553 start_hrtimer_ms(&em485->start_tx_timer,
1554 up->port.rs485.delay_rts_before_send);
1555 return;
1556 }
1557 }
1558
1559 __start_tx(port);
1560 }
1561
1562 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1563 {
1564 struct uart_8250_em485 *em485;
1565 struct uart_8250_port *p;
1566 unsigned long flags;
1567
1568 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1569 p = em485->port;
1570
1571 spin_lock_irqsave(&p->port.lock, flags);
1572 if (em485->active_timer == &em485->start_tx_timer) {
1573 __start_tx(&p->port);
1574 em485->active_timer = NULL;
1575 }
1576 spin_unlock_irqrestore(&p->port.lock, flags);
1577 return HRTIMER_NORESTART;
1578 }
1579
1580 static void serial8250_start_tx(struct uart_port *port)
1581 {
1582 struct uart_8250_port *up = up_to_u8250p(port);
1583 struct uart_8250_em485 *em485 = up->em485;
1584
1585 serial8250_rpm_get_tx(up);
1586
1587 if (em485 &&
1588 em485->active_timer == &em485->start_tx_timer)
1589 return;
1590
1591 if (em485)
1592 start_tx_rs485(port);
1593 else
1594 __start_tx(port);
1595 }
1596
1597 static void serial8250_throttle(struct uart_port *port)
1598 {
1599 port->throttle(port);
1600 }
1601
1602 static void serial8250_unthrottle(struct uart_port *port)
1603 {
1604 port->unthrottle(port);
1605 }
1606
1607 static void serial8250_disable_ms(struct uart_port *port)
1608 {
1609 struct uart_8250_port *up = up_to_u8250p(port);
1610
1611 /* no MSR capabilities */
1612 if (up->bugs & UART_BUG_NOMSR)
1613 return;
1614
1615 mctrl_gpio_disable_ms(up->gpios);
1616
1617 up->ier &= ~UART_IER_MSI;
1618 serial_port_out(port, UART_IER, up->ier);
1619 }
1620
1621 static void serial8250_enable_ms(struct uart_port *port)
1622 {
1623 struct uart_8250_port *up = up_to_u8250p(port);
1624
1625 /* no MSR capabilities */
1626 if (up->bugs & UART_BUG_NOMSR)
1627 return;
1628
1629 mctrl_gpio_enable_ms(up->gpios);
1630
1631 up->ier |= UART_IER_MSI;
1632
1633 serial8250_rpm_get(up);
1634 serial_port_out(port, UART_IER, up->ier);
1635 serial8250_rpm_put(up);
1636 }
1637
1638 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1639 {
1640 struct uart_port *port = &up->port;
1641 unsigned char ch;
1642 char flag = TTY_NORMAL;
1643
1644 if (likely(lsr & UART_LSR_DR))
1645 ch = serial_in(up, UART_RX);
1646 else
1647 /*
1648 * Intel 82571 has a Serial Over Lan device that will
1649 * set UART_LSR_BI without setting UART_LSR_DR when
1650 * it receives a break. To avoid reading from the
1651 * receive buffer without UART_LSR_DR bit set, we
1652 * just force the read character to be 0
1653 */
1654 ch = 0;
1655
1656 port->icount.rx++;
1657
1658 lsr |= up->lsr_saved_flags;
1659 up->lsr_saved_flags = 0;
1660
1661 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1662 if (lsr & UART_LSR_BI) {
1663 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1664 port->icount.brk++;
1665 /*
1666 * We do the SysRQ and SAK checking
1667 * here because otherwise the break
1668 * may get masked by ignore_status_mask
1669 * or read_status_mask.
1670 */
1671 if (uart_handle_break(port))
1672 return;
1673 } else if (lsr & UART_LSR_PE)
1674 port->icount.parity++;
1675 else if (lsr & UART_LSR_FE)
1676 port->icount.frame++;
1677 if (lsr & UART_LSR_OE)
1678 port->icount.overrun++;
1679
1680 /*
1681 * Mask off conditions which should be ignored.
1682 */
1683 lsr &= port->read_status_mask;
1684
1685 if (lsr & UART_LSR_BI) {
1686 pr_debug("%s: handling break\n", __func__);
1687 flag = TTY_BREAK;
1688 } else if (lsr & UART_LSR_PE)
1689 flag = TTY_PARITY;
1690 else if (lsr & UART_LSR_FE)
1691 flag = TTY_FRAME;
1692 }
1693 if (uart_prepare_sysrq_char(port, ch))
1694 return;
1695
1696 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1697 }
1698 EXPORT_SYMBOL_GPL(serial8250_read_char);
1699
1700 /*
1701 * serial8250_rx_chars: processes according to the passed in LSR
1702 * value, and returns the remaining LSR bits not handled
1703 * by this Rx routine.
1704 */
1705 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1706 {
1707 struct uart_port *port = &up->port;
1708 int max_count = 256;
1709
1710 do {
1711 serial8250_read_char(up, lsr);
1712 if (--max_count == 0)
1713 break;
1714 lsr = serial_in(up, UART_LSR);
1715 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1716
1717 tty_flip_buffer_push(&port->state->port);
1718 return lsr;
1719 }
1720 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1721
1722 void serial8250_tx_chars(struct uart_8250_port *up)
1723 {
1724 struct uart_port *port = &up->port;
1725 struct circ_buf *xmit = &port->state->xmit;
1726 int count;
1727
1728 if (port->x_char) {
1729 serial_out(up, UART_TX, port->x_char);
1730 port->icount.tx++;
1731 port->x_char = 0;
1732 return;
1733 }
1734 if (uart_tx_stopped(port)) {
1735 serial8250_stop_tx(port);
1736 return;
1737 }
1738 if (uart_circ_empty(xmit)) {
1739 __stop_tx(up);
1740 return;
1741 }
1742
1743 count = up->tx_loadsz;
1744 do {
1745 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1746 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1747 port->icount.tx++;
1748 if (uart_circ_empty(xmit))
1749 break;
1750 if ((up->capabilities & UART_CAP_HFIFO) &&
1751 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1752 break;
1753 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1754 if ((up->capabilities & UART_CAP_MINI) &&
1755 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1756 break;
1757 } while (--count > 0);
1758
1759 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1760 uart_write_wakeup(port);
1761
1762 /*
1763 * With RPM enabled, we have to wait until the FIFO is empty before the
1764 * HW can go idle. So we get here once again with empty FIFO and disable
1765 * the interrupt and RPM in __stop_tx()
1766 */
1767 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1768 __stop_tx(up);
1769 }
1770 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1771
1772 /* Caller holds uart port lock */
1773 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1774 {
1775 struct uart_port *port = &up->port;
1776 unsigned int status = serial_in(up, UART_MSR);
1777
1778 status |= up->msr_saved_flags;
1779 up->msr_saved_flags = 0;
1780 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1781 port->state != NULL) {
1782 if (status & UART_MSR_TERI)
1783 port->icount.rng++;
1784 if (status & UART_MSR_DDSR)
1785 port->icount.dsr++;
1786 if (status & UART_MSR_DDCD)
1787 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1788 if (status & UART_MSR_DCTS)
1789 uart_handle_cts_change(port, status & UART_MSR_CTS);
1790
1791 wake_up_interruptible(&port->state->port.delta_msr_wait);
1792 }
1793
1794 return status;
1795 }
1796 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1797
1798 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1799 {
1800 switch (iir & 0x3f) {
1801 case UART_IIR_RX_TIMEOUT:
1802 serial8250_rx_dma_flush(up);
1803 /* fall-through */
1804 case UART_IIR_RLSI:
1805 return true;
1806 }
1807 return up->dma->rx_dma(up);
1808 }
1809
1810 /*
1811 * This handles the interrupt from one port.
1812 */
1813 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1814 {
1815 unsigned char status;
1816 unsigned long flags;
1817 struct uart_8250_port *up = up_to_u8250p(port);
1818
1819 if (iir & UART_IIR_NO_INT)
1820 return 0;
1821
1822 spin_lock_irqsave(&port->lock, flags);
1823
1824 status = serial_port_in(port, UART_LSR);
1825
1826 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1827 if (!up->dma || handle_rx_dma(up, iir))
1828 status = serial8250_rx_chars(up, status);
1829 }
1830 serial8250_modem_status(up);
1831 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1832 (up->ier & UART_IER_THRI))
1833 serial8250_tx_chars(up);
1834
1835 uart_unlock_and_check_sysrq(port, flags);
1836 return 1;
1837 }
1838 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1839
1840 static int serial8250_default_handle_irq(struct uart_port *port)
1841 {
1842 struct uart_8250_port *up = up_to_u8250p(port);
1843 unsigned int iir;
1844 int ret;
1845
1846 serial8250_rpm_get(up);
1847
1848 iir = serial_port_in(port, UART_IIR);
1849 ret = serial8250_handle_irq(port, iir);
1850
1851 serial8250_rpm_put(up);
1852 return ret;
1853 }
1854
1855 /*
1856 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1857 * have a programmable TX threshold that triggers the THRE interrupt in
1858 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1859 * has space available. Load it up with tx_loadsz bytes.
1860 */
1861 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1862 {
1863 unsigned long flags;
1864 unsigned int iir = serial_port_in(port, UART_IIR);
1865
1866 /* TX Threshold IRQ triggered so load up FIFO */
1867 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1868 struct uart_8250_port *up = up_to_u8250p(port);
1869
1870 spin_lock_irqsave(&port->lock, flags);
1871 serial8250_tx_chars(up);
1872 spin_unlock_irqrestore(&port->lock, flags);
1873 }
1874
1875 iir = serial_port_in(port, UART_IIR);
1876 return serial8250_handle_irq(port, iir);
1877 }
1878
1879 static unsigned int serial8250_tx_empty(struct uart_port *port)
1880 {
1881 struct uart_8250_port *up = up_to_u8250p(port);
1882 unsigned long flags;
1883 unsigned int lsr;
1884
1885 serial8250_rpm_get(up);
1886
1887 spin_lock_irqsave(&port->lock, flags);
1888 lsr = serial_port_in(port, UART_LSR);
1889 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1890 spin_unlock_irqrestore(&port->lock, flags);
1891
1892 serial8250_rpm_put(up);
1893
1894 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1895 }
1896
1897 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1898 {
1899 struct uart_8250_port *up = up_to_u8250p(port);
1900 unsigned int status;
1901 unsigned int val;
1902
1903 serial8250_rpm_get(up);
1904 status = serial8250_modem_status(up);
1905 serial8250_rpm_put(up);
1906
1907 val = serial8250_MSR_to_TIOCM(status);
1908 if (up->gpios)
1909 return mctrl_gpio_get(up->gpios, &val);
1910
1911 return val;
1912 }
1913 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1914
1915 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1916 {
1917 if (port->get_mctrl)
1918 return port->get_mctrl(port);
1919 return serial8250_do_get_mctrl(port);
1920 }
1921
1922 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1923 {
1924 struct uart_8250_port *up = up_to_u8250p(port);
1925 unsigned char mcr;
1926
1927 mcr = serial8250_TIOCM_to_MCR(mctrl);
1928
1929 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1930
1931 serial8250_out_MCR(up, mcr);
1932 }
1933 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1934
1935 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1936 {
1937 if (port->set_mctrl)
1938 port->set_mctrl(port, mctrl);
1939 else
1940 serial8250_do_set_mctrl(port, mctrl);
1941 }
1942
1943 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1944 {
1945 struct uart_8250_port *up = up_to_u8250p(port);
1946 unsigned long flags;
1947
1948 serial8250_rpm_get(up);
1949 spin_lock_irqsave(&port->lock, flags);
1950 if (break_state == -1)
1951 up->lcr |= UART_LCR_SBC;
1952 else
1953 up->lcr &= ~UART_LCR_SBC;
1954 serial_port_out(port, UART_LCR, up->lcr);
1955 spin_unlock_irqrestore(&port->lock, flags);
1956 serial8250_rpm_put(up);
1957 }
1958
1959 /*
1960 * Wait for transmitter & holding register to empty
1961 */
1962 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1963 {
1964 unsigned int status, tmout = 10000;
1965
1966 /* Wait up to 10ms for the character(s) to be sent. */
1967 for (;;) {
1968 status = serial_in(up, UART_LSR);
1969
1970 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1971
1972 if ((status & bits) == bits)
1973 break;
1974 if (--tmout == 0)
1975 break;
1976 udelay(1);
1977 touch_nmi_watchdog();
1978 }
1979
1980 /* Wait up to 1s for flow control if necessary */
1981 if (up->port.flags & UPF_CONS_FLOW) {
1982 for (tmout = 1000000; tmout; tmout--) {
1983 unsigned int msr = serial_in(up, UART_MSR);
1984 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1985 if (msr & UART_MSR_CTS)
1986 break;
1987 udelay(1);
1988 touch_nmi_watchdog();
1989 }
1990 }
1991 }
1992
1993 #ifdef CONFIG_CONSOLE_POLL
1994 /*
1995 * Console polling routines for writing and reading from the uart while
1996 * in an interrupt or debug context.
1997 */
1998
1999 static int serial8250_get_poll_char(struct uart_port *port)
2000 {
2001 struct uart_8250_port *up = up_to_u8250p(port);
2002 unsigned char lsr;
2003 int status;
2004
2005 serial8250_rpm_get(up);
2006
2007 lsr = serial_port_in(port, UART_LSR);
2008
2009 if (!(lsr & UART_LSR_DR)) {
2010 status = NO_POLL_CHAR;
2011 goto out;
2012 }
2013
2014 status = serial_port_in(port, UART_RX);
2015 out:
2016 serial8250_rpm_put(up);
2017 return status;
2018 }
2019
2020
2021 static void serial8250_put_poll_char(struct uart_port *port,
2022 unsigned char c)
2023 {
2024 unsigned int ier;
2025 struct uart_8250_port *up = up_to_u8250p(port);
2026
2027 serial8250_rpm_get(up);
2028 /*
2029 * First save the IER then disable the interrupts
2030 */
2031 ier = serial_port_in(port, UART_IER);
2032 if (up->capabilities & UART_CAP_UUE)
2033 serial_port_out(port, UART_IER, UART_IER_UUE);
2034 else
2035 serial_port_out(port, UART_IER, 0);
2036
2037 wait_for_xmitr(up, BOTH_EMPTY);
2038 /*
2039 * Send the character out.
2040 */
2041 serial_port_out(port, UART_TX, c);
2042
2043 /*
2044 * Finally, wait for transmitter to become empty
2045 * and restore the IER
2046 */
2047 wait_for_xmitr(up, BOTH_EMPTY);
2048 serial_port_out(port, UART_IER, ier);
2049 serial8250_rpm_put(up);
2050 }
2051
2052 #endif /* CONFIG_CONSOLE_POLL */
2053
2054 int serial8250_do_startup(struct uart_port *port)
2055 {
2056 struct uart_8250_port *up = up_to_u8250p(port);
2057 unsigned long flags;
2058 unsigned char lsr, iir;
2059 int retval;
2060
2061 if (!port->fifosize)
2062 port->fifosize = uart_config[port->type].fifo_size;
2063 if (!up->tx_loadsz)
2064 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2065 if (!up->capabilities)
2066 up->capabilities = uart_config[port->type].flags;
2067 up->mcr = 0;
2068
2069 if (port->iotype != up->cur_iotype)
2070 set_io_from_upio(port);
2071
2072 serial8250_rpm_get(up);
2073 if (port->type == PORT_16C950) {
2074 /* Wake up and initialize UART */
2075 up->acr = 0;
2076 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2077 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2078 serial_port_out(port, UART_IER, 0);
2079 serial_port_out(port, UART_LCR, 0);
2080 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2081 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2082 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2083 serial_port_out(port, UART_LCR, 0);
2084 }
2085
2086 if (port->type == PORT_DA830) {
2087 /* Reset the port */
2088 serial_port_out(port, UART_IER, 0);
2089 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2090 mdelay(10);
2091
2092 /* Enable Tx, Rx and free run mode */
2093 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2094 UART_DA830_PWREMU_MGMT_UTRST |
2095 UART_DA830_PWREMU_MGMT_URRST |
2096 UART_DA830_PWREMU_MGMT_FREE);
2097 }
2098
2099 if (port->type == PORT_NPCM) {
2100 /*
2101 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2102 * register). Enable it, and set TIOC (timeout interrupt
2103 * comparator) to be 0x20 for correct operation.
2104 */
2105 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2106 }
2107
2108 #ifdef CONFIG_SERIAL_8250_RSA
2109 /*
2110 * If this is an RSA port, see if we can kick it up to the
2111 * higher speed clock.
2112 */
2113 enable_rsa(up);
2114 #endif
2115
2116 /*
2117 * Clear the FIFO buffers and disable them.
2118 * (they will be reenabled in set_termios())
2119 */
2120 serial8250_clear_fifos(up);
2121
2122 /*
2123 * Clear the interrupt registers.
2124 */
2125 serial_port_in(port, UART_LSR);
2126 serial_port_in(port, UART_RX);
2127 serial_port_in(port, UART_IIR);
2128 serial_port_in(port, UART_MSR);
2129
2130 /*
2131 * At this point, there's no way the LSR could still be 0xff;
2132 * if it is, then bail out, because there's likely no UART
2133 * here.
2134 */
2135 if (!(port->flags & UPF_BUGGY_UART) &&
2136 (serial_port_in(port, UART_LSR) == 0xff)) {
2137 pr_info_ratelimited("%s: LSR safety check engaged!\n", port->name);
2138 retval = -ENODEV;
2139 goto out;
2140 }
2141
2142 /*
2143 * For a XR16C850, we need to set the trigger levels
2144 */
2145 if (port->type == PORT_16850) {
2146 unsigned char fctr;
2147
2148 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2149
2150 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2151 serial_port_out(port, UART_FCTR,
2152 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2153 serial_port_out(port, UART_TRG, UART_TRG_96);
2154 serial_port_out(port, UART_FCTR,
2155 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2156 serial_port_out(port, UART_TRG, UART_TRG_96);
2157
2158 serial_port_out(port, UART_LCR, 0);
2159 }
2160
2161 /*
2162 * For the Altera 16550 variants, set TX threshold trigger level.
2163 */
2164 if (((port->type == PORT_ALTR_16550_F32) ||
2165 (port->type == PORT_ALTR_16550_F64) ||
2166 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2167 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2168 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2169 pr_err("%s TX FIFO Threshold errors, skipping\n",
2170 port->name);
2171 } else {
2172 serial_port_out(port, UART_ALTR_AFR,
2173 UART_ALTR_EN_TXFIFO_LW);
2174 serial_port_out(port, UART_ALTR_TX_LOW,
2175 port->fifosize - up->tx_loadsz);
2176 port->handle_irq = serial8250_tx_threshold_handle_irq;
2177 }
2178 }
2179
2180 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2181 unsigned char iir1;
2182 /*
2183 * Test for UARTs that do not reassert THRE when the
2184 * transmitter is idle and the interrupt has already
2185 * been cleared. Real 16550s should always reassert
2186 * this interrupt whenever the transmitter is idle and
2187 * the interrupt is enabled. Delays are necessary to
2188 * allow register changes to become visible.
2189 */
2190 spin_lock_irqsave(&port->lock, flags);
2191 if (up->port.irqflags & IRQF_SHARED)
2192 disable_irq_nosync(port->irq);
2193
2194 wait_for_xmitr(up, UART_LSR_THRE);
2195 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2196 udelay(1); /* allow THRE to set */
2197 iir1 = serial_port_in(port, UART_IIR);
2198 serial_port_out(port, UART_IER, 0);
2199 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2200 udelay(1); /* allow a working UART time to re-assert THRE */
2201 iir = serial_port_in(port, UART_IIR);
2202 serial_port_out(port, UART_IER, 0);
2203
2204 if (port->irqflags & IRQF_SHARED)
2205 enable_irq(port->irq);
2206 spin_unlock_irqrestore(&port->lock, flags);
2207
2208 /*
2209 * If the interrupt is not reasserted, or we otherwise
2210 * don't trust the iir, setup a timer to kick the UART
2211 * on a regular basis.
2212 */
2213 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2214 up->port.flags & UPF_BUG_THRE) {
2215 up->bugs |= UART_BUG_THRE;
2216 }
2217 }
2218
2219 retval = up->ops->setup_irq(up);
2220 if (retval)
2221 goto out;
2222
2223 /*
2224 * Now, initialize the UART
2225 */
2226 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2227
2228 spin_lock_irqsave(&port->lock, flags);
2229 if (up->port.flags & UPF_FOURPORT) {
2230 if (!up->port.irq)
2231 up->port.mctrl |= TIOCM_OUT1;
2232 } else
2233 /*
2234 * Most PC uarts need OUT2 raised to enable interrupts.
2235 */
2236 if (port->irq)
2237 up->port.mctrl |= TIOCM_OUT2;
2238
2239 serial8250_set_mctrl(port, port->mctrl);
2240
2241 /*
2242 * Serial over Lan (SoL) hack:
2243 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2244 * used for Serial Over Lan. Those chips take a longer time than a
2245 * normal serial device to signalize that a transmission data was
2246 * queued. Due to that, the above test generally fails. One solution
2247 * would be to delay the reading of iir. However, this is not
2248 * reliable, since the timeout is variable. So, let's just don't
2249 * test if we receive TX irq. This way, we'll never enable
2250 * UART_BUG_TXEN.
2251 */
2252 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2253 goto dont_test_tx_en;
2254
2255 /*
2256 * Do a quick test to see if we receive an interrupt when we enable
2257 * the TX irq.
2258 */
2259 serial_port_out(port, UART_IER, UART_IER_THRI);
2260 lsr = serial_port_in(port, UART_LSR);
2261 iir = serial_port_in(port, UART_IIR);
2262 serial_port_out(port, UART_IER, 0);
2263
2264 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2265 if (!(up->bugs & UART_BUG_TXEN)) {
2266 up->bugs |= UART_BUG_TXEN;
2267 pr_debug("%s - enabling bad tx status workarounds\n",
2268 port->name);
2269 }
2270 } else {
2271 up->bugs &= ~UART_BUG_TXEN;
2272 }
2273
2274 dont_test_tx_en:
2275 spin_unlock_irqrestore(&port->lock, flags);
2276
2277 /*
2278 * Clear the interrupt registers again for luck, and clear the
2279 * saved flags to avoid getting false values from polling
2280 * routines or the previous session.
2281 */
2282 serial_port_in(port, UART_LSR);
2283 serial_port_in(port, UART_RX);
2284 serial_port_in(port, UART_IIR);
2285 serial_port_in(port, UART_MSR);
2286 up->lsr_saved_flags = 0;
2287 up->msr_saved_flags = 0;
2288
2289 /*
2290 * Request DMA channels for both RX and TX.
2291 */
2292 if (up->dma) {
2293 retval = serial8250_request_dma(up);
2294 if (retval) {
2295 pr_warn_ratelimited("%s - failed to request DMA\n",
2296 port->name);
2297 up->dma = NULL;
2298 }
2299 }
2300
2301 /*
2302 * Set the IER shadow for rx interrupts but defer actual interrupt
2303 * enable until after the FIFOs are enabled; otherwise, an already-
2304 * active sender can swamp the interrupt handler with "too much work".
2305 */
2306 up->ier = UART_IER_RLSI | UART_IER_RDI;
2307
2308 if (port->flags & UPF_FOURPORT) {
2309 unsigned int icp;
2310 /*
2311 * Enable interrupts on the AST Fourport board
2312 */
2313 icp = (port->iobase & 0xfe0) | 0x01f;
2314 outb_p(0x80, icp);
2315 inb_p(icp);
2316 }
2317 retval = 0;
2318 out:
2319 serial8250_rpm_put(up);
2320 return retval;
2321 }
2322 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2323
2324 static int serial8250_startup(struct uart_port *port)
2325 {
2326 if (port->startup)
2327 return port->startup(port);
2328 return serial8250_do_startup(port);
2329 }
2330
2331 void serial8250_do_shutdown(struct uart_port *port)
2332 {
2333 struct uart_8250_port *up = up_to_u8250p(port);
2334 unsigned long flags;
2335
2336 serial8250_rpm_get(up);
2337 /*
2338 * Disable interrupts from this port
2339 */
2340 spin_lock_irqsave(&port->lock, flags);
2341 up->ier = 0;
2342 serial_port_out(port, UART_IER, 0);
2343 spin_unlock_irqrestore(&port->lock, flags);
2344
2345 synchronize_irq(port->irq);
2346
2347 if (up->dma)
2348 serial8250_release_dma(up);
2349
2350 spin_lock_irqsave(&port->lock, flags);
2351 if (port->flags & UPF_FOURPORT) {
2352 /* reset interrupts on the AST Fourport board */
2353 inb((port->iobase & 0xfe0) | 0x1f);
2354 port->mctrl |= TIOCM_OUT1;
2355 } else
2356 port->mctrl &= ~TIOCM_OUT2;
2357
2358 serial8250_set_mctrl(port, port->mctrl);
2359 spin_unlock_irqrestore(&port->lock, flags);
2360
2361 /*
2362 * Disable break condition and FIFOs
2363 */
2364 serial_port_out(port, UART_LCR,
2365 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2366 serial8250_clear_fifos(up);
2367
2368 #ifdef CONFIG_SERIAL_8250_RSA
2369 /*
2370 * Reset the RSA board back to 115kbps compat mode.
2371 */
2372 disable_rsa(up);
2373 #endif
2374
2375 /*
2376 * Read data port to reset things, and then unlink from
2377 * the IRQ chain.
2378 */
2379 serial_port_in(port, UART_RX);
2380 serial8250_rpm_put(up);
2381
2382 up->ops->release_irq(up);
2383 }
2384 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2385
2386 static void serial8250_shutdown(struct uart_port *port)
2387 {
2388 if (port->shutdown)
2389 port->shutdown(port);
2390 else
2391 serial8250_do_shutdown(port);
2392 }
2393
2394 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2395 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2396 unsigned int baud)
2397 {
2398 struct uart_port *port = &up->port;
2399
2400 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2401 }
2402
2403 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2404 unsigned int baud,
2405 unsigned int *frac)
2406 {
2407 struct uart_8250_port *up = up_to_u8250p(port);
2408 unsigned int quot;
2409
2410 /*
2411 * Handle magic divisors for baud rates above baud_base on
2412 * SMSC SuperIO chips.
2413 *
2414 */
2415 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2416 baud == (port->uartclk/4))
2417 quot = 0x8001;
2418 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2419 baud == (port->uartclk/8))
2420 quot = 0x8002;
2421 else if (up->port.type == PORT_NPCM)
2422 quot = npcm_get_divisor(up, baud);
2423 else
2424 quot = uart_get_divisor(port, baud);
2425
2426 /*
2427 * Oxford Semi 952 rev B workaround
2428 */
2429 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2430 quot++;
2431
2432 return quot;
2433 }
2434
2435 static unsigned int serial8250_get_divisor(struct uart_port *port,
2436 unsigned int baud,
2437 unsigned int *frac)
2438 {
2439 if (port->get_divisor)
2440 return port->get_divisor(port, baud, frac);
2441
2442 return serial8250_do_get_divisor(port, baud, frac);
2443 }
2444
2445 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2446 tcflag_t c_cflag)
2447 {
2448 unsigned char cval;
2449
2450 switch (c_cflag & CSIZE) {
2451 case CS5:
2452 cval = UART_LCR_WLEN5;
2453 break;
2454 case CS6:
2455 cval = UART_LCR_WLEN6;
2456 break;
2457 case CS7:
2458 cval = UART_LCR_WLEN7;
2459 break;
2460 default:
2461 case CS8:
2462 cval = UART_LCR_WLEN8;
2463 break;
2464 }
2465
2466 if (c_cflag & CSTOPB)
2467 cval |= UART_LCR_STOP;
2468 if (c_cflag & PARENB) {
2469 cval |= UART_LCR_PARITY;
2470 if (up->bugs & UART_BUG_PARITY)
2471 up->fifo_bug = true;
2472 }
2473 if (!(c_cflag & PARODD))
2474 cval |= UART_LCR_EPAR;
2475 #ifdef CMSPAR
2476 if (c_cflag & CMSPAR)
2477 cval |= UART_LCR_SPAR;
2478 #endif
2479
2480 return cval;
2481 }
2482
2483 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2484 unsigned int quot, unsigned int quot_frac)
2485 {
2486 struct uart_8250_port *up = up_to_u8250p(port);
2487
2488 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2489 if (is_omap1510_8250(up)) {
2490 if (baud == 115200) {
2491 quot = 1;
2492 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2493 } else
2494 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2495 }
2496
2497 /*
2498 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2499 * otherwise just set DLAB
2500 */
2501 if (up->capabilities & UART_NATSEMI)
2502 serial_port_out(port, UART_LCR, 0xe0);
2503 else
2504 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2505
2506 serial_dl_write(up, quot);
2507 }
2508 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2509
2510 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2511 unsigned int quot, unsigned int quot_frac)
2512 {
2513 if (port->set_divisor)
2514 port->set_divisor(port, baud, quot, quot_frac);
2515 else
2516 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2517 }
2518
2519 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2520 struct ktermios *termios,
2521 struct ktermios *old)
2522 {
2523 /*
2524 * Ask the core to calculate the divisor for us.
2525 * Allow 1% tolerance at the upper limit so uart clks marginally
2526 * slower than nominal still match standard baud rates without
2527 * causing transmission errors.
2528 */
2529 return uart_get_baud_rate(port, termios, old,
2530 port->uartclk / 16 / UART_DIV_MAX,
2531 port->uartclk);
2532 }
2533
2534 void
2535 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2536 struct ktermios *old)
2537 {
2538 struct uart_8250_port *up = up_to_u8250p(port);
2539 unsigned char cval;
2540 unsigned long flags;
2541 unsigned int baud, quot, frac = 0;
2542
2543 if (up->capabilities & UART_CAP_MINI) {
2544 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2545 if ((termios->c_cflag & CSIZE) == CS5 ||
2546 (termios->c_cflag & CSIZE) == CS6)
2547 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2548 }
2549 cval = serial8250_compute_lcr(up, termios->c_cflag);
2550
2551 baud = serial8250_get_baud_rate(port, termios, old);
2552 quot = serial8250_get_divisor(port, baud, &frac);
2553
2554 /*
2555 * Ok, we're now changing the port state. Do it with
2556 * interrupts disabled.
2557 */
2558 serial8250_rpm_get(up);
2559 spin_lock_irqsave(&port->lock, flags);
2560
2561 up->lcr = cval; /* Save computed LCR */
2562
2563 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2564 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2565 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2566 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2567 up->fcr |= UART_FCR_TRIGGER_1;
2568 }
2569 }
2570
2571 /*
2572 * MCR-based auto flow control. When AFE is enabled, RTS will be
2573 * deasserted when the receive FIFO contains more characters than
2574 * the trigger, or the MCR RTS bit is cleared.
2575 */
2576 if (up->capabilities & UART_CAP_AFE) {
2577 up->mcr &= ~UART_MCR_AFE;
2578 if (termios->c_cflag & CRTSCTS)
2579 up->mcr |= UART_MCR_AFE;
2580 }
2581
2582 /*
2583 * Update the per-port timeout.
2584 */
2585 uart_update_timeout(port, termios->c_cflag, baud);
2586
2587 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2588 if (termios->c_iflag & INPCK)
2589 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2590 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2591 port->read_status_mask |= UART_LSR_BI;
2592
2593 /*
2594 * Characteres to ignore
2595 */
2596 port->ignore_status_mask = 0;
2597 if (termios->c_iflag & IGNPAR)
2598 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2599 if (termios->c_iflag & IGNBRK) {
2600 port->ignore_status_mask |= UART_LSR_BI;
2601 /*
2602 * If we're ignoring parity and break indicators,
2603 * ignore overruns too (for real raw support).
2604 */
2605 if (termios->c_iflag & IGNPAR)
2606 port->ignore_status_mask |= UART_LSR_OE;
2607 }
2608
2609 /*
2610 * ignore all characters if CREAD is not set
2611 */
2612 if ((termios->c_cflag & CREAD) == 0)
2613 port->ignore_status_mask |= UART_LSR_DR;
2614
2615 /*
2616 * CTS flow control flag and modem status interrupts
2617 */
2618 up->ier &= ~UART_IER_MSI;
2619 if (!(up->bugs & UART_BUG_NOMSR) &&
2620 UART_ENABLE_MS(&up->port, termios->c_cflag))
2621 up->ier |= UART_IER_MSI;
2622 if (up->capabilities & UART_CAP_UUE)
2623 up->ier |= UART_IER_UUE;
2624 if (up->capabilities & UART_CAP_RTOIE)
2625 up->ier |= UART_IER_RTOIE;
2626
2627 serial_port_out(port, UART_IER, up->ier);
2628
2629 if (up->capabilities & UART_CAP_EFR) {
2630 unsigned char efr = 0;
2631 /*
2632 * TI16C752/Startech hardware flow control. FIXME:
2633 * - TI16C752 requires control thresholds to be set.
2634 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2635 */
2636 if (termios->c_cflag & CRTSCTS)
2637 efr |= UART_EFR_CTS;
2638
2639 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2640 if (port->flags & UPF_EXAR_EFR)
2641 serial_port_out(port, UART_XR_EFR, efr);
2642 else
2643 serial_port_out(port, UART_EFR, efr);
2644 }
2645
2646 serial8250_set_divisor(port, baud, quot, frac);
2647
2648 /*
2649 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2650 * is written without DLAB set, this mode will be disabled.
2651 */
2652 if (port->type == PORT_16750)
2653 serial_port_out(port, UART_FCR, up->fcr);
2654
2655 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2656 if (port->type != PORT_16750) {
2657 /* emulated UARTs (Lucent Venus 167x) need two steps */
2658 if (up->fcr & UART_FCR_ENABLE_FIFO)
2659 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2660 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2661 }
2662 serial8250_set_mctrl(port, port->mctrl);
2663 spin_unlock_irqrestore(&port->lock, flags);
2664 serial8250_rpm_put(up);
2665
2666 /* Don't rewrite B0 */
2667 if (tty_termios_baud_rate(termios))
2668 tty_termios_encode_baud_rate(termios, baud, baud);
2669 }
2670 EXPORT_SYMBOL(serial8250_do_set_termios);
2671
2672 static void
2673 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2674 struct ktermios *old)
2675 {
2676 if (port->set_termios)
2677 port->set_termios(port, termios, old);
2678 else
2679 serial8250_do_set_termios(port, termios, old);
2680 }
2681
2682 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2683 {
2684 if (termios->c_line == N_PPS) {
2685 port->flags |= UPF_HARDPPS_CD;
2686 spin_lock_irq(&port->lock);
2687 serial8250_enable_ms(port);
2688 spin_unlock_irq(&port->lock);
2689 } else {
2690 port->flags &= ~UPF_HARDPPS_CD;
2691 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2692 spin_lock_irq(&port->lock);
2693 serial8250_disable_ms(port);
2694 spin_unlock_irq(&port->lock);
2695 }
2696 }
2697 }
2698 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2699
2700 static void
2701 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2702 {
2703 if (port->set_ldisc)
2704 port->set_ldisc(port, termios);
2705 else
2706 serial8250_do_set_ldisc(port, termios);
2707 }
2708
2709 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2710 unsigned int oldstate)
2711 {
2712 struct uart_8250_port *p = up_to_u8250p(port);
2713
2714 serial8250_set_sleep(p, state != 0);
2715 }
2716 EXPORT_SYMBOL(serial8250_do_pm);
2717
2718 static void
2719 serial8250_pm(struct uart_port *port, unsigned int state,
2720 unsigned int oldstate)
2721 {
2722 if (port->pm)
2723 port->pm(port, state, oldstate);
2724 else
2725 serial8250_do_pm(port, state, oldstate);
2726 }
2727
2728 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2729 {
2730 if (pt->port.mapsize)
2731 return pt->port.mapsize;
2732 if (pt->port.iotype == UPIO_AU) {
2733 if (pt->port.type == PORT_RT2880)
2734 return 0x100;
2735 return 0x1000;
2736 }
2737 if (is_omap1_8250(pt))
2738 return 0x16 << pt->port.regshift;
2739
2740 return 8 << pt->port.regshift;
2741 }
2742
2743 /*
2744 * Resource handling.
2745 */
2746 static int serial8250_request_std_resource(struct uart_8250_port *up)
2747 {
2748 unsigned int size = serial8250_port_size(up);
2749 struct uart_port *port = &up->port;
2750 int ret = 0;
2751
2752 switch (port->iotype) {
2753 case UPIO_AU:
2754 case UPIO_TSI:
2755 case UPIO_MEM32:
2756 case UPIO_MEM32BE:
2757 case UPIO_MEM16:
2758 case UPIO_MEM:
2759 if (!port->mapbase)
2760 break;
2761
2762 if (!request_mem_region(port->mapbase, size, "serial")) {
2763 ret = -EBUSY;
2764 break;
2765 }
2766
2767 if (port->flags & UPF_IOREMAP) {
2768 port->membase = ioremap(port->mapbase, size);
2769 if (!port->membase) {
2770 release_mem_region(port->mapbase, size);
2771 ret = -ENOMEM;
2772 }
2773 }
2774 break;
2775
2776 case UPIO_HUB6:
2777 case UPIO_PORT:
2778 if (!request_region(port->iobase, size, "serial"))
2779 ret = -EBUSY;
2780 break;
2781 }
2782 return ret;
2783 }
2784
2785 static void serial8250_release_std_resource(struct uart_8250_port *up)
2786 {
2787 unsigned int size = serial8250_port_size(up);
2788 struct uart_port *port = &up->port;
2789
2790 switch (port->iotype) {
2791 case UPIO_AU:
2792 case UPIO_TSI:
2793 case UPIO_MEM32:
2794 case UPIO_MEM32BE:
2795 case UPIO_MEM16:
2796 case UPIO_MEM:
2797 if (!port->mapbase)
2798 break;
2799
2800 if (port->flags & UPF_IOREMAP) {
2801 iounmap(port->membase);
2802 port->membase = NULL;
2803 }
2804
2805 release_mem_region(port->mapbase, size);
2806 break;
2807
2808 case UPIO_HUB6:
2809 case UPIO_PORT:
2810 release_region(port->iobase, size);
2811 break;
2812 }
2813 }
2814
2815 static void serial8250_release_port(struct uart_port *port)
2816 {
2817 struct uart_8250_port *up = up_to_u8250p(port);
2818
2819 serial8250_release_std_resource(up);
2820 }
2821
2822 static int serial8250_request_port(struct uart_port *port)
2823 {
2824 struct uart_8250_port *up = up_to_u8250p(port);
2825
2826 return serial8250_request_std_resource(up);
2827 }
2828
2829 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2830 {
2831 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2832 unsigned char bytes;
2833
2834 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2835
2836 return bytes ? bytes : -EOPNOTSUPP;
2837 }
2838
2839 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2840 {
2841 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2842 int i;
2843
2844 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2845 return -EOPNOTSUPP;
2846
2847 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2848 if (bytes < conf_type->rxtrig_bytes[i])
2849 /* Use the nearest lower value */
2850 return (--i) << UART_FCR_R_TRIG_SHIFT;
2851 }
2852
2853 return UART_FCR_R_TRIG_11;
2854 }
2855
2856 static int do_get_rxtrig(struct tty_port *port)
2857 {
2858 struct uart_state *state = container_of(port, struct uart_state, port);
2859 struct uart_port *uport = state->uart_port;
2860 struct uart_8250_port *up = up_to_u8250p(uport);
2861
2862 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2863 return -EINVAL;
2864
2865 return fcr_get_rxtrig_bytes(up);
2866 }
2867
2868 static int do_serial8250_get_rxtrig(struct tty_port *port)
2869 {
2870 int rxtrig_bytes;
2871
2872 mutex_lock(&port->mutex);
2873 rxtrig_bytes = do_get_rxtrig(port);
2874 mutex_unlock(&port->mutex);
2875
2876 return rxtrig_bytes;
2877 }
2878
2879 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2880 struct device_attribute *attr, char *buf)
2881 {
2882 struct tty_port *port = dev_get_drvdata(dev);
2883 int rxtrig_bytes;
2884
2885 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2886 if (rxtrig_bytes < 0)
2887 return rxtrig_bytes;
2888
2889 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2890 }
2891
2892 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2893 {
2894 struct uart_state *state = container_of(port, struct uart_state, port);
2895 struct uart_port *uport = state->uart_port;
2896 struct uart_8250_port *up = up_to_u8250p(uport);
2897 int rxtrig;
2898
2899 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2900 up->fifo_bug)
2901 return -EINVAL;
2902
2903 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2904 if (rxtrig < 0)
2905 return rxtrig;
2906
2907 serial8250_clear_fifos(up);
2908 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2909 up->fcr |= (unsigned char)rxtrig;
2910 serial_out(up, UART_FCR, up->fcr);
2911 return 0;
2912 }
2913
2914 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2915 {
2916 int ret;
2917
2918 mutex_lock(&port->mutex);
2919 ret = do_set_rxtrig(port, bytes);
2920 mutex_unlock(&port->mutex);
2921
2922 return ret;
2923 }
2924
2925 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2926 struct device_attribute *attr, const char *buf, size_t count)
2927 {
2928 struct tty_port *port = dev_get_drvdata(dev);
2929 unsigned char bytes;
2930 int ret;
2931
2932 if (!count)
2933 return -EINVAL;
2934
2935 ret = kstrtou8(buf, 10, &bytes);
2936 if (ret < 0)
2937 return ret;
2938
2939 ret = do_serial8250_set_rxtrig(port, bytes);
2940 if (ret < 0)
2941 return ret;
2942
2943 return count;
2944 }
2945
2946 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2947 serial8250_get_attr_rx_trig_bytes,
2948 serial8250_set_attr_rx_trig_bytes);
2949
2950 static struct attribute *serial8250_dev_attrs[] = {
2951 &dev_attr_rx_trig_bytes.attr,
2952 NULL,
2953 };
2954
2955 static struct attribute_group serial8250_dev_attr_group = {
2956 .attrs = serial8250_dev_attrs,
2957 };
2958
2959 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2960 {
2961 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2962
2963 if (conf_type->rxtrig_bytes[0])
2964 up->port.attr_group = &serial8250_dev_attr_group;
2965 }
2966
2967 static void serial8250_config_port(struct uart_port *port, int flags)
2968 {
2969 struct uart_8250_port *up = up_to_u8250p(port);
2970 int ret;
2971
2972 /*
2973 * Find the region that we can probe for. This in turn
2974 * tells us whether we can probe for the type of port.
2975 */
2976 ret = serial8250_request_std_resource(up);
2977 if (ret < 0)
2978 return;
2979
2980 if (port->iotype != up->cur_iotype)
2981 set_io_from_upio(port);
2982
2983 if (flags & UART_CONFIG_TYPE)
2984 autoconfig(up);
2985
2986 /* if access method is AU, it is a 16550 with a quirk */
2987 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2988 up->bugs |= UART_BUG_NOMSR;
2989
2990 /* HW bugs may trigger IRQ while IIR == NO_INT */
2991 if (port->type == PORT_TEGRA)
2992 up->bugs |= UART_BUG_NOMSR;
2993
2994 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2995 autoconfig_irq(up);
2996
2997 if (port->type == PORT_UNKNOWN)
2998 serial8250_release_std_resource(up);
2999
3000 register_dev_spec_attr_grp(up);
3001 up->fcr = uart_config[up->port.type].fcr;
3002 }
3003
3004 static int
3005 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3006 {
3007 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3008 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3009 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3010 ser->type == PORT_STARTECH)
3011 return -EINVAL;
3012 return 0;
3013 }
3014
3015 static const char *serial8250_type(struct uart_port *port)
3016 {
3017 int type = port->type;
3018
3019 if (type >= ARRAY_SIZE(uart_config))
3020 type = 0;
3021 return uart_config[type].name;
3022 }
3023
3024 static const struct uart_ops serial8250_pops = {
3025 .tx_empty = serial8250_tx_empty,
3026 .set_mctrl = serial8250_set_mctrl,
3027 .get_mctrl = serial8250_get_mctrl,
3028 .stop_tx = serial8250_stop_tx,
3029 .start_tx = serial8250_start_tx,
3030 .throttle = serial8250_throttle,
3031 .unthrottle = serial8250_unthrottle,
3032 .stop_rx = serial8250_stop_rx,
3033 .enable_ms = serial8250_enable_ms,
3034 .break_ctl = serial8250_break_ctl,
3035 .startup = serial8250_startup,
3036 .shutdown = serial8250_shutdown,
3037 .set_termios = serial8250_set_termios,
3038 .set_ldisc = serial8250_set_ldisc,
3039 .pm = serial8250_pm,
3040 .type = serial8250_type,
3041 .release_port = serial8250_release_port,
3042 .request_port = serial8250_request_port,
3043 .config_port = serial8250_config_port,
3044 .verify_port = serial8250_verify_port,
3045 #ifdef CONFIG_CONSOLE_POLL
3046 .poll_get_char = serial8250_get_poll_char,
3047 .poll_put_char = serial8250_put_poll_char,
3048 #endif
3049 };
3050
3051 void serial8250_init_port(struct uart_8250_port *up)
3052 {
3053 struct uart_port *port = &up->port;
3054
3055 spin_lock_init(&port->lock);
3056 port->ops = &serial8250_pops;
3057 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3058
3059 up->cur_iotype = 0xFF;
3060 }
3061 EXPORT_SYMBOL_GPL(serial8250_init_port);
3062
3063 void serial8250_set_defaults(struct uart_8250_port *up)
3064 {
3065 struct uart_port *port = &up->port;
3066
3067 if (up->port.flags & UPF_FIXED_TYPE) {
3068 unsigned int type = up->port.type;
3069
3070 if (!up->port.fifosize)
3071 up->port.fifosize = uart_config[type].fifo_size;
3072 if (!up->tx_loadsz)
3073 up->tx_loadsz = uart_config[type].tx_loadsz;
3074 if (!up->capabilities)
3075 up->capabilities = uart_config[type].flags;
3076 }
3077
3078 set_io_from_upio(port);
3079
3080 /* default dma handlers */
3081 if (up->dma) {
3082 if (!up->dma->tx_dma)
3083 up->dma->tx_dma = serial8250_tx_dma;
3084 if (!up->dma->rx_dma)
3085 up->dma->rx_dma = serial8250_rx_dma;
3086 }
3087 }
3088 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3089
3090 #ifdef CONFIG_SERIAL_8250_CONSOLE
3091
3092 static void serial8250_console_putchar(struct uart_port *port, int ch)
3093 {
3094 struct uart_8250_port *up = up_to_u8250p(port);
3095
3096 wait_for_xmitr(up, UART_LSR_THRE);
3097 serial_port_out(port, UART_TX, ch);
3098 }
3099
3100 /*
3101 * Restore serial console when h/w power-off detected
3102 */
3103 static void serial8250_console_restore(struct uart_8250_port *up)
3104 {
3105 struct uart_port *port = &up->port;
3106 struct ktermios termios;
3107 unsigned int baud, quot, frac = 0;
3108
3109 termios.c_cflag = port->cons->cflag;
3110 if (port->state->port.tty && termios.c_cflag == 0)
3111 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3112
3113 baud = serial8250_get_baud_rate(port, &termios, NULL);
3114 quot = serial8250_get_divisor(port, baud, &frac);
3115
3116 serial8250_set_divisor(port, baud, quot, frac);
3117 serial_port_out(port, UART_LCR, up->lcr);
3118 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3119 }
3120
3121 /*
3122 * Print a string to the serial port trying not to disturb
3123 * any possible real use of the port...
3124 *
3125 * The console_lock must be held when we get here.
3126 */
3127 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3128 unsigned int count)
3129 {
3130 struct uart_port *port = &up->port;
3131 unsigned long flags;
3132 unsigned int ier;
3133 int locked = 1;
3134
3135 touch_nmi_watchdog();
3136
3137 serial8250_rpm_get(up);
3138
3139 if (oops_in_progress)
3140 locked = spin_trylock_irqsave(&port->lock, flags);
3141 else
3142 spin_lock_irqsave(&port->lock, flags);
3143
3144 /*
3145 * First save the IER then disable the interrupts
3146 */
3147 ier = serial_port_in(port, UART_IER);
3148
3149 if (up->capabilities & UART_CAP_UUE)
3150 serial_port_out(port, UART_IER, UART_IER_UUE);
3151 else
3152 serial_port_out(port, UART_IER, 0);
3153
3154 /* check scratch reg to see if port powered off during system sleep */
3155 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3156 serial8250_console_restore(up);
3157 up->canary = 0;
3158 }
3159
3160 uart_console_write(port, s, count, serial8250_console_putchar);
3161
3162 /*
3163 * Finally, wait for transmitter to become empty
3164 * and restore the IER
3165 */
3166 wait_for_xmitr(up, BOTH_EMPTY);
3167 serial_port_out(port, UART_IER, ier);
3168
3169 /*
3170 * The receive handling will happen properly because the
3171 * receive ready bit will still be set; it is not cleared
3172 * on read. However, modem control will not, we must
3173 * call it if we have saved something in the saved flags
3174 * while processing with interrupts off.
3175 */
3176 if (up->msr_saved_flags)
3177 serial8250_modem_status(up);
3178
3179 if (locked)
3180 spin_unlock_irqrestore(&port->lock, flags);
3181 serial8250_rpm_put(up);
3182 }
3183
3184 static unsigned int probe_baud(struct uart_port *port)
3185 {
3186 unsigned char lcr, dll, dlm;
3187 unsigned int quot;
3188
3189 lcr = serial_port_in(port, UART_LCR);
3190 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3191 dll = serial_port_in(port, UART_DLL);
3192 dlm = serial_port_in(port, UART_DLM);
3193 serial_port_out(port, UART_LCR, lcr);
3194
3195 quot = (dlm << 8) | dll;
3196 return (port->uartclk / 16) / quot;
3197 }
3198
3199 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3200 {
3201 int baud = 9600;
3202 int bits = 8;
3203 int parity = 'n';
3204 int flow = 'n';
3205
3206 if (!port->iobase && !port->membase)
3207 return -ENODEV;
3208
3209 if (options)
3210 uart_parse_options(options, &baud, &parity, &bits, &flow);
3211 else if (probe)
3212 baud = probe_baud(port);
3213
3214 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3215 }
3216
3217 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3218
3219 MODULE_LICENSE("GPL");
Linux with added FPC-III support