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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / tty / serial / atmel_serial.c
blobc15c398c88a938bd49494f959a3cb8da5b983620
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
5 *
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 *
9 * DMA support added by Chip Coldwell.
10 */
11 #include <linux/tty.h>
12 #include <linux/ioport.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/serial.h>
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/sysrq.h>
19 #include <linux/tty_flip.h>
20 #include <linux/platform_device.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/atmel_pdc.h>
27 #include <linux/uaccess.h>
28 #include <linux/platform_data/atmel.h>
29 #include <linux/timer.h>
30 #include <linux/gpio.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/suspend.h>
35 #include <linux/mm.h>
36
37 #include <asm/div64.h>
38 #include <asm/io.h>
39 #include <asm/ioctls.h>
40
41 #define PDC_BUFFER_SIZE 512
42 /* Revisit: We should calculate this based on the actual port settings */
43 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
44
45 /* The minium number of data FIFOs should be able to contain */
46 #define ATMEL_MIN_FIFO_SIZE 8
47 /*
48 * These two offsets are substracted from the RX FIFO size to define the RTS
49 * high and low thresholds
50 */
51 #define ATMEL_RTS_HIGH_OFFSET 16
52 #define ATMEL_RTS_LOW_OFFSET 20
53
54 #include <linux/serial_core.h>
55
56 #include "serial_mctrl_gpio.h"
57 #include "atmel_serial.h"
58
59 static void atmel_start_rx(struct uart_port *port);
60 static void atmel_stop_rx(struct uart_port *port);
61
62 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
63
64 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
65 * should coexist with the 8250 driver, such as if we have an external 16C550
66 * UART. */
67 #define SERIAL_ATMEL_MAJOR 204
68 #define MINOR_START 154
69 #define ATMEL_DEVICENAME "ttyAT"
70
71 #else
72
73 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
74 * name, but it is legally reserved for the 8250 driver. */
75 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
76 #define MINOR_START 64
77 #define ATMEL_DEVICENAME "ttyS"
78
79 #endif
80
81 #define ATMEL_ISR_PASS_LIMIT 256
82
83 struct atmel_dma_buffer {
84 unsigned char *buf;
85 dma_addr_t dma_addr;
86 unsigned int dma_size;
87 unsigned int ofs;
88 };
89
90 struct atmel_uart_char {
91 u16 status;
92 u16 ch;
93 };
94
95 /*
96 * Be careful, the real size of the ring buffer is
97 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
98 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
99 * DMA mode.
100 */
101 #define ATMEL_SERIAL_RINGSIZE 1024
102
103 /*
104 * at91: 6 USARTs and one DBGU port (SAM9260)
105 * samx7: 3 USARTs and 5 UARTs
106 */
107 #define ATMEL_MAX_UART 8
108
109 /*
110 * We wrap our port structure around the generic uart_port.
111 */
112 struct atmel_uart_port {
113 struct uart_port uart; /* uart */
114 struct clk *clk; /* uart clock */
115 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
116 u32 backup_imr; /* IMR saved during suspend */
117 int break_active; /* break being received */
118
119 bool use_dma_rx; /* enable DMA receiver */
120 bool use_pdc_rx; /* enable PDC receiver */
121 short pdc_rx_idx; /* current PDC RX buffer */
122 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
123
124 bool use_dma_tx; /* enable DMA transmitter */
125 bool use_pdc_tx; /* enable PDC transmitter */
126 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
127
128 spinlock_t lock_tx; /* port lock */
129 spinlock_t lock_rx; /* port lock */
130 struct dma_chan *chan_tx;
131 struct dma_chan *chan_rx;
132 struct dma_async_tx_descriptor *desc_tx;
133 struct dma_async_tx_descriptor *desc_rx;
134 dma_cookie_t cookie_tx;
135 dma_cookie_t cookie_rx;
136 struct scatterlist sg_tx;
137 struct scatterlist sg_rx;
138 struct tasklet_struct tasklet_rx;
139 struct tasklet_struct tasklet_tx;
140 atomic_t tasklet_shutdown;
141 unsigned int irq_status_prev;
142 unsigned int tx_len;
143
144 struct circ_buf rx_ring;
145
146 struct mctrl_gpios *gpios;
147 u32 backup_mode; /* MR saved during iso7816 operations */
148 u32 backup_brgr; /* BRGR saved during iso7816 operations */
149 unsigned int tx_done_mask;
150 u32 fifo_size;
151 u32 rts_high;
152 u32 rts_low;
153 bool ms_irq_enabled;
154 u32 rtor; /* address of receiver timeout register if it exists */
155 bool has_frac_baudrate;
156 bool has_hw_timer;
157 struct timer_list uart_timer;
158
159 bool tx_stopped;
160 bool suspended;
161 unsigned int pending;
162 unsigned int pending_status;
163 spinlock_t lock_suspended;
164
165 bool hd_start_rx; /* can start RX during half-duplex operation */
166
167 /* ISO7816 */
168 unsigned int fidi_min;
169 unsigned int fidi_max;
170
171 #ifdef CONFIG_PM
172 struct {
173 u32 cr;
174 u32 mr;
175 u32 imr;
176 u32 brgr;
177 u32 rtor;
178 u32 ttgr;
179 u32 fmr;
180 u32 fimr;
181 } cache;
182 #endif
183
184 int (*prepare_rx)(struct uart_port *port);
185 int (*prepare_tx)(struct uart_port *port);
186 void (*schedule_rx)(struct uart_port *port);
187 void (*schedule_tx)(struct uart_port *port);
188 void (*release_rx)(struct uart_port *port);
189 void (*release_tx)(struct uart_port *port);
190 };
191
192 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
193 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
194
195 #if defined(CONFIG_OF)
196 static const struct of_device_id atmel_serial_dt_ids[] = {
197 { .compatible = "atmel,at91rm9200-usart-serial" },
198 { /* sentinel */ }
199 };
200 #endif
201
202 static inline struct atmel_uart_port *
203 to_atmel_uart_port(struct uart_port *uart)
204 {
205 return container_of(uart, struct atmel_uart_port, uart);
206 }
207
208 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
209 {
210 return __raw_readl(port->membase + reg);
211 }
212
213 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
214 {
215 __raw_writel(value, port->membase + reg);
216 }
217
218 static inline u8 atmel_uart_read_char(struct uart_port *port)
219 {
220 return __raw_readb(port->membase + ATMEL_US_RHR);
221 }
222
223 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
224 {
225 __raw_writeb(value, port->membase + ATMEL_US_THR);
226 }
227
228 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
229 {
230 return ((port->rs485.flags & SER_RS485_ENABLED) &&
231 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
232 (port->iso7816.flags & SER_ISO7816_ENABLED);
233 }
234
235 #ifdef CONFIG_SERIAL_ATMEL_PDC
236 static bool atmel_use_pdc_rx(struct uart_port *port)
237 {
238 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
239
240 return atmel_port->use_pdc_rx;
241 }
242
243 static bool atmel_use_pdc_tx(struct uart_port *port)
244 {
245 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
246
247 return atmel_port->use_pdc_tx;
248 }
249 #else
250 static bool atmel_use_pdc_rx(struct uart_port *port)
251 {
252 return false;
253 }
254
255 static bool atmel_use_pdc_tx(struct uart_port *port)
256 {
257 return false;
258 }
259 #endif
260
261 static bool atmel_use_dma_tx(struct uart_port *port)
262 {
263 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
264
265 return atmel_port->use_dma_tx;
266 }
267
268 static bool atmel_use_dma_rx(struct uart_port *port)
269 {
270 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
271
272 return atmel_port->use_dma_rx;
273 }
274
275 static bool atmel_use_fifo(struct uart_port *port)
276 {
277 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
278
279 return atmel_port->fifo_size;
280 }
281
282 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
283 struct tasklet_struct *t)
284 {
285 if (!atomic_read(&atmel_port->tasklet_shutdown))
286 tasklet_schedule(t);
287 }
288
289 /* Enable or disable the rs485 support */
290 static int atmel_config_rs485(struct uart_port *port,
291 struct serial_rs485 *rs485conf)
292 {
293 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
294 unsigned int mode;
295
296 /* Disable interrupts */
297 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
298
299 mode = atmel_uart_readl(port, ATMEL_US_MR);
300
301 /* Resetting serial mode to RS232 (0x0) */
302 mode &= ~ATMEL_US_USMODE;
303
304 port->rs485 = *rs485conf;
305
306 if (rs485conf->flags & SER_RS485_ENABLED) {
307 dev_dbg(port->dev, "Setting UART to RS485\n");
308 if (port->rs485.flags & SER_RS485_RX_DURING_TX)
309 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
310 else
311 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
312
313 atmel_uart_writel(port, ATMEL_US_TTGR,
314 rs485conf->delay_rts_after_send);
315 mode |= ATMEL_US_USMODE_RS485;
316 } else {
317 dev_dbg(port->dev, "Setting UART to RS232\n");
318 if (atmel_use_pdc_tx(port))
319 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
320 ATMEL_US_TXBUFE;
321 else
322 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
323 }
324 atmel_uart_writel(port, ATMEL_US_MR, mode);
325
326 /* Enable interrupts */
327 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
328
329 return 0;
330 }
331
332 static unsigned int atmel_calc_cd(struct uart_port *port,
333 struct serial_iso7816 *iso7816conf)
334 {
335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
336 unsigned int cd;
337 u64 mck_rate;
338
339 mck_rate = (u64)clk_get_rate(atmel_port->clk);
340 do_div(mck_rate, iso7816conf->clk);
341 cd = mck_rate;
342 return cd;
343 }
344
345 static unsigned int atmel_calc_fidi(struct uart_port *port,
346 struct serial_iso7816 *iso7816conf)
347 {
348 u64 fidi = 0;
349
350 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
351 fidi = (u64)iso7816conf->sc_fi;
352 do_div(fidi, iso7816conf->sc_di);
353 }
354 return (u32)fidi;
355 }
356
357 /* Enable or disable the iso7816 support */
358 /* Called with interrupts disabled */
359 static int atmel_config_iso7816(struct uart_port *port,
360 struct serial_iso7816 *iso7816conf)
361 {
362 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
363 unsigned int mode;
364 unsigned int cd, fidi;
365 int ret = 0;
366
367 /* Disable interrupts */
368 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
369
370 mode = atmel_uart_readl(port, ATMEL_US_MR);
371
372 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
373 mode &= ~ATMEL_US_USMODE;
374
375 if (iso7816conf->tg > 255) {
376 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
377 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
378 ret = -EINVAL;
379 goto err_out;
380 }
381
382 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
383 == SER_ISO7816_T(0)) {
384 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
385 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
386 == SER_ISO7816_T(1)) {
387 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
388 } else {
389 dev_err(port->dev, "ISO7816: Type not supported\n");
390 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
391 ret = -EINVAL;
392 goto err_out;
393 }
394
395 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
396
397 /* select mck clock, and output */
398 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
399 /* set parity for normal/inverse mode + max iterations */
400 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
401
402 cd = atmel_calc_cd(port, iso7816conf);
403 fidi = atmel_calc_fidi(port, iso7816conf);
404 if (fidi == 0) {
405 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
406 } else if (fidi < atmel_port->fidi_min
407 || fidi > atmel_port->fidi_max) {
408 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
409 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
410 ret = -EINVAL;
411 goto err_out;
412 }
413
414 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
415 /* port not yet in iso7816 mode: store configuration */
416 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
417 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
418 }
419
420 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
421 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
422 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
423
424 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
425 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
426 } else {
427 dev_dbg(port->dev, "Setting UART back to RS232\n");
428 /* back to last RS232 settings */
429 mode = atmel_port->backup_mode;
430 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
431 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
432 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
433 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
434
435 if (atmel_use_pdc_tx(port))
436 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
437 ATMEL_US_TXBUFE;
438 else
439 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
440 }
441
442 port->iso7816 = *iso7816conf;
443
444 atmel_uart_writel(port, ATMEL_US_MR, mode);
445
446 err_out:
447 /* Enable interrupts */
448 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
449
450 return ret;
451 }
452
453 /*
454 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
455 */
456 static u_int atmel_tx_empty(struct uart_port *port)
457 {
458 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
459
460 if (atmel_port->tx_stopped)
461 return TIOCSER_TEMT;
462 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
463 TIOCSER_TEMT :
464 0;
465 }
466
467 /*
468 * Set state of the modem control output lines
469 */
470 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
471 {
472 unsigned int control = 0;
473 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
474 unsigned int rts_paused, rts_ready;
475 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
476
477 /* override mode to RS485 if needed, otherwise keep the current mode */
478 if (port->rs485.flags & SER_RS485_ENABLED) {
479 atmel_uart_writel(port, ATMEL_US_TTGR,
480 port->rs485.delay_rts_after_send);
481 mode &= ~ATMEL_US_USMODE;
482 mode |= ATMEL_US_USMODE_RS485;
483 }
484
485 /* set the RTS line state according to the mode */
486 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
487 /* force RTS line to high level */
488 rts_paused = ATMEL_US_RTSEN;
489
490 /* give the control of the RTS line back to the hardware */
491 rts_ready = ATMEL_US_RTSDIS;
492 } else {
493 /* force RTS line to high level */
494 rts_paused = ATMEL_US_RTSDIS;
495
496 /* force RTS line to low level */
497 rts_ready = ATMEL_US_RTSEN;
498 }
499
500 if (mctrl & TIOCM_RTS)
501 control |= rts_ready;
502 else
503 control |= rts_paused;
504
505 if (mctrl & TIOCM_DTR)
506 control |= ATMEL_US_DTREN;
507 else
508 control |= ATMEL_US_DTRDIS;
509
510 atmel_uart_writel(port, ATMEL_US_CR, control);
511
512 mctrl_gpio_set(atmel_port->gpios, mctrl);
513
514 /* Local loopback mode? */
515 mode &= ~ATMEL_US_CHMODE;
516 if (mctrl & TIOCM_LOOP)
517 mode |= ATMEL_US_CHMODE_LOC_LOOP;
518 else
519 mode |= ATMEL_US_CHMODE_NORMAL;
520
521 atmel_uart_writel(port, ATMEL_US_MR, mode);
522 }
523
524 /*
525 * Get state of the modem control input lines
526 */
527 static u_int atmel_get_mctrl(struct uart_port *port)
528 {
529 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
530 unsigned int ret = 0, status;
531
532 status = atmel_uart_readl(port, ATMEL_US_CSR);
533
534 /*
535 * The control signals are active low.
536 */
537 if (!(status & ATMEL_US_DCD))
538 ret |= TIOCM_CD;
539 if (!(status & ATMEL_US_CTS))
540 ret |= TIOCM_CTS;
541 if (!(status & ATMEL_US_DSR))
542 ret |= TIOCM_DSR;
543 if (!(status & ATMEL_US_RI))
544 ret |= TIOCM_RI;
545
546 return mctrl_gpio_get(atmel_port->gpios, &ret);
547 }
548
549 /*
550 * Stop transmitting.
551 */
552 static void atmel_stop_tx(struct uart_port *port)
553 {
554 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
555
556 if (atmel_use_pdc_tx(port)) {
557 /* disable PDC transmit */
558 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
559 }
560
561 /*
562 * Disable the transmitter.
563 * This is mandatory when DMA is used, otherwise the DMA buffer
564 * is fully transmitted.
565 */
566 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
567 atmel_port->tx_stopped = true;
568
569 /* Disable interrupts */
570 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
571
572 if (atmel_uart_is_half_duplex(port))
573 atmel_start_rx(port);
574
575 }
576
577 /*
578 * Start transmitting.
579 */
580 static void atmel_start_tx(struct uart_port *port)
581 {
582 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
583
584 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
585 & ATMEL_PDC_TXTEN))
586 /* The transmitter is already running. Yes, we
587 really need this.*/
588 return;
589
590 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
591 if (atmel_uart_is_half_duplex(port))
592 atmel_stop_rx(port);
593
594 if (atmel_use_pdc_tx(port))
595 /* re-enable PDC transmit */
596 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
597
598 /* Enable interrupts */
599 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
600
601 /* re-enable the transmitter */
602 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
603 atmel_port->tx_stopped = false;
604 }
605
606 /*
607 * start receiving - port is in process of being opened.
608 */
609 static void atmel_start_rx(struct uart_port *port)
610 {
611 /* reset status and receiver */
612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
613
614 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
615
616 if (atmel_use_pdc_rx(port)) {
617 /* enable PDC controller */
618 atmel_uart_writel(port, ATMEL_US_IER,
619 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
620 port->read_status_mask);
621 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
622 } else {
623 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
624 }
625 }
626
627 /*
628 * Stop receiving - port is in process of being closed.
629 */
630 static void atmel_stop_rx(struct uart_port *port)
631 {
632 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
633
634 if (atmel_use_pdc_rx(port)) {
635 /* disable PDC receive */
636 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
637 atmel_uart_writel(port, ATMEL_US_IDR,
638 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
639 port->read_status_mask);
640 } else {
641 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
642 }
643 }
644
645 /*
646 * Enable modem status interrupts
647 */
648 static void atmel_enable_ms(struct uart_port *port)
649 {
650 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
651 uint32_t ier = 0;
652
653 /*
654 * Interrupt should not be enabled twice
655 */
656 if (atmel_port->ms_irq_enabled)
657 return;
658
659 atmel_port->ms_irq_enabled = true;
660
661 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
662 ier |= ATMEL_US_CTSIC;
663
664 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
665 ier |= ATMEL_US_DSRIC;
666
667 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
668 ier |= ATMEL_US_RIIC;
669
670 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
671 ier |= ATMEL_US_DCDIC;
672
673 atmel_uart_writel(port, ATMEL_US_IER, ier);
674
675 mctrl_gpio_enable_ms(atmel_port->gpios);
676 }
677
678 /*
679 * Disable modem status interrupts
680 */
681 static void atmel_disable_ms(struct uart_port *port)
682 {
683 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
684 uint32_t idr = 0;
685
686 /*
687 * Interrupt should not be disabled twice
688 */
689 if (!atmel_port->ms_irq_enabled)
690 return;
691
692 atmel_port->ms_irq_enabled = false;
693
694 mctrl_gpio_disable_ms(atmel_port->gpios);
695
696 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
697 idr |= ATMEL_US_CTSIC;
698
699 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
700 idr |= ATMEL_US_DSRIC;
701
702 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
703 idr |= ATMEL_US_RIIC;
704
705 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
706 idr |= ATMEL_US_DCDIC;
707
708 atmel_uart_writel(port, ATMEL_US_IDR, idr);
709 }
710
711 /*
712 * Control the transmission of a break signal
713 */
714 static void atmel_break_ctl(struct uart_port *port, int break_state)
715 {
716 if (break_state != 0)
717 /* start break */
718 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
719 else
720 /* stop break */
721 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
722 }
723
724 /*
725 * Stores the incoming character in the ring buffer
726 */
727 static void
728 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
729 unsigned int ch)
730 {
731 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
732 struct circ_buf *ring = &atmel_port->rx_ring;
733 struct atmel_uart_char *c;
734
735 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
736 /* Buffer overflow, ignore char */
737 return;
738
739 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
740 c->status = status;
741 c->ch = ch;
742
743 /* Make sure the character is stored before we update head. */
744 smp_wmb();
745
746 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
747 }
748
749 /*
750 * Deal with parity, framing and overrun errors.
751 */
752 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
753 {
754 /* clear error */
755 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
756
757 if (status & ATMEL_US_RXBRK) {
758 /* ignore side-effect */
759 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
760 port->icount.brk++;
761 }
762 if (status & ATMEL_US_PARE)
763 port->icount.parity++;
764 if (status & ATMEL_US_FRAME)
765 port->icount.frame++;
766 if (status & ATMEL_US_OVRE)
767 port->icount.overrun++;
768 }
769
770 /*
771 * Characters received (called from interrupt handler)
772 */
773 static void atmel_rx_chars(struct uart_port *port)
774 {
775 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
776 unsigned int status, ch;
777
778 status = atmel_uart_readl(port, ATMEL_US_CSR);
779 while (status & ATMEL_US_RXRDY) {
780 ch = atmel_uart_read_char(port);
781
782 /*
783 * note that the error handling code is
784 * out of the main execution path
785 */
786 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
787 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
788 || atmel_port->break_active)) {
789
790 /* clear error */
791 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
792
793 if (status & ATMEL_US_RXBRK
794 && !atmel_port->break_active) {
795 atmel_port->break_active = 1;
796 atmel_uart_writel(port, ATMEL_US_IER,
797 ATMEL_US_RXBRK);
798 } else {
799 /*
800 * This is either the end-of-break
801 * condition or we've received at
802 * least one character without RXBRK
803 * being set. In both cases, the next
804 * RXBRK will indicate start-of-break.
805 */
806 atmel_uart_writel(port, ATMEL_US_IDR,
807 ATMEL_US_RXBRK);
808 status &= ~ATMEL_US_RXBRK;
809 atmel_port->break_active = 0;
810 }
811 }
812
813 atmel_buffer_rx_char(port, status, ch);
814 status = atmel_uart_readl(port, ATMEL_US_CSR);
815 }
816
817 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
818 }
819
820 /*
821 * Transmit characters (called from tasklet with TXRDY interrupt
822 * disabled)
823 */
824 static void atmel_tx_chars(struct uart_port *port)
825 {
826 struct circ_buf *xmit = &port->state->xmit;
827 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
828
829 if (port->x_char &&
830 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) {
831 atmel_uart_write_char(port, port->x_char);
832 port->icount.tx++;
833 port->x_char = 0;
834 }
835 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
836 return;
837
838 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) {
839 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
840 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
841 port->icount.tx++;
842 if (uart_circ_empty(xmit))
843 break;
844 }
845
846 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
847 uart_write_wakeup(port);
848
849 if (!uart_circ_empty(xmit)) {
850 /* we still have characters to transmit, so we should continue
851 * transmitting them when TX is ready, regardless of
852 * mode or duplexity
853 */
854 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
855
856 /* Enable interrupts */
857 atmel_uart_writel(port, ATMEL_US_IER,
858 atmel_port->tx_done_mask);
859 } else {
860 if (atmel_uart_is_half_duplex(port))
861 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
862 }
863 }
864
865 static void atmel_complete_tx_dma(void *arg)
866 {
867 struct atmel_uart_port *atmel_port = arg;
868 struct uart_port *port = &atmel_port->uart;
869 struct circ_buf *xmit = &port->state->xmit;
870 struct dma_chan *chan = atmel_port->chan_tx;
871 unsigned long flags;
872
873 spin_lock_irqsave(&port->lock, flags);
874
875 if (chan)
876 dmaengine_terminate_all(chan);
877 xmit->tail += atmel_port->tx_len;
878 xmit->tail &= UART_XMIT_SIZE - 1;
879
880 port->icount.tx += atmel_port->tx_len;
881
882 spin_lock_irq(&atmel_port->lock_tx);
883 async_tx_ack(atmel_port->desc_tx);
884 atmel_port->cookie_tx = -EINVAL;
885 atmel_port->desc_tx = NULL;
886 spin_unlock_irq(&atmel_port->lock_tx);
887
888 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
889 uart_write_wakeup(port);
890
891 /*
892 * xmit is a circular buffer so, if we have just send data from
893 * xmit->tail to the end of xmit->buf, now we have to transmit the
894 * remaining data from the beginning of xmit->buf to xmit->head.
895 */
896 if (!uart_circ_empty(xmit))
897 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
898 else if (atmel_uart_is_half_duplex(port)) {
899 /*
900 * DMA done, re-enable TXEMPTY and signal that we can stop
901 * TX and start RX for RS485
902 */
903 atmel_port->hd_start_rx = true;
904 atmel_uart_writel(port, ATMEL_US_IER,
905 atmel_port->tx_done_mask);
906 }
907
908 spin_unlock_irqrestore(&port->lock, flags);
909 }
910
911 static void atmel_release_tx_dma(struct uart_port *port)
912 {
913 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
914 struct dma_chan *chan = atmel_port->chan_tx;
915
916 if (chan) {
917 dmaengine_terminate_all(chan);
918 dma_release_channel(chan);
919 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
920 DMA_TO_DEVICE);
921 }
922
923 atmel_port->desc_tx = NULL;
924 atmel_port->chan_tx = NULL;
925 atmel_port->cookie_tx = -EINVAL;
926 }
927
928 /*
929 * Called from tasklet with TXRDY interrupt is disabled.
930 */
931 static void atmel_tx_dma(struct uart_port *port)
932 {
933 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
934 struct circ_buf *xmit = &port->state->xmit;
935 struct dma_chan *chan = atmel_port->chan_tx;
936 struct dma_async_tx_descriptor *desc;
937 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
938 unsigned int tx_len, part1_len, part2_len, sg_len;
939 dma_addr_t phys_addr;
940
941 /* Make sure we have an idle channel */
942 if (atmel_port->desc_tx != NULL)
943 return;
944
945 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
946 /*
947 * DMA is idle now.
948 * Port xmit buffer is already mapped,
949 * and it is one page... Just adjust
950 * offsets and lengths. Since it is a circular buffer,
951 * we have to transmit till the end, and then the rest.
952 * Take the port lock to get a
953 * consistent xmit buffer state.
954 */
955 tx_len = CIRC_CNT_TO_END(xmit->head,
956 xmit->tail,
957 UART_XMIT_SIZE);
958
959 if (atmel_port->fifo_size) {
960 /* multi data mode */
961 part1_len = (tx_len & ~0x3); /* DWORD access */
962 part2_len = (tx_len & 0x3); /* BYTE access */
963 } else {
964 /* single data (legacy) mode */
965 part1_len = 0;
966 part2_len = tx_len; /* BYTE access only */
967 }
968
969 sg_init_table(sgl, 2);
970 sg_len = 0;
971 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
972 if (part1_len) {
973 sg = &sgl[sg_len++];
974 sg_dma_address(sg) = phys_addr;
975 sg_dma_len(sg) = part1_len;
976
977 phys_addr += part1_len;
978 }
979
980 if (part2_len) {
981 sg = &sgl[sg_len++];
982 sg_dma_address(sg) = phys_addr;
983 sg_dma_len(sg) = part2_len;
984 }
985
986 /*
987 * save tx_len so atmel_complete_tx_dma() will increase
988 * xmit->tail correctly
989 */
990 atmel_port->tx_len = tx_len;
991
992 desc = dmaengine_prep_slave_sg(chan,
993 sgl,
994 sg_len,
995 DMA_MEM_TO_DEV,
996 DMA_PREP_INTERRUPT |
997 DMA_CTRL_ACK);
998 if (!desc) {
999 dev_err(port->dev, "Failed to send via dma!\n");
1000 return;
1001 }
1002
1003 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
1004
1005 atmel_port->desc_tx = desc;
1006 desc->callback = atmel_complete_tx_dma;
1007 desc->callback_param = atmel_port;
1008 atmel_port->cookie_tx = dmaengine_submit(desc);
1009 }
1010
1011 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1012 uart_write_wakeup(port);
1013 }
1014
1015 static int atmel_prepare_tx_dma(struct uart_port *port)
1016 {
1017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1018 struct device *mfd_dev = port->dev->parent;
1019 dma_cap_mask_t mask;
1020 struct dma_slave_config config;
1021 int ret, nent;
1022
1023 dma_cap_zero(mask);
1024 dma_cap_set(DMA_SLAVE, mask);
1025
1026 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1027 if (atmel_port->chan_tx == NULL)
1028 goto chan_err;
1029 dev_info(port->dev, "using %s for tx DMA transfers\n",
1030 dma_chan_name(atmel_port->chan_tx));
1031
1032 spin_lock_init(&atmel_port->lock_tx);
1033 sg_init_table(&atmel_port->sg_tx, 1);
1034 /* UART circular tx buffer is an aligned page. */
1035 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1036 sg_set_page(&atmel_port->sg_tx,
1037 virt_to_page(port->state->xmit.buf),
1038 UART_XMIT_SIZE,
1039 offset_in_page(port->state->xmit.buf));
1040 nent = dma_map_sg(port->dev,
1041 &atmel_port->sg_tx,
1042 1,
1043 DMA_TO_DEVICE);
1044
1045 if (!nent) {
1046 dev_dbg(port->dev, "need to release resource of dma\n");
1047 goto chan_err;
1048 } else {
1049 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1050 sg_dma_len(&atmel_port->sg_tx),
1051 port->state->xmit.buf,
1052 &sg_dma_address(&atmel_port->sg_tx));
1053 }
1054
1055 /* Configure the slave DMA */
1056 memset(&config, 0, sizeof(config));
1057 config.direction = DMA_MEM_TO_DEV;
1058 config.dst_addr_width = (atmel_port->fifo_size) ?
1059 DMA_SLAVE_BUSWIDTH_4_BYTES :
1060 DMA_SLAVE_BUSWIDTH_1_BYTE;
1061 config.dst_addr = port->mapbase + ATMEL_US_THR;
1062 config.dst_maxburst = 1;
1063
1064 ret = dmaengine_slave_config(atmel_port->chan_tx,
1065 &config);
1066 if (ret) {
1067 dev_err(port->dev, "DMA tx slave configuration failed\n");
1068 goto chan_err;
1069 }
1070
1071 return 0;
1072
1073 chan_err:
1074 dev_err(port->dev, "TX channel not available, switch to pio\n");
1075 atmel_port->use_dma_tx = false;
1076 if (atmel_port->chan_tx)
1077 atmel_release_tx_dma(port);
1078 return -EINVAL;
1079 }
1080
1081 static void atmel_complete_rx_dma(void *arg)
1082 {
1083 struct uart_port *port = arg;
1084 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1085
1086 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1087 }
1088
1089 static void atmel_release_rx_dma(struct uart_port *port)
1090 {
1091 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1092 struct dma_chan *chan = atmel_port->chan_rx;
1093
1094 if (chan) {
1095 dmaengine_terminate_all(chan);
1096 dma_release_channel(chan);
1097 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1098 DMA_FROM_DEVICE);
1099 }
1100
1101 atmel_port->desc_rx = NULL;
1102 atmel_port->chan_rx = NULL;
1103 atmel_port->cookie_rx = -EINVAL;
1104 }
1105
1106 static void atmel_rx_from_dma(struct uart_port *port)
1107 {
1108 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1109 struct tty_port *tport = &port->state->port;
1110 struct circ_buf *ring = &atmel_port->rx_ring;
1111 struct dma_chan *chan = atmel_port->chan_rx;
1112 struct dma_tx_state state;
1113 enum dma_status dmastat;
1114 size_t count;
1115
1116
1117 /* Reset the UART timeout early so that we don't miss one */
1118 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1119 dmastat = dmaengine_tx_status(chan,
1120 atmel_port->cookie_rx,
1121 &state);
1122 /* Restart a new tasklet if DMA status is error */
1123 if (dmastat == DMA_ERROR) {
1124 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1125 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1126 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1127 return;
1128 }
1129
1130 /* CPU claims ownership of RX DMA buffer */
1131 dma_sync_sg_for_cpu(port->dev,
1132 &atmel_port->sg_rx,
1133 1,
1134 DMA_FROM_DEVICE);
1135
1136 /*
1137 * ring->head points to the end of data already written by the DMA.
1138 * ring->tail points to the beginning of data to be read by the
1139 * framework.
1140 * The current transfer size should not be larger than the dma buffer
1141 * length.
1142 */
1143 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1144 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1145 /*
1146 * At this point ring->head may point to the first byte right after the
1147 * last byte of the dma buffer:
1148 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1149 *
1150 * However ring->tail must always points inside the dma buffer:
1151 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1152 *
1153 * Since we use a ring buffer, we have to handle the case
1154 * where head is lower than tail. In such a case, we first read from
1155 * tail to the end of the buffer then reset tail.
1156 */
1157 if (ring->head < ring->tail) {
1158 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1159
1160 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1161 ring->tail = 0;
1162 port->icount.rx += count;
1163 }
1164
1165 /* Finally we read data from tail to head */
1166 if (ring->tail < ring->head) {
1167 count = ring->head - ring->tail;
1168
1169 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1170 /* Wrap ring->head if needed */
1171 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1172 ring->head = 0;
1173 ring->tail = ring->head;
1174 port->icount.rx += count;
1175 }
1176
1177 /* USART retreives ownership of RX DMA buffer */
1178 dma_sync_sg_for_device(port->dev,
1179 &atmel_port->sg_rx,
1180 1,
1181 DMA_FROM_DEVICE);
1182
1183 /*
1184 * Drop the lock here since it might end up calling
1185 * uart_start(), which takes the lock.
1186 */
1187 spin_unlock(&port->lock);
1188 tty_flip_buffer_push(tport);
1189 spin_lock(&port->lock);
1190
1191 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1192 }
1193
1194 static int atmel_prepare_rx_dma(struct uart_port *port)
1195 {
1196 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1197 struct device *mfd_dev = port->dev->parent;
1198 struct dma_async_tx_descriptor *desc;
1199 dma_cap_mask_t mask;
1200 struct dma_slave_config config;
1201 struct circ_buf *ring;
1202 int ret, nent;
1203
1204 ring = &atmel_port->rx_ring;
1205
1206 dma_cap_zero(mask);
1207 dma_cap_set(DMA_CYCLIC, mask);
1208
1209 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1210 if (atmel_port->chan_rx == NULL)
1211 goto chan_err;
1212 dev_info(port->dev, "using %s for rx DMA transfers\n",
1213 dma_chan_name(atmel_port->chan_rx));
1214
1215 spin_lock_init(&atmel_port->lock_rx);
1216 sg_init_table(&atmel_port->sg_rx, 1);
1217 /* UART circular rx buffer is an aligned page. */
1218 BUG_ON(!PAGE_ALIGNED(ring->buf));
1219 sg_set_page(&atmel_port->sg_rx,
1220 virt_to_page(ring->buf),
1221 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1222 offset_in_page(ring->buf));
1223 nent = dma_map_sg(port->dev,
1224 &atmel_port->sg_rx,
1225 1,
1226 DMA_FROM_DEVICE);
1227
1228 if (!nent) {
1229 dev_dbg(port->dev, "need to release resource of dma\n");
1230 goto chan_err;
1231 } else {
1232 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1233 sg_dma_len(&atmel_port->sg_rx),
1234 ring->buf,
1235 &sg_dma_address(&atmel_port->sg_rx));
1236 }
1237
1238 /* Configure the slave DMA */
1239 memset(&config, 0, sizeof(config));
1240 config.direction = DMA_DEV_TO_MEM;
1241 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1242 config.src_addr = port->mapbase + ATMEL_US_RHR;
1243 config.src_maxburst = 1;
1244
1245 ret = dmaengine_slave_config(atmel_port->chan_rx,
1246 &config);
1247 if (ret) {
1248 dev_err(port->dev, "DMA rx slave configuration failed\n");
1249 goto chan_err;
1250 }
1251 /*
1252 * Prepare a cyclic dma transfer, assign 2 descriptors,
1253 * each one is half ring buffer size
1254 */
1255 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1256 sg_dma_address(&atmel_port->sg_rx),
1257 sg_dma_len(&atmel_port->sg_rx),
1258 sg_dma_len(&atmel_port->sg_rx)/2,
1259 DMA_DEV_TO_MEM,
1260 DMA_PREP_INTERRUPT);
1261 if (!desc) {
1262 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1263 goto chan_err;
1264 }
1265 desc->callback = atmel_complete_rx_dma;
1266 desc->callback_param = port;
1267 atmel_port->desc_rx = desc;
1268 atmel_port->cookie_rx = dmaengine_submit(desc);
1269
1270 return 0;
1271
1272 chan_err:
1273 dev_err(port->dev, "RX channel not available, switch to pio\n");
1274 atmel_port->use_dma_rx = false;
1275 if (atmel_port->chan_rx)
1276 atmel_release_rx_dma(port);
1277 return -EINVAL;
1278 }
1279
1280 static void atmel_uart_timer_callback(struct timer_list *t)
1281 {
1282 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1283 uart_timer);
1284 struct uart_port *port = &atmel_port->uart;
1285
1286 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1287 tasklet_schedule(&atmel_port->tasklet_rx);
1288 mod_timer(&atmel_port->uart_timer,
1289 jiffies + uart_poll_timeout(port));
1290 }
1291 }
1292
1293 /*
1294 * receive interrupt handler.
1295 */
1296 static void
1297 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1298 {
1299 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1300
1301 if (atmel_use_pdc_rx(port)) {
1302 /*
1303 * PDC receive. Just schedule the tasklet and let it
1304 * figure out the details.
1305 *
1306 * TODO: We're not handling error flags correctly at
1307 * the moment.
1308 */
1309 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1310 atmel_uart_writel(port, ATMEL_US_IDR,
1311 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1312 atmel_tasklet_schedule(atmel_port,
1313 &atmel_port->tasklet_rx);
1314 }
1315
1316 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1317 ATMEL_US_FRAME | ATMEL_US_PARE))
1318 atmel_pdc_rxerr(port, pending);
1319 }
1320
1321 if (atmel_use_dma_rx(port)) {
1322 if (pending & ATMEL_US_TIMEOUT) {
1323 atmel_uart_writel(port, ATMEL_US_IDR,
1324 ATMEL_US_TIMEOUT);
1325 atmel_tasklet_schedule(atmel_port,
1326 &atmel_port->tasklet_rx);
1327 }
1328 }
1329
1330 /* Interrupt receive */
1331 if (pending & ATMEL_US_RXRDY)
1332 atmel_rx_chars(port);
1333 else if (pending & ATMEL_US_RXBRK) {
1334 /*
1335 * End of break detected. If it came along with a
1336 * character, atmel_rx_chars will handle it.
1337 */
1338 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1339 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1340 atmel_port->break_active = 0;
1341 }
1342 }
1343
1344 /*
1345 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1346 */
1347 static void
1348 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1349 {
1350 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1351
1352 if (pending & atmel_port->tx_done_mask) {
1353 atmel_uart_writel(port, ATMEL_US_IDR,
1354 atmel_port->tx_done_mask);
1355
1356 /* Start RX if flag was set and FIFO is empty */
1357 if (atmel_port->hd_start_rx) {
1358 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1359 & ATMEL_US_TXEMPTY))
1360 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1361
1362 atmel_port->hd_start_rx = false;
1363 atmel_start_rx(port);
1364 }
1365
1366 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1367 }
1368 }
1369
1370 /*
1371 * status flags interrupt handler.
1372 */
1373 static void
1374 atmel_handle_status(struct uart_port *port, unsigned int pending,
1375 unsigned int status)
1376 {
1377 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1378 unsigned int status_change;
1379
1380 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1381 | ATMEL_US_CTSIC)) {
1382 status_change = status ^ atmel_port->irq_status_prev;
1383 atmel_port->irq_status_prev = status;
1384
1385 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1386 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1387 /* TODO: All reads to CSR will clear these interrupts! */
1388 if (status_change & ATMEL_US_RI)
1389 port->icount.rng++;
1390 if (status_change & ATMEL_US_DSR)
1391 port->icount.dsr++;
1392 if (status_change & ATMEL_US_DCD)
1393 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1394 if (status_change & ATMEL_US_CTS)
1395 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1396
1397 wake_up_interruptible(&port->state->port.delta_msr_wait);
1398 }
1399 }
1400
1401 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1402 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1403 }
1404
1405 /*
1406 * Interrupt handler
1407 */
1408 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1409 {
1410 struct uart_port *port = dev_id;
1411 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1412 unsigned int status, pending, mask, pass_counter = 0;
1413
1414 spin_lock(&atmel_port->lock_suspended);
1415
1416 do {
1417 status = atmel_uart_readl(port, ATMEL_US_CSR);
1418 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1419 pending = status & mask;
1420 if (!pending)
1421 break;
1422
1423 if (atmel_port->suspended) {
1424 atmel_port->pending |= pending;
1425 atmel_port->pending_status = status;
1426 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1427 pm_system_wakeup();
1428 break;
1429 }
1430
1431 atmel_handle_receive(port, pending);
1432 atmel_handle_status(port, pending, status);
1433 atmel_handle_transmit(port, pending);
1434 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1435
1436 spin_unlock(&atmel_port->lock_suspended);
1437
1438 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1439 }
1440
1441 static void atmel_release_tx_pdc(struct uart_port *port)
1442 {
1443 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1444 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1445
1446 dma_unmap_single(port->dev,
1447 pdc->dma_addr,
1448 pdc->dma_size,
1449 DMA_TO_DEVICE);
1450 }
1451
1452 /*
1453 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1454 */
1455 static void atmel_tx_pdc(struct uart_port *port)
1456 {
1457 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1458 struct circ_buf *xmit = &port->state->xmit;
1459 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1460 int count;
1461
1462 /* nothing left to transmit? */
1463 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1464 return;
1465
1466 xmit->tail += pdc->ofs;
1467 xmit->tail &= UART_XMIT_SIZE - 1;
1468
1469 port->icount.tx += pdc->ofs;
1470 pdc->ofs = 0;
1471
1472 /* more to transmit - setup next transfer */
1473
1474 /* disable PDC transmit */
1475 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1476
1477 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1478 dma_sync_single_for_device(port->dev,
1479 pdc->dma_addr,
1480 pdc->dma_size,
1481 DMA_TO_DEVICE);
1482
1483 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1484 pdc->ofs = count;
1485
1486 atmel_uart_writel(port, ATMEL_PDC_TPR,
1487 pdc->dma_addr + xmit->tail);
1488 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1489 /* re-enable PDC transmit */
1490 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1491 /* Enable interrupts */
1492 atmel_uart_writel(port, ATMEL_US_IER,
1493 atmel_port->tx_done_mask);
1494 } else {
1495 if (atmel_uart_is_half_duplex(port)) {
1496 /* DMA done, stop TX, start RX for RS485 */
1497 atmel_start_rx(port);
1498 }
1499 }
1500
1501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1502 uart_write_wakeup(port);
1503 }
1504
1505 static int atmel_prepare_tx_pdc(struct uart_port *port)
1506 {
1507 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1508 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1509 struct circ_buf *xmit = &port->state->xmit;
1510
1511 pdc->buf = xmit->buf;
1512 pdc->dma_addr = dma_map_single(port->dev,
1513 pdc->buf,
1514 UART_XMIT_SIZE,
1515 DMA_TO_DEVICE);
1516 pdc->dma_size = UART_XMIT_SIZE;
1517 pdc->ofs = 0;
1518
1519 return 0;
1520 }
1521
1522 static void atmel_rx_from_ring(struct uart_port *port)
1523 {
1524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1525 struct circ_buf *ring = &atmel_port->rx_ring;
1526 unsigned int flg;
1527 unsigned int status;
1528
1529 while (ring->head != ring->tail) {
1530 struct atmel_uart_char c;
1531
1532 /* Make sure c is loaded after head. */
1533 smp_rmb();
1534
1535 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1536
1537 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1538
1539 port->icount.rx++;
1540 status = c.status;
1541 flg = TTY_NORMAL;
1542
1543 /*
1544 * note that the error handling code is
1545 * out of the main execution path
1546 */
1547 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1548 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1549 if (status & ATMEL_US_RXBRK) {
1550 /* ignore side-effect */
1551 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1552
1553 port->icount.brk++;
1554 if (uart_handle_break(port))
1555 continue;
1556 }
1557 if (status & ATMEL_US_PARE)
1558 port->icount.parity++;
1559 if (status & ATMEL_US_FRAME)
1560 port->icount.frame++;
1561 if (status & ATMEL_US_OVRE)
1562 port->icount.overrun++;
1563
1564 status &= port->read_status_mask;
1565
1566 if (status & ATMEL_US_RXBRK)
1567 flg = TTY_BREAK;
1568 else if (status & ATMEL_US_PARE)
1569 flg = TTY_PARITY;
1570 else if (status & ATMEL_US_FRAME)
1571 flg = TTY_FRAME;
1572 }
1573
1574
1575 if (uart_handle_sysrq_char(port, c.ch))
1576 continue;
1577
1578 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1579 }
1580
1581 /*
1582 * Drop the lock here since it might end up calling
1583 * uart_start(), which takes the lock.
1584 */
1585 spin_unlock(&port->lock);
1586 tty_flip_buffer_push(&port->state->port);
1587 spin_lock(&port->lock);
1588 }
1589
1590 static void atmel_release_rx_pdc(struct uart_port *port)
1591 {
1592 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1593 int i;
1594
1595 for (i = 0; i < 2; i++) {
1596 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1597
1598 dma_unmap_single(port->dev,
1599 pdc->dma_addr,
1600 pdc->dma_size,
1601 DMA_FROM_DEVICE);
1602 kfree(pdc->buf);
1603 }
1604 }
1605
1606 static void atmel_rx_from_pdc(struct uart_port *port)
1607 {
1608 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1609 struct tty_port *tport = &port->state->port;
1610 struct atmel_dma_buffer *pdc;
1611 int rx_idx = atmel_port->pdc_rx_idx;
1612 unsigned int head;
1613 unsigned int tail;
1614 unsigned int count;
1615
1616 do {
1617 /* Reset the UART timeout early so that we don't miss one */
1618 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1619
1620 pdc = &atmel_port->pdc_rx[rx_idx];
1621 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1622 tail = pdc->ofs;
1623
1624 /* If the PDC has switched buffers, RPR won't contain
1625 * any address within the current buffer. Since head
1626 * is unsigned, we just need a one-way comparison to
1627 * find out.
1628 *
1629 * In this case, we just need to consume the entire
1630 * buffer and resubmit it for DMA. This will clear the
1631 * ENDRX bit as well, so that we can safely re-enable
1632 * all interrupts below.
1633 */
1634 head = min(head, pdc->dma_size);
1635
1636 if (likely(head != tail)) {
1637 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1638 pdc->dma_size, DMA_FROM_DEVICE);
1639
1640 /*
1641 * head will only wrap around when we recycle
1642 * the DMA buffer, and when that happens, we
1643 * explicitly set tail to 0. So head will
1644 * always be greater than tail.
1645 */
1646 count = head - tail;
1647
1648 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1649 count);
1650
1651 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1652 pdc->dma_size, DMA_FROM_DEVICE);
1653
1654 port->icount.rx += count;
1655 pdc->ofs = head;
1656 }
1657
1658 /*
1659 * If the current buffer is full, we need to check if
1660 * the next one contains any additional data.
1661 */
1662 if (head >= pdc->dma_size) {
1663 pdc->ofs = 0;
1664 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1665 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1666
1667 rx_idx = !rx_idx;
1668 atmel_port->pdc_rx_idx = rx_idx;
1669 }
1670 } while (head >= pdc->dma_size);
1671
1672 /*
1673 * Drop the lock here since it might end up calling
1674 * uart_start(), which takes the lock.
1675 */
1676 spin_unlock(&port->lock);
1677 tty_flip_buffer_push(tport);
1678 spin_lock(&port->lock);
1679
1680 atmel_uart_writel(port, ATMEL_US_IER,
1681 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1682 }
1683
1684 static int atmel_prepare_rx_pdc(struct uart_port *port)
1685 {
1686 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1687 int i;
1688
1689 for (i = 0; i < 2; i++) {
1690 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1691
1692 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1693 if (pdc->buf == NULL) {
1694 if (i != 0) {
1695 dma_unmap_single(port->dev,
1696 atmel_port->pdc_rx[0].dma_addr,
1697 PDC_BUFFER_SIZE,
1698 DMA_FROM_DEVICE);
1699 kfree(atmel_port->pdc_rx[0].buf);
1700 }
1701 atmel_port->use_pdc_rx = false;
1702 return -ENOMEM;
1703 }
1704 pdc->dma_addr = dma_map_single(port->dev,
1705 pdc->buf,
1706 PDC_BUFFER_SIZE,
1707 DMA_FROM_DEVICE);
1708 pdc->dma_size = PDC_BUFFER_SIZE;
1709 pdc->ofs = 0;
1710 }
1711
1712 atmel_port->pdc_rx_idx = 0;
1713
1714 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1715 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1716
1717 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1718 atmel_port->pdc_rx[1].dma_addr);
1719 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1720
1721 return 0;
1722 }
1723
1724 /*
1725 * tasklet handling tty stuff outside the interrupt handler.
1726 */
1727 static void atmel_tasklet_rx_func(unsigned long data)
1728 {
1729 struct uart_port *port = (struct uart_port *)data;
1730 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1731
1732 /* The interrupt handler does not take the lock */
1733 spin_lock(&port->lock);
1734 atmel_port->schedule_rx(port);
1735 spin_unlock(&port->lock);
1736 }
1737
1738 static void atmel_tasklet_tx_func(unsigned long data)
1739 {
1740 struct uart_port *port = (struct uart_port *)data;
1741 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1742
1743 /* The interrupt handler does not take the lock */
1744 spin_lock(&port->lock);
1745 atmel_port->schedule_tx(port);
1746 spin_unlock(&port->lock);
1747 }
1748
1749 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1750 struct platform_device *pdev)
1751 {
1752 struct device_node *np = pdev->dev.of_node;
1753
1754 /* DMA/PDC usage specification */
1755 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1756 if (of_property_read_bool(np, "dmas")) {
1757 atmel_port->use_dma_rx = true;
1758 atmel_port->use_pdc_rx = false;
1759 } else {
1760 atmel_port->use_dma_rx = false;
1761 atmel_port->use_pdc_rx = true;
1762 }
1763 } else {
1764 atmel_port->use_dma_rx = false;
1765 atmel_port->use_pdc_rx = false;
1766 }
1767
1768 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1769 if (of_property_read_bool(np, "dmas")) {
1770 atmel_port->use_dma_tx = true;
1771 atmel_port->use_pdc_tx = false;
1772 } else {
1773 atmel_port->use_dma_tx = false;
1774 atmel_port->use_pdc_tx = true;
1775 }
1776 } else {
1777 atmel_port->use_dma_tx = false;
1778 atmel_port->use_pdc_tx = false;
1779 }
1780 }
1781
1782 static void atmel_set_ops(struct uart_port *port)
1783 {
1784 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1785
1786 if (atmel_use_dma_rx(port)) {
1787 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1788 atmel_port->schedule_rx = &atmel_rx_from_dma;
1789 atmel_port->release_rx = &atmel_release_rx_dma;
1790 } else if (atmel_use_pdc_rx(port)) {
1791 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1792 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1793 atmel_port->release_rx = &atmel_release_rx_pdc;
1794 } else {
1795 atmel_port->prepare_rx = NULL;
1796 atmel_port->schedule_rx = &atmel_rx_from_ring;
1797 atmel_port->release_rx = NULL;
1798 }
1799
1800 if (atmel_use_dma_tx(port)) {
1801 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1802 atmel_port->schedule_tx = &atmel_tx_dma;
1803 atmel_port->release_tx = &atmel_release_tx_dma;
1804 } else if (atmel_use_pdc_tx(port)) {
1805 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1806 atmel_port->schedule_tx = &atmel_tx_pdc;
1807 atmel_port->release_tx = &atmel_release_tx_pdc;
1808 } else {
1809 atmel_port->prepare_tx = NULL;
1810 atmel_port->schedule_tx = &atmel_tx_chars;
1811 atmel_port->release_tx = NULL;
1812 }
1813 }
1814
1815 /*
1816 * Get ip name usart or uart
1817 */
1818 static void atmel_get_ip_name(struct uart_port *port)
1819 {
1820 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1821 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1822 u32 version;
1823 u32 usart, dbgu_uart, new_uart;
1824 /* ASCII decoding for IP version */
1825 usart = 0x55534152; /* USAR(T) */
1826 dbgu_uart = 0x44424755; /* DBGU */
1827 new_uart = 0x55415254; /* UART */
1828
1829 /*
1830 * Only USART devices from at91sam9260 SOC implement fractional
1831 * baudrate. It is available for all asynchronous modes, with the
1832 * following restriction: the sampling clock's duty cycle is not
1833 * constant.
1834 */
1835 atmel_port->has_frac_baudrate = false;
1836 atmel_port->has_hw_timer = false;
1837
1838 if (name == new_uart) {
1839 dev_dbg(port->dev, "Uart with hw timer");
1840 atmel_port->has_hw_timer = true;
1841 atmel_port->rtor = ATMEL_UA_RTOR;
1842 } else if (name == usart) {
1843 dev_dbg(port->dev, "Usart\n");
1844 atmel_port->has_frac_baudrate = true;
1845 atmel_port->has_hw_timer = true;
1846 atmel_port->rtor = ATMEL_US_RTOR;
1847 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1848 switch (version) {
1849 case 0x814: /* sama5d2 */
1850 /* fall through */
1851 case 0x701: /* sama5d4 */
1852 atmel_port->fidi_min = 3;
1853 atmel_port->fidi_max = 65535;
1854 break;
1855 case 0x502: /* sam9x5, sama5d3 */
1856 atmel_port->fidi_min = 3;
1857 atmel_port->fidi_max = 2047;
1858 break;
1859 default:
1860 atmel_port->fidi_min = 1;
1861 atmel_port->fidi_max = 2047;
1862 }
1863 } else if (name == dbgu_uart) {
1864 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1865 } else {
1866 /* fallback for older SoCs: use version field */
1867 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1868 switch (version) {
1869 case 0x302:
1870 case 0x10213:
1871 case 0x10302:
1872 dev_dbg(port->dev, "This version is usart\n");
1873 atmel_port->has_frac_baudrate = true;
1874 atmel_port->has_hw_timer = true;
1875 atmel_port->rtor = ATMEL_US_RTOR;
1876 break;
1877 case 0x203:
1878 case 0x10202:
1879 dev_dbg(port->dev, "This version is uart\n");
1880 break;
1881 default:
1882 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1883 }
1884 }
1885 }
1886
1887 /*
1888 * Perform initialization and enable port for reception
1889 */
1890 static int atmel_startup(struct uart_port *port)
1891 {
1892 struct platform_device *pdev = to_platform_device(port->dev);
1893 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1894 int retval;
1895
1896 /*
1897 * Ensure that no interrupts are enabled otherwise when
1898 * request_irq() is called we could get stuck trying to
1899 * handle an unexpected interrupt
1900 */
1901 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1902 atmel_port->ms_irq_enabled = false;
1903
1904 /*
1905 * Allocate the IRQ
1906 */
1907 retval = request_irq(port->irq, atmel_interrupt,
1908 IRQF_SHARED | IRQF_COND_SUSPEND,
1909 dev_name(&pdev->dev), port);
1910 if (retval) {
1911 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1912 return retval;
1913 }
1914
1915 atomic_set(&atmel_port->tasklet_shutdown, 0);
1916 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1917 (unsigned long)port);
1918 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1919 (unsigned long)port);
1920
1921 /*
1922 * Initialize DMA (if necessary)
1923 */
1924 atmel_init_property(atmel_port, pdev);
1925 atmel_set_ops(port);
1926
1927 if (atmel_port->prepare_rx) {
1928 retval = atmel_port->prepare_rx(port);
1929 if (retval < 0)
1930 atmel_set_ops(port);
1931 }
1932
1933 if (atmel_port->prepare_tx) {
1934 retval = atmel_port->prepare_tx(port);
1935 if (retval < 0)
1936 atmel_set_ops(port);
1937 }
1938
1939 /*
1940 * Enable FIFO when available
1941 */
1942 if (atmel_port->fifo_size) {
1943 unsigned int txrdym = ATMEL_US_ONE_DATA;
1944 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1945 unsigned int fmr;
1946
1947 atmel_uart_writel(port, ATMEL_US_CR,
1948 ATMEL_US_FIFOEN |
1949 ATMEL_US_RXFCLR |
1950 ATMEL_US_TXFLCLR);
1951
1952 if (atmel_use_dma_tx(port))
1953 txrdym = ATMEL_US_FOUR_DATA;
1954
1955 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1956 if (atmel_port->rts_high &&
1957 atmel_port->rts_low)
1958 fmr |= ATMEL_US_FRTSC |
1959 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1960 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1961
1962 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1963 }
1964
1965 /* Save current CSR for comparison in atmel_tasklet_func() */
1966 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1967
1968 /*
1969 * Finally, enable the serial port
1970 */
1971 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1972 /* enable xmit & rcvr */
1973 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1974 atmel_port->tx_stopped = false;
1975
1976 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1977
1978 if (atmel_use_pdc_rx(port)) {
1979 /* set UART timeout */
1980 if (!atmel_port->has_hw_timer) {
1981 mod_timer(&atmel_port->uart_timer,
1982 jiffies + uart_poll_timeout(port));
1983 /* set USART timeout */
1984 } else {
1985 atmel_uart_writel(port, atmel_port->rtor,
1986 PDC_RX_TIMEOUT);
1987 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1988
1989 atmel_uart_writel(port, ATMEL_US_IER,
1990 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1991 }
1992 /* enable PDC controller */
1993 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1994 } else if (atmel_use_dma_rx(port)) {
1995 /* set UART timeout */
1996 if (!atmel_port->has_hw_timer) {
1997 mod_timer(&atmel_port->uart_timer,
1998 jiffies + uart_poll_timeout(port));
1999 /* set USART timeout */
2000 } else {
2001 atmel_uart_writel(port, atmel_port->rtor,
2002 PDC_RX_TIMEOUT);
2003 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
2004
2005 atmel_uart_writel(port, ATMEL_US_IER,
2006 ATMEL_US_TIMEOUT);
2007 }
2008 } else {
2009 /* enable receive only */
2010 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2011 }
2012
2013 return 0;
2014 }
2015
2016 /*
2017 * Flush any TX data submitted for DMA. Called when the TX circular
2018 * buffer is reset.
2019 */
2020 static void atmel_flush_buffer(struct uart_port *port)
2021 {
2022 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2023
2024 if (atmel_use_pdc_tx(port)) {
2025 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2026 atmel_port->pdc_tx.ofs = 0;
2027 }
2028 /*
2029 * in uart_flush_buffer(), the xmit circular buffer has just
2030 * been cleared, so we have to reset tx_len accordingly.
2031 */
2032 atmel_port->tx_len = 0;
2033 }
2034
2035 /*
2036 * Disable the port
2037 */
2038 static void atmel_shutdown(struct uart_port *port)
2039 {
2040 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2041
2042 /* Disable modem control lines interrupts */
2043 atmel_disable_ms(port);
2044
2045 /* Disable interrupts at device level */
2046 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2047
2048 /* Prevent spurious interrupts from scheduling the tasklet */
2049 atomic_inc(&atmel_port->tasklet_shutdown);
2050
2051 /*
2052 * Prevent any tasklets being scheduled during
2053 * cleanup
2054 */
2055 del_timer_sync(&atmel_port->uart_timer);
2056
2057 /* Make sure that no interrupt is on the fly */
2058 synchronize_irq(port->irq);
2059
2060 /*
2061 * Clear out any scheduled tasklets before
2062 * we destroy the buffers
2063 */
2064 tasklet_kill(&atmel_port->tasklet_rx);
2065 tasklet_kill(&atmel_port->tasklet_tx);
2066
2067 /*
2068 * Ensure everything is stopped and
2069 * disable port and break condition.
2070 */
2071 atmel_stop_rx(port);
2072 atmel_stop_tx(port);
2073
2074 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2075
2076 /*
2077 * Shut-down the DMA.
2078 */
2079 if (atmel_port->release_rx)
2080 atmel_port->release_rx(port);
2081 if (atmel_port->release_tx)
2082 atmel_port->release_tx(port);
2083
2084 /*
2085 * Reset ring buffer pointers
2086 */
2087 atmel_port->rx_ring.head = 0;
2088 atmel_port->rx_ring.tail = 0;
2089
2090 /*
2091 * Free the interrupts
2092 */
2093 free_irq(port->irq, port);
2094
2095 atmel_flush_buffer(port);
2096 }
2097
2098 /*
2099 * Power / Clock management.
2100 */
2101 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2102 unsigned int oldstate)
2103 {
2104 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2105
2106 switch (state) {
2107 case 0:
2108 /*
2109 * Enable the peripheral clock for this serial port.
2110 * This is called on uart_open() or a resume event.
2111 */
2112 clk_prepare_enable(atmel_port->clk);
2113
2114 /* re-enable interrupts if we disabled some on suspend */
2115 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2116 break;
2117 case 3:
2118 /* Back up the interrupt mask and disable all interrupts */
2119 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2120 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2121
2122 /*
2123 * Disable the peripheral clock for this serial port.
2124 * This is called on uart_close() or a suspend event.
2125 */
2126 clk_disable_unprepare(atmel_port->clk);
2127 break;
2128 default:
2129 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2130 }
2131 }
2132
2133 /*
2134 * Change the port parameters
2135 */
2136 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2137 struct ktermios *old)
2138 {
2139 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2140 unsigned long flags;
2141 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2142
2143 /* save the current mode register */
2144 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2145
2146 /* reset the mode, clock divisor, parity, stop bits and data size */
2147 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2148 ATMEL_US_PAR | ATMEL_US_USMODE);
2149
2150 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2151
2152 /* byte size */
2153 switch (termios->c_cflag & CSIZE) {
2154 case CS5:
2155 mode |= ATMEL_US_CHRL_5;
2156 break;
2157 case CS6:
2158 mode |= ATMEL_US_CHRL_6;
2159 break;
2160 case CS7:
2161 mode |= ATMEL_US_CHRL_7;
2162 break;
2163 default:
2164 mode |= ATMEL_US_CHRL_8;
2165 break;
2166 }
2167
2168 /* stop bits */
2169 if (termios->c_cflag & CSTOPB)
2170 mode |= ATMEL_US_NBSTOP_2;
2171
2172 /* parity */
2173 if (termios->c_cflag & PARENB) {
2174 /* Mark or Space parity */
2175 if (termios->c_cflag & CMSPAR) {
2176 if (termios->c_cflag & PARODD)
2177 mode |= ATMEL_US_PAR_MARK;
2178 else
2179 mode |= ATMEL_US_PAR_SPACE;
2180 } else if (termios->c_cflag & PARODD)
2181 mode |= ATMEL_US_PAR_ODD;
2182 else
2183 mode |= ATMEL_US_PAR_EVEN;
2184 } else
2185 mode |= ATMEL_US_PAR_NONE;
2186
2187 spin_lock_irqsave(&port->lock, flags);
2188
2189 port->read_status_mask = ATMEL_US_OVRE;
2190 if (termios->c_iflag & INPCK)
2191 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2192 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2193 port->read_status_mask |= ATMEL_US_RXBRK;
2194
2195 if (atmel_use_pdc_rx(port))
2196 /* need to enable error interrupts */
2197 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2198
2199 /*
2200 * Characters to ignore
2201 */
2202 port->ignore_status_mask = 0;
2203 if (termios->c_iflag & IGNPAR)
2204 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2205 if (termios->c_iflag & IGNBRK) {
2206 port->ignore_status_mask |= ATMEL_US_RXBRK;
2207 /*
2208 * If we're ignoring parity and break indicators,
2209 * ignore overruns too (for real raw support).
2210 */
2211 if (termios->c_iflag & IGNPAR)
2212 port->ignore_status_mask |= ATMEL_US_OVRE;
2213 }
2214 /* TODO: Ignore all characters if CREAD is set.*/
2215
2216 /* update the per-port timeout */
2217 uart_update_timeout(port, termios->c_cflag, baud);
2218
2219 /*
2220 * save/disable interrupts. The tty layer will ensure that the
2221 * transmitter is empty if requested by the caller, so there's
2222 * no need to wait for it here.
2223 */
2224 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2225 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2226
2227 /* disable receiver and transmitter */
2228 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2229 atmel_port->tx_stopped = true;
2230
2231 /* mode */
2232 if (port->rs485.flags & SER_RS485_ENABLED) {
2233 atmel_uart_writel(port, ATMEL_US_TTGR,
2234 port->rs485.delay_rts_after_send);
2235 mode |= ATMEL_US_USMODE_RS485;
2236 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2237 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2238 /* select mck clock, and output */
2239 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2240 /* set max iterations */
2241 mode |= ATMEL_US_MAX_ITER(3);
2242 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2243 == SER_ISO7816_T(0))
2244 mode |= ATMEL_US_USMODE_ISO7816_T0;
2245 else
2246 mode |= ATMEL_US_USMODE_ISO7816_T1;
2247 } else if (termios->c_cflag & CRTSCTS) {
2248 /* RS232 with hardware handshake (RTS/CTS) */
2249 if (atmel_use_fifo(port) &&
2250 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2251 /*
2252 * with ATMEL_US_USMODE_HWHS set, the controller will
2253 * be able to drive the RTS pin high/low when the RX
2254 * FIFO is above RXFTHRES/below RXFTHRES2.
2255 * It will also disable the transmitter when the CTS
2256 * pin is high.
2257 * This mode is not activated if CTS pin is a GPIO
2258 * because in this case, the transmitter is always
2259 * disabled (there must be an internal pull-up
2260 * responsible for this behaviour).
2261 * If the RTS pin is a GPIO, the controller won't be
2262 * able to drive it according to the FIFO thresholds,
2263 * but it will be handled by the driver.
2264 */
2265 mode |= ATMEL_US_USMODE_HWHS;
2266 } else {
2267 /*
2268 * For platforms without FIFO, the flow control is
2269 * handled by the driver.
2270 */
2271 mode |= ATMEL_US_USMODE_NORMAL;
2272 }
2273 } else {
2274 /* RS232 without hadware handshake */
2275 mode |= ATMEL_US_USMODE_NORMAL;
2276 }
2277
2278 /*
2279 * Set the baud rate:
2280 * Fractional baudrate allows to setup output frequency more
2281 * accurately. This feature is enabled only when using normal mode.
2282 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2283 * Currently, OVER is always set to 0 so we get
2284 * baudrate = selected clock / (16 * (CD + FP / 8))
2285 * then
2286 * 8 CD + FP = selected clock / (2 * baudrate)
2287 */
2288 if (atmel_port->has_frac_baudrate) {
2289 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2290 cd = div >> 3;
2291 fp = div & ATMEL_US_FP_MASK;
2292 } else {
2293 cd = uart_get_divisor(port, baud);
2294 }
2295
2296 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2297 cd /= 8;
2298 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2299 }
2300 quot = cd | fp << ATMEL_US_FP_OFFSET;
2301
2302 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2303 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2304
2305 /* set the mode, clock divisor, parity, stop bits and data size */
2306 atmel_uart_writel(port, ATMEL_US_MR, mode);
2307
2308 /*
2309 * when switching the mode, set the RTS line state according to the
2310 * new mode, otherwise keep the former state
2311 */
2312 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2313 unsigned int rts_state;
2314
2315 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2316 /* let the hardware control the RTS line */
2317 rts_state = ATMEL_US_RTSDIS;
2318 } else {
2319 /* force RTS line to low level */
2320 rts_state = ATMEL_US_RTSEN;
2321 }
2322
2323 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2324 }
2325
2326 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2327 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2328 atmel_port->tx_stopped = false;
2329
2330 /* restore interrupts */
2331 atmel_uart_writel(port, ATMEL_US_IER, imr);
2332
2333 /* CTS flow-control and modem-status interrupts */
2334 if (UART_ENABLE_MS(port, termios->c_cflag))
2335 atmel_enable_ms(port);
2336 else
2337 atmel_disable_ms(port);
2338
2339 spin_unlock_irqrestore(&port->lock, flags);
2340 }
2341
2342 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2343 {
2344 if (termios->c_line == N_PPS) {
2345 port->flags |= UPF_HARDPPS_CD;
2346 spin_lock_irq(&port->lock);
2347 atmel_enable_ms(port);
2348 spin_unlock_irq(&port->lock);
2349 } else {
2350 port->flags &= ~UPF_HARDPPS_CD;
2351 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2352 spin_lock_irq(&port->lock);
2353 atmel_disable_ms(port);
2354 spin_unlock_irq(&port->lock);
2355 }
2356 }
2357 }
2358
2359 /*
2360 * Return string describing the specified port
2361 */
2362 static const char *atmel_type(struct uart_port *port)
2363 {
2364 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2365 }
2366
2367 /*
2368 * Release the memory region(s) being used by 'port'.
2369 */
2370 static void atmel_release_port(struct uart_port *port)
2371 {
2372 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2373 int size = resource_size(mpdev->resource);
2374
2375 release_mem_region(port->mapbase, size);
2376
2377 if (port->flags & UPF_IOREMAP) {
2378 iounmap(port->membase);
2379 port->membase = NULL;
2380 }
2381 }
2382
2383 /*
2384 * Request the memory region(s) being used by 'port'.
2385 */
2386 static int atmel_request_port(struct uart_port *port)
2387 {
2388 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2389 int size = resource_size(mpdev->resource);
2390
2391 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2392 return -EBUSY;
2393
2394 if (port->flags & UPF_IOREMAP) {
2395 port->membase = ioremap(port->mapbase, size);
2396 if (port->membase == NULL) {
2397 release_mem_region(port->mapbase, size);
2398 return -ENOMEM;
2399 }
2400 }
2401
2402 return 0;
2403 }
2404
2405 /*
2406 * Configure/autoconfigure the port.
2407 */
2408 static void atmel_config_port(struct uart_port *port, int flags)
2409 {
2410 if (flags & UART_CONFIG_TYPE) {
2411 port->type = PORT_ATMEL;
2412 atmel_request_port(port);
2413 }
2414 }
2415
2416 /*
2417 * Verify the new serial_struct (for TIOCSSERIAL).
2418 */
2419 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2420 {
2421 int ret = 0;
2422 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2423 ret = -EINVAL;
2424 if (port->irq != ser->irq)
2425 ret = -EINVAL;
2426 if (ser->io_type != SERIAL_IO_MEM)
2427 ret = -EINVAL;
2428 if (port->uartclk / 16 != ser->baud_base)
2429 ret = -EINVAL;
2430 if (port->mapbase != (unsigned long)ser->iomem_base)
2431 ret = -EINVAL;
2432 if (port->iobase != ser->port)
2433 ret = -EINVAL;
2434 if (ser->hub6 != 0)
2435 ret = -EINVAL;
2436 return ret;
2437 }
2438
2439 #ifdef CONFIG_CONSOLE_POLL
2440 static int atmel_poll_get_char(struct uart_port *port)
2441 {
2442 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2443 cpu_relax();
2444
2445 return atmel_uart_read_char(port);
2446 }
2447
2448 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2449 {
2450 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2451 cpu_relax();
2452
2453 atmel_uart_write_char(port, ch);
2454 }
2455 #endif
2456
2457 static const struct uart_ops atmel_pops = {
2458 .tx_empty = atmel_tx_empty,
2459 .set_mctrl = atmel_set_mctrl,
2460 .get_mctrl = atmel_get_mctrl,
2461 .stop_tx = atmel_stop_tx,
2462 .start_tx = atmel_start_tx,
2463 .stop_rx = atmel_stop_rx,
2464 .enable_ms = atmel_enable_ms,
2465 .break_ctl = atmel_break_ctl,
2466 .startup = atmel_startup,
2467 .shutdown = atmel_shutdown,
2468 .flush_buffer = atmel_flush_buffer,
2469 .set_termios = atmel_set_termios,
2470 .set_ldisc = atmel_set_ldisc,
2471 .type = atmel_type,
2472 .release_port = atmel_release_port,
2473 .request_port = atmel_request_port,
2474 .config_port = atmel_config_port,
2475 .verify_port = atmel_verify_port,
2476 .pm = atmel_serial_pm,
2477 #ifdef CONFIG_CONSOLE_POLL
2478 .poll_get_char = atmel_poll_get_char,
2479 .poll_put_char = atmel_poll_put_char,
2480 #endif
2481 };
2482
2483 /*
2484 * Configure the port from the platform device resource info.
2485 */
2486 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2487 struct platform_device *pdev)
2488 {
2489 int ret;
2490 struct uart_port *port = &atmel_port->uart;
2491 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2492
2493 atmel_init_property(atmel_port, pdev);
2494 atmel_set_ops(port);
2495
2496 uart_get_rs485_mode(&mpdev->dev, &port->rs485);
2497
2498 port->iotype = UPIO_MEM;
2499 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2500 port->ops = &atmel_pops;
2501 port->fifosize = 1;
2502 port->dev = &pdev->dev;
2503 port->mapbase = mpdev->resource[0].start;
2504 port->irq = mpdev->resource[1].start;
2505 port->rs485_config = atmel_config_rs485;
2506 port->iso7816_config = atmel_config_iso7816;
2507 port->membase = NULL;
2508
2509 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2510
2511 /* for console, the clock could already be configured */
2512 if (!atmel_port->clk) {
2513 atmel_port->clk = clk_get(&mpdev->dev, "usart");
2514 if (IS_ERR(atmel_port->clk)) {
2515 ret = PTR_ERR(atmel_port->clk);
2516 atmel_port->clk = NULL;
2517 return ret;
2518 }
2519 ret = clk_prepare_enable(atmel_port->clk);
2520 if (ret) {
2521 clk_put(atmel_port->clk);
2522 atmel_port->clk = NULL;
2523 return ret;
2524 }
2525 port->uartclk = clk_get_rate(atmel_port->clk);
2526 clk_disable_unprepare(atmel_port->clk);
2527 /* only enable clock when USART is in use */
2528 }
2529
2530 /*
2531 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2532 * ENDTX|TXBUFE
2533 */
2534 if (atmel_uart_is_half_duplex(port))
2535 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2536 else if (atmel_use_pdc_tx(port)) {
2537 port->fifosize = PDC_BUFFER_SIZE;
2538 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2539 } else {
2540 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2541 }
2542
2543 return 0;
2544 }
2545
2546 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2547 static void atmel_console_putchar(struct uart_port *port, int ch)
2548 {
2549 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2550 cpu_relax();
2551 atmel_uart_write_char(port, ch);
2552 }
2553
2554 /*
2555 * Interrupts are disabled on entering
2556 */
2557 static void atmel_console_write(struct console *co, const char *s, u_int count)
2558 {
2559 struct uart_port *port = &atmel_ports[co->index].uart;
2560 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2561 unsigned int status, imr;
2562 unsigned int pdc_tx;
2563
2564 /*
2565 * First, save IMR and then disable interrupts
2566 */
2567 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2568 atmel_uart_writel(port, ATMEL_US_IDR,
2569 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2570
2571 /* Store PDC transmit status and disable it */
2572 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2573 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2574
2575 /* Make sure that tx path is actually able to send characters */
2576 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2577 atmel_port->tx_stopped = false;
2578
2579 uart_console_write(port, s, count, atmel_console_putchar);
2580
2581 /*
2582 * Finally, wait for transmitter to become empty
2583 * and restore IMR
2584 */
2585 do {
2586 status = atmel_uart_readl(port, ATMEL_US_CSR);
2587 } while (!(status & ATMEL_US_TXRDY));
2588
2589 /* Restore PDC transmit status */
2590 if (pdc_tx)
2591 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2592
2593 /* set interrupts back the way they were */
2594 atmel_uart_writel(port, ATMEL_US_IER, imr);
2595 }
2596
2597 /*
2598 * If the port was already initialised (eg, by a boot loader),
2599 * try to determine the current setup.
2600 */
2601 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2602 int *parity, int *bits)
2603 {
2604 unsigned int mr, quot;
2605
2606 /*
2607 * If the baud rate generator isn't running, the port wasn't
2608 * initialized by the boot loader.
2609 */
2610 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2611 if (!quot)
2612 return;
2613
2614 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2615 if (mr == ATMEL_US_CHRL_8)
2616 *bits = 8;
2617 else
2618 *bits = 7;
2619
2620 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2621 if (mr == ATMEL_US_PAR_EVEN)
2622 *parity = 'e';
2623 else if (mr == ATMEL_US_PAR_ODD)
2624 *parity = 'o';
2625
2626 /*
2627 * The serial core only rounds down when matching this to a
2628 * supported baud rate. Make sure we don't end up slightly
2629 * lower than one of those, as it would make us fall through
2630 * to a much lower baud rate than we really want.
2631 */
2632 *baud = port->uartclk / (16 * (quot - 1));
2633 }
2634
2635 static int __init atmel_console_setup(struct console *co, char *options)
2636 {
2637 int ret;
2638 struct uart_port *port = &atmel_ports[co->index].uart;
2639 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2640 int baud = 115200;
2641 int bits = 8;
2642 int parity = 'n';
2643 int flow = 'n';
2644
2645 if (port->membase == NULL) {
2646 /* Port not initialized yet - delay setup */
2647 return -ENODEV;
2648 }
2649
2650 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2651 if (ret)
2652 return ret;
2653
2654 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2655 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2656 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2657 atmel_port->tx_stopped = false;
2658
2659 if (options)
2660 uart_parse_options(options, &baud, &parity, &bits, &flow);
2661 else
2662 atmel_console_get_options(port, &baud, &parity, &bits);
2663
2664 return uart_set_options(port, co, baud, parity, bits, flow);
2665 }
2666
2667 static struct uart_driver atmel_uart;
2668
2669 static struct console atmel_console = {
2670 .name = ATMEL_DEVICENAME,
2671 .write = atmel_console_write,
2672 .device = uart_console_device,
2673 .setup = atmel_console_setup,
2674 .flags = CON_PRINTBUFFER,
2675 .index = -1,
2676 .data = &atmel_uart,
2677 };
2678
2679 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2680
2681 static inline bool atmel_is_console_port(struct uart_port *port)
2682 {
2683 return port->cons && port->cons->index == port->line;
2684 }
2685
2686 #else
2687 #define ATMEL_CONSOLE_DEVICE NULL
2688
2689 static inline bool atmel_is_console_port(struct uart_port *port)
2690 {
2691 return false;
2692 }
2693 #endif
2694
2695 static struct uart_driver atmel_uart = {
2696 .owner = THIS_MODULE,
2697 .driver_name = "atmel_serial",
2698 .dev_name = ATMEL_DEVICENAME,
2699 .major = SERIAL_ATMEL_MAJOR,
2700 .minor = MINOR_START,
2701 .nr = ATMEL_MAX_UART,
2702 .cons = ATMEL_CONSOLE_DEVICE,
2703 };
2704
2705 #ifdef CONFIG_PM
2706 static bool atmel_serial_clk_will_stop(void)
2707 {
2708 #ifdef CONFIG_ARCH_AT91
2709 return at91_suspend_entering_slow_clock();
2710 #else
2711 return false;
2712 #endif
2713 }
2714
2715 static int atmel_serial_suspend(struct platform_device *pdev,
2716 pm_message_t state)
2717 {
2718 struct uart_port *port = platform_get_drvdata(pdev);
2719 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2720
2721 if (atmel_is_console_port(port) && console_suspend_enabled) {
2722 /* Drain the TX shifter */
2723 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2724 ATMEL_US_TXEMPTY))
2725 cpu_relax();
2726 }
2727
2728 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2729 /* Cache register values as we won't get a full shutdown/startup
2730 * cycle
2731 */
2732 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2733 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2734 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2735 atmel_port->cache.rtor = atmel_uart_readl(port,
2736 atmel_port->rtor);
2737 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2738 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2739 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2740 }
2741
2742 /* we can not wake up if we're running on slow clock */
2743 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2744 if (atmel_serial_clk_will_stop()) {
2745 unsigned long flags;
2746
2747 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2748 atmel_port->suspended = true;
2749 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2750 device_set_wakeup_enable(&pdev->dev, 0);
2751 }
2752
2753 uart_suspend_port(&atmel_uart, port);
2754
2755 return 0;
2756 }
2757
2758 static int atmel_serial_resume(struct platform_device *pdev)
2759 {
2760 struct uart_port *port = platform_get_drvdata(pdev);
2761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2762 unsigned long flags;
2763
2764 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2765 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2766 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2767 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2768 atmel_uart_writel(port, atmel_port->rtor,
2769 atmel_port->cache.rtor);
2770 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2771
2772 if (atmel_port->fifo_size) {
2773 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2774 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2775 atmel_uart_writel(port, ATMEL_US_FMR,
2776 atmel_port->cache.fmr);
2777 atmel_uart_writel(port, ATMEL_US_FIER,
2778 atmel_port->cache.fimr);
2779 }
2780 atmel_start_rx(port);
2781 }
2782
2783 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2784 if (atmel_port->pending) {
2785 atmel_handle_receive(port, atmel_port->pending);
2786 atmel_handle_status(port, atmel_port->pending,
2787 atmel_port->pending_status);
2788 atmel_handle_transmit(port, atmel_port->pending);
2789 atmel_port->pending = 0;
2790 }
2791 atmel_port->suspended = false;
2792 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2793
2794 uart_resume_port(&atmel_uart, port);
2795 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2796
2797 return 0;
2798 }
2799 #else
2800 #define atmel_serial_suspend NULL
2801 #define atmel_serial_resume NULL
2802 #endif
2803
2804 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2805 struct platform_device *pdev)
2806 {
2807 atmel_port->fifo_size = 0;
2808 atmel_port->rts_low = 0;
2809 atmel_port->rts_high = 0;
2810
2811 if (of_property_read_u32(pdev->dev.of_node,
2812 "atmel,fifo-size",
2813 &atmel_port->fifo_size))
2814 return;
2815
2816 if (!atmel_port->fifo_size)
2817 return;
2818
2819 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2820 atmel_port->fifo_size = 0;
2821 dev_err(&pdev->dev, "Invalid FIFO size\n");
2822 return;
2823 }
2824
2825 /*
2826 * 0 <= rts_low <= rts_high <= fifo_size
2827 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2828 * to flush their internal TX FIFO, commonly up to 16 data, before
2829 * actually stopping to send new data. So we try to set the RTS High
2830 * Threshold to a reasonably high value respecting this 16 data
2831 * empirical rule when possible.
2832 */
2833 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2834 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2835 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2836 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2837
2838 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2839 atmel_port->fifo_size);
2840 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2841 atmel_port->rts_high);
2842 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2843 atmel_port->rts_low);
2844 }
2845
2846 static int atmel_serial_probe(struct platform_device *pdev)
2847 {
2848 struct atmel_uart_port *atmel_port;
2849 struct device_node *np = pdev->dev.parent->of_node;
2850 void *data;
2851 int ret;
2852 bool rs485_enabled;
2853
2854 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2855
2856 /*
2857 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2858 * as compatible string. This driver is probed by at91-usart mfd driver
2859 * which is just a wrapper over the atmel_serial driver and
2860 * spi-at91-usart driver. All attributes needed by this driver are
2861 * found in of_node of parent.
2862 */
2863 pdev->dev.of_node = np;
2864
2865 ret = of_alias_get_id(np, "serial");
2866 if (ret < 0)
2867 /* port id not found in platform data nor device-tree aliases:
2868 * auto-enumerate it */
2869 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2870
2871 if (ret >= ATMEL_MAX_UART) {
2872 ret = -ENODEV;
2873 goto err;
2874 }
2875
2876 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2877 /* port already in use */
2878 ret = -EBUSY;
2879 goto err;
2880 }
2881
2882 atmel_port = &atmel_ports[ret];
2883 atmel_port->backup_imr = 0;
2884 atmel_port->uart.line = ret;
2885 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2886 atmel_serial_probe_fifos(atmel_port, pdev);
2887
2888 atomic_set(&atmel_port->tasklet_shutdown, 0);
2889 spin_lock_init(&atmel_port->lock_suspended);
2890
2891 ret = atmel_init_port(atmel_port, pdev);
2892 if (ret)
2893 goto err_clear_bit;
2894
2895 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2896 if (IS_ERR(atmel_port->gpios)) {
2897 ret = PTR_ERR(atmel_port->gpios);
2898 goto err_clear_bit;
2899 }
2900
2901 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2902 ret = -ENOMEM;
2903 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2904 sizeof(struct atmel_uart_char),
2905 GFP_KERNEL);
2906 if (!data)
2907 goto err_alloc_ring;
2908 atmel_port->rx_ring.buf = data;
2909 }
2910
2911 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2912
2913 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2914 if (ret)
2915 goto err_add_port;
2916
2917 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2918 if (atmel_is_console_port(&atmel_port->uart)
2919 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2920 /*
2921 * The serial core enabled the clock for us, so undo
2922 * the clk_prepare_enable() in atmel_console_setup()
2923 */
2924 clk_disable_unprepare(atmel_port->clk);
2925 }
2926 #endif
2927
2928 device_init_wakeup(&pdev->dev, 1);
2929 platform_set_drvdata(pdev, atmel_port);
2930
2931 /*
2932 * The peripheral clock has been disabled by atmel_init_port():
2933 * enable it before accessing I/O registers
2934 */
2935 clk_prepare_enable(atmel_port->clk);
2936
2937 if (rs485_enabled) {
2938 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2939 ATMEL_US_USMODE_NORMAL);
2940 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2941 ATMEL_US_RTSEN);
2942 }
2943
2944 /*
2945 * Get port name of usart or uart
2946 */
2947 atmel_get_ip_name(&atmel_port->uart);
2948
2949 /*
2950 * The peripheral clock can now safely be disabled till the port
2951 * is used
2952 */
2953 clk_disable_unprepare(atmel_port->clk);
2954
2955 return 0;
2956
2957 err_add_port:
2958 kfree(atmel_port->rx_ring.buf);
2959 atmel_port->rx_ring.buf = NULL;
2960 err_alloc_ring:
2961 if (!atmel_is_console_port(&atmel_port->uart)) {
2962 clk_put(atmel_port->clk);
2963 atmel_port->clk = NULL;
2964 }
2965 err_clear_bit:
2966 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2967 err:
2968 return ret;
2969 }
2970
2971 /*
2972 * Even if the driver is not modular, it makes sense to be able to
2973 * unbind a device: there can be many bound devices, and there are
2974 * situations where dynamic binding and unbinding can be useful.
2975 *
2976 * For example, a connected device can require a specific firmware update
2977 * protocol that needs bitbanging on IO lines, but use the regular serial
2978 * port in the normal case.
2979 */
2980 static int atmel_serial_remove(struct platform_device *pdev)
2981 {
2982 struct uart_port *port = platform_get_drvdata(pdev);
2983 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2984 int ret = 0;
2985
2986 tasklet_kill(&atmel_port->tasklet_rx);
2987 tasklet_kill(&atmel_port->tasklet_tx);
2988
2989 device_init_wakeup(&pdev->dev, 0);
2990
2991 ret = uart_remove_one_port(&atmel_uart, port);
2992
2993 kfree(atmel_port->rx_ring.buf);
2994
2995 /* "port" is allocated statically, so we shouldn't free it */
2996
2997 clear_bit(port->line, atmel_ports_in_use);
2998
2999 clk_put(atmel_port->clk);
3000 atmel_port->clk = NULL;
3001 pdev->dev.of_node = NULL;
3002
3003 return ret;
3004 }
3005
3006 static struct platform_driver atmel_serial_driver = {
3007 .probe = atmel_serial_probe,
3008 .remove = atmel_serial_remove,
3009 .suspend = atmel_serial_suspend,
3010 .resume = atmel_serial_resume,
3011 .driver = {
3012 .name = "atmel_usart_serial",
3013 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
3014 },
3015 };
3016
3017 static int __init atmel_serial_init(void)
3018 {
3019 int ret;
3020
3021 ret = uart_register_driver(&atmel_uart);
3022 if (ret)
3023 return ret;
3024
3025 ret = platform_driver_register(&atmel_serial_driver);
3026 if (ret)
3027 uart_unregister_driver(&atmel_uart);
3028
3029 return ret;
3030 }
3031 device_initcall(atmel_serial_init);
Linux with added FPC-III support