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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / tty / serial / omap-serial.c
blob48017cec7f2fb5abba42a1b109b6f346e8bc3580
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:
9 * Govindraj R <govindraj.raja@ti.com>
10 * Thara Gopinath <thara@ti.com>
11 *
12 * Note: This driver is made separate from 8250 driver as we cannot
13 * over load 8250 driver with omap platform specific configuration for
14 * features like DMA, it makes easier to implement features like DMA and
15 * hardware flow control and software flow control configuration with
16 * this driver as required for the omap-platform.
17 */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/console.h>
22 #include <linux/serial_reg.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/clk.h>
30 #include <linux/serial_core.h>
31 #include <linux/irq.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/of.h>
35 #include <linux/of_irq.h>
36 #include <linux/gpio.h>
37 #include <linux/of_gpio.h>
38 #include <linux/platform_data/serial-omap.h>
39
40 #include <dt-bindings/gpio/gpio.h>
41
42 #define OMAP_MAX_HSUART_PORTS 10
43
44 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
45
46 #define OMAP_UART_REV_42 0x0402
47 #define OMAP_UART_REV_46 0x0406
48 #define OMAP_UART_REV_52 0x0502
49 #define OMAP_UART_REV_63 0x0603
50
51 #define OMAP_UART_TX_WAKEUP_EN BIT(7)
52
53 /* Feature flags */
54 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
55
56 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
57 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
58
59 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
60
61 /* SCR register bitmasks */
62 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
63 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
64 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
65
66 /* FCR register bitmasks */
67 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
68 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
69
70 /* MVR register bitmasks */
71 #define OMAP_UART_MVR_SCHEME_SHIFT 30
72
73 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
74 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
75 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
76
77 #define OMAP_UART_MVR_MAJ_MASK 0x700
78 #define OMAP_UART_MVR_MAJ_SHIFT 8
79 #define OMAP_UART_MVR_MIN_MASK 0x3f
80
81 #define OMAP_UART_DMA_CH_FREE -1
82
83 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
84 #define OMAP_MODE13X_SPEED 230400
85
86 /* WER = 0x7F
87 * Enable module level wakeup in WER reg
88 */
89 #define OMAP_UART_WER_MOD_WKUP 0x7F
90
91 /* Enable XON/XOFF flow control on output */
92 #define OMAP_UART_SW_TX 0x08
93
94 /* Enable XON/XOFF flow control on input */
95 #define OMAP_UART_SW_RX 0x02
96
97 #define OMAP_UART_SW_CLR 0xF0
98
99 #define OMAP_UART_TCR_TRIG 0x0F
100
101 struct uart_omap_dma {
102 u8 uart_dma_tx;
103 u8 uart_dma_rx;
104 int rx_dma_channel;
105 int tx_dma_channel;
106 dma_addr_t rx_buf_dma_phys;
107 dma_addr_t tx_buf_dma_phys;
108 unsigned int uart_base;
109 /*
110 * Buffer for rx dma. It is not required for tx because the buffer
111 * comes from port structure.
112 */
113 unsigned char *rx_buf;
114 unsigned int prev_rx_dma_pos;
115 int tx_buf_size;
116 int tx_dma_used;
117 int rx_dma_used;
118 spinlock_t tx_lock;
119 spinlock_t rx_lock;
120 /* timer to poll activity on rx dma */
121 struct timer_list rx_timer;
122 unsigned int rx_buf_size;
123 unsigned int rx_poll_rate;
124 unsigned int rx_timeout;
125 };
126
127 struct uart_omap_port {
128 struct uart_port port;
129 struct uart_omap_dma uart_dma;
130 struct device *dev;
131 int wakeirq;
132
133 unsigned char ier;
134 unsigned char lcr;
135 unsigned char mcr;
136 unsigned char fcr;
137 unsigned char efr;
138 unsigned char dll;
139 unsigned char dlh;
140 unsigned char mdr1;
141 unsigned char scr;
142 unsigned char wer;
143
144 int use_dma;
145 /*
146 * Some bits in registers are cleared on a read, so they must
147 * be saved whenever the register is read, but the bits will not
148 * be immediately processed.
149 */
150 unsigned int lsr_break_flag;
151 unsigned char msr_saved_flags;
152 char name[20];
153 unsigned long port_activity;
154 int context_loss_cnt;
155 u32 errata;
156 u32 features;
157
158 int rts_gpio;
159
160 struct pm_qos_request pm_qos_request;
161 u32 latency;
162 u32 calc_latency;
163 struct work_struct qos_work;
164 bool is_suspending;
165 };
166
167 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
168
169 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
170
171 /* Forward declaration of functions */
172 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
173
174 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
175 {
176 offset <<= up->port.regshift;
177 return readw(up->port.membase + offset);
178 }
179
180 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
181 {
182 offset <<= up->port.regshift;
183 writew(value, up->port.membase + offset);
184 }
185
186 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
187 {
188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
190 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
191 serial_out(up, UART_FCR, 0);
192 }
193
194 #ifdef CONFIG_PM
195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
196 {
197 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
198
199 if (!pdata || !pdata->get_context_loss_count)
200 return -EINVAL;
201
202 return pdata->get_context_loss_count(up->dev);
203 }
204
205 /* REVISIT: Remove this when omap3 boots in device tree only mode */
206 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
207 {
208 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
209
210 if (!pdata || !pdata->enable_wakeup)
211 return;
212
213 pdata->enable_wakeup(up->dev, enable);
214 }
215 #endif /* CONFIG_PM */
216
217 /*
218 * Calculate the absolute difference between the desired and actual baud
219 * rate for the given mode.
220 */
221 static inline int calculate_baud_abs_diff(struct uart_port *port,
222 unsigned int baud, unsigned int mode)
223 {
224 unsigned int n = port->uartclk / (mode * baud);
225 int abs_diff;
226
227 if (n == 0)
228 n = 1;
229
230 abs_diff = baud - (port->uartclk / (mode * n));
231 if (abs_diff < 0)
232 abs_diff = -abs_diff;
233
234 return abs_diff;
235 }
236
237 /*
238 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
239 * @port: uart port info
240 * @baud: baudrate for which mode needs to be determined
241 *
242 * Returns true if baud rate is MODE16X and false if MODE13X
243 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
244 * and Error Rates" determines modes not for all common baud rates.
245 * E.g. for 1000000 baud rate mode must be 16x, but according to that
246 * table it's determined as 13x.
247 */
248 static bool
249 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
250 {
251 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
252 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
253
254 return (abs_diff_13 >= abs_diff_16);
255 }
256
257 /*
258 * serial_omap_get_divisor - calculate divisor value
259 * @port: uart port info
260 * @baud: baudrate for which divisor needs to be calculated.
261 */
262 static unsigned int
263 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
264 {
265 unsigned int mode;
266
267 if (!serial_omap_baud_is_mode16(port, baud))
268 mode = 13;
269 else
270 mode = 16;
271 return port->uartclk/(mode * baud);
272 }
273
274 static void serial_omap_enable_ms(struct uart_port *port)
275 {
276 struct uart_omap_port *up = to_uart_omap_port(port);
277
278 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
279
280 pm_runtime_get_sync(up->dev);
281 up->ier |= UART_IER_MSI;
282 serial_out(up, UART_IER, up->ier);
283 pm_runtime_mark_last_busy(up->dev);
284 pm_runtime_put_autosuspend(up->dev);
285 }
286
287 static void serial_omap_stop_tx(struct uart_port *port)
288 {
289 struct uart_omap_port *up = to_uart_omap_port(port);
290 int res;
291
292 pm_runtime_get_sync(up->dev);
293
294 /* Handle RS-485 */
295 if (port->rs485.flags & SER_RS485_ENABLED) {
296 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
297 /* THR interrupt is fired when both TX FIFO and TX
298 * shift register are empty. This means there's nothing
299 * left to transmit now, so make sure the THR interrupt
300 * is fired when TX FIFO is below the trigger level,
301 * disable THR interrupts and toggle the RS-485 GPIO
302 * data direction pin if needed.
303 */
304 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
305 serial_out(up, UART_OMAP_SCR, up->scr);
306 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
307 1 : 0;
308 if (gpio_get_value(up->rts_gpio) != res) {
309 if (port->rs485.delay_rts_after_send > 0)
310 mdelay(
311 port->rs485.delay_rts_after_send);
312 gpio_set_value(up->rts_gpio, res);
313 }
314 } else {
315 /* We're asked to stop, but there's still stuff in the
316 * UART FIFO, so make sure the THR interrupt is fired
317 * when both TX FIFO and TX shift register are empty.
318 * The next THR interrupt (if no transmission is started
319 * in the meantime) will indicate the end of a
320 * transmission. Therefore we _don't_ disable THR
321 * interrupts in this situation.
322 */
323 up->scr |= OMAP_UART_SCR_TX_EMPTY;
324 serial_out(up, UART_OMAP_SCR, up->scr);
325 return;
326 }
327 }
328
329 if (up->ier & UART_IER_THRI) {
330 up->ier &= ~UART_IER_THRI;
331 serial_out(up, UART_IER, up->ier);
332 }
333
334 if ((port->rs485.flags & SER_RS485_ENABLED) &&
335 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
336 /*
337 * Empty the RX FIFO, we are not interested in anything
338 * received during the half-duplex transmission.
339 */
340 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
341 /* Re-enable RX interrupts */
342 up->ier |= UART_IER_RLSI | UART_IER_RDI;
343 up->port.read_status_mask |= UART_LSR_DR;
344 serial_out(up, UART_IER, up->ier);
345 }
346
347 pm_runtime_mark_last_busy(up->dev);
348 pm_runtime_put_autosuspend(up->dev);
349 }
350
351 static void serial_omap_stop_rx(struct uart_port *port)
352 {
353 struct uart_omap_port *up = to_uart_omap_port(port);
354
355 pm_runtime_get_sync(up->dev);
356 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
357 up->port.read_status_mask &= ~UART_LSR_DR;
358 serial_out(up, UART_IER, up->ier);
359 pm_runtime_mark_last_busy(up->dev);
360 pm_runtime_put_autosuspend(up->dev);
361 }
362
363 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
364 {
365 struct circ_buf *xmit = &up->port.state->xmit;
366 int count;
367
368 if (up->port.x_char) {
369 serial_out(up, UART_TX, up->port.x_char);
370 up->port.icount.tx++;
371 up->port.x_char = 0;
372 return;
373 }
374 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
375 serial_omap_stop_tx(&up->port);
376 return;
377 }
378 count = up->port.fifosize / 4;
379 do {
380 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
381 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
382 up->port.icount.tx++;
383 if (uart_circ_empty(xmit))
384 break;
385 } while (--count > 0);
386
387 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
388 uart_write_wakeup(&up->port);
389
390 if (uart_circ_empty(xmit))
391 serial_omap_stop_tx(&up->port);
392 }
393
394 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
395 {
396 if (!(up->ier & UART_IER_THRI)) {
397 up->ier |= UART_IER_THRI;
398 serial_out(up, UART_IER, up->ier);
399 }
400 }
401
402 static void serial_omap_start_tx(struct uart_port *port)
403 {
404 struct uart_omap_port *up = to_uart_omap_port(port);
405 int res;
406
407 pm_runtime_get_sync(up->dev);
408
409 /* Handle RS-485 */
410 if (port->rs485.flags & SER_RS485_ENABLED) {
411 /* Fire THR interrupts when FIFO is below trigger level */
412 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
413 serial_out(up, UART_OMAP_SCR, up->scr);
414
415 /* if rts not already enabled */
416 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
417 if (gpio_get_value(up->rts_gpio) != res) {
418 gpio_set_value(up->rts_gpio, res);
419 if (port->rs485.delay_rts_before_send > 0)
420 mdelay(port->rs485.delay_rts_before_send);
421 }
422 }
423
424 if ((port->rs485.flags & SER_RS485_ENABLED) &&
425 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
426 serial_omap_stop_rx(port);
427
428 serial_omap_enable_ier_thri(up);
429 pm_runtime_mark_last_busy(up->dev);
430 pm_runtime_put_autosuspend(up->dev);
431 }
432
433 static void serial_omap_throttle(struct uart_port *port)
434 {
435 struct uart_omap_port *up = to_uart_omap_port(port);
436 unsigned long flags;
437
438 pm_runtime_get_sync(up->dev);
439 spin_lock_irqsave(&up->port.lock, flags);
440 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
441 serial_out(up, UART_IER, up->ier);
442 spin_unlock_irqrestore(&up->port.lock, flags);
443 pm_runtime_mark_last_busy(up->dev);
444 pm_runtime_put_autosuspend(up->dev);
445 }
446
447 static void serial_omap_unthrottle(struct uart_port *port)
448 {
449 struct uart_omap_port *up = to_uart_omap_port(port);
450 unsigned long flags;
451
452 pm_runtime_get_sync(up->dev);
453 spin_lock_irqsave(&up->port.lock, flags);
454 up->ier |= UART_IER_RLSI | UART_IER_RDI;
455 serial_out(up, UART_IER, up->ier);
456 spin_unlock_irqrestore(&up->port.lock, flags);
457 pm_runtime_mark_last_busy(up->dev);
458 pm_runtime_put_autosuspend(up->dev);
459 }
460
461 static unsigned int check_modem_status(struct uart_omap_port *up)
462 {
463 unsigned int status;
464
465 status = serial_in(up, UART_MSR);
466 status |= up->msr_saved_flags;
467 up->msr_saved_flags = 0;
468 if ((status & UART_MSR_ANY_DELTA) == 0)
469 return status;
470
471 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
472 up->port.state != NULL) {
473 if (status & UART_MSR_TERI)
474 up->port.icount.rng++;
475 if (status & UART_MSR_DDSR)
476 up->port.icount.dsr++;
477 if (status & UART_MSR_DDCD)
478 uart_handle_dcd_change
479 (&up->port, status & UART_MSR_DCD);
480 if (status & UART_MSR_DCTS)
481 uart_handle_cts_change
482 (&up->port, status & UART_MSR_CTS);
483 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
484 }
485
486 return status;
487 }
488
489 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
490 {
491 unsigned int flag;
492
493 /*
494 * Read one data character out to avoid stalling the receiver according
495 * to the table 23-246 of the omap4 TRM.
496 */
497 if (likely(lsr & UART_LSR_DR))
498 serial_in(up, UART_RX);
499
500 up->port.icount.rx++;
501 flag = TTY_NORMAL;
502
503 if (lsr & UART_LSR_BI) {
504 flag = TTY_BREAK;
505 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
506 up->port.icount.brk++;
507 /*
508 * We do the SysRQ and SAK checking
509 * here because otherwise the break
510 * may get masked by ignore_status_mask
511 * or read_status_mask.
512 */
513 if (uart_handle_break(&up->port))
514 return;
515
516 }
517
518 if (lsr & UART_LSR_PE) {
519 flag = TTY_PARITY;
520 up->port.icount.parity++;
521 }
522
523 if (lsr & UART_LSR_FE) {
524 flag = TTY_FRAME;
525 up->port.icount.frame++;
526 }
527
528 if (lsr & UART_LSR_OE)
529 up->port.icount.overrun++;
530
531 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
532 if (up->port.line == up->port.cons->index) {
533 /* Recover the break flag from console xmit */
534 lsr |= up->lsr_break_flag;
535 }
536 #endif
537 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
538 }
539
540 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
541 {
542 unsigned char ch = 0;
543 unsigned int flag;
544
545 if (!(lsr & UART_LSR_DR))
546 return;
547
548 ch = serial_in(up, UART_RX);
549 flag = TTY_NORMAL;
550 up->port.icount.rx++;
551
552 if (uart_handle_sysrq_char(&up->port, ch))
553 return;
554
555 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
556 }
557
558 /**
559 * serial_omap_irq() - This handles the interrupt from one port
560 * @irq: uart port irq number
561 * @dev_id: uart port info
562 */
563 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
564 {
565 struct uart_omap_port *up = dev_id;
566 unsigned int iir, lsr;
567 unsigned int type;
568 irqreturn_t ret = IRQ_NONE;
569 int max_count = 256;
570
571 spin_lock(&up->port.lock);
572 pm_runtime_get_sync(up->dev);
573
574 do {
575 iir = serial_in(up, UART_IIR);
576 if (iir & UART_IIR_NO_INT)
577 break;
578
579 ret = IRQ_HANDLED;
580 lsr = serial_in(up, UART_LSR);
581
582 /* extract IRQ type from IIR register */
583 type = iir & 0x3e;
584
585 switch (type) {
586 case UART_IIR_MSI:
587 check_modem_status(up);
588 break;
589 case UART_IIR_THRI:
590 transmit_chars(up, lsr);
591 break;
592 case UART_IIR_RX_TIMEOUT:
593 /* FALLTHROUGH */
594 case UART_IIR_RDI:
595 serial_omap_rdi(up, lsr);
596 break;
597 case UART_IIR_RLSI:
598 serial_omap_rlsi(up, lsr);
599 break;
600 case UART_IIR_CTS_RTS_DSR:
601 /* simply try again */
602 break;
603 case UART_IIR_XOFF:
604 /* FALLTHROUGH */
605 default:
606 break;
607 }
608 } while (max_count--);
609
610 spin_unlock(&up->port.lock);
611
612 tty_flip_buffer_push(&up->port.state->port);
613
614 pm_runtime_mark_last_busy(up->dev);
615 pm_runtime_put_autosuspend(up->dev);
616 up->port_activity = jiffies;
617
618 return ret;
619 }
620
621 static unsigned int serial_omap_tx_empty(struct uart_port *port)
622 {
623 struct uart_omap_port *up = to_uart_omap_port(port);
624 unsigned long flags = 0;
625 unsigned int ret = 0;
626
627 pm_runtime_get_sync(up->dev);
628 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
629 spin_lock_irqsave(&up->port.lock, flags);
630 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
631 spin_unlock_irqrestore(&up->port.lock, flags);
632 pm_runtime_mark_last_busy(up->dev);
633 pm_runtime_put_autosuspend(up->dev);
634 return ret;
635 }
636
637 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
638 {
639 struct uart_omap_port *up = to_uart_omap_port(port);
640 unsigned int status;
641 unsigned int ret = 0;
642
643 pm_runtime_get_sync(up->dev);
644 status = check_modem_status(up);
645 pm_runtime_mark_last_busy(up->dev);
646 pm_runtime_put_autosuspend(up->dev);
647
648 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
649
650 if (status & UART_MSR_DCD)
651 ret |= TIOCM_CAR;
652 if (status & UART_MSR_RI)
653 ret |= TIOCM_RNG;
654 if (status & UART_MSR_DSR)
655 ret |= TIOCM_DSR;
656 if (status & UART_MSR_CTS)
657 ret |= TIOCM_CTS;
658 return ret;
659 }
660
661 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
662 {
663 struct uart_omap_port *up = to_uart_omap_port(port);
664 unsigned char mcr = 0, old_mcr, lcr;
665
666 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
667 if (mctrl & TIOCM_RTS)
668 mcr |= UART_MCR_RTS;
669 if (mctrl & TIOCM_DTR)
670 mcr |= UART_MCR_DTR;
671 if (mctrl & TIOCM_OUT1)
672 mcr |= UART_MCR_OUT1;
673 if (mctrl & TIOCM_OUT2)
674 mcr |= UART_MCR_OUT2;
675 if (mctrl & TIOCM_LOOP)
676 mcr |= UART_MCR_LOOP;
677
678 pm_runtime_get_sync(up->dev);
679 old_mcr = serial_in(up, UART_MCR);
680 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
681 UART_MCR_DTR | UART_MCR_RTS);
682 up->mcr = old_mcr | mcr;
683 serial_out(up, UART_MCR, up->mcr);
684
685 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
686 lcr = serial_in(up, UART_LCR);
687 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
688 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
689 up->efr |= UART_EFR_RTS;
690 else
691 up->efr &= ~UART_EFR_RTS;
692 serial_out(up, UART_EFR, up->efr);
693 serial_out(up, UART_LCR, lcr);
694
695 pm_runtime_mark_last_busy(up->dev);
696 pm_runtime_put_autosuspend(up->dev);
697 }
698
699 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
700 {
701 struct uart_omap_port *up = to_uart_omap_port(port);
702 unsigned long flags = 0;
703
704 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
705 pm_runtime_get_sync(up->dev);
706 spin_lock_irqsave(&up->port.lock, flags);
707 if (break_state == -1)
708 up->lcr |= UART_LCR_SBC;
709 else
710 up->lcr &= ~UART_LCR_SBC;
711 serial_out(up, UART_LCR, up->lcr);
712 spin_unlock_irqrestore(&up->port.lock, flags);
713 pm_runtime_mark_last_busy(up->dev);
714 pm_runtime_put_autosuspend(up->dev);
715 }
716
717 static int serial_omap_startup(struct uart_port *port)
718 {
719 struct uart_omap_port *up = to_uart_omap_port(port);
720 unsigned long flags = 0;
721 int retval;
722
723 /*
724 * Allocate the IRQ
725 */
726 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
727 up->name, up);
728 if (retval)
729 return retval;
730
731 /* Optional wake-up IRQ */
732 if (up->wakeirq) {
733 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
734 if (retval) {
735 free_irq(up->port.irq, up);
736 return retval;
737 }
738 }
739
740 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
741
742 pm_runtime_get_sync(up->dev);
743 /*
744 * Clear the FIFO buffers and disable them.
745 * (they will be reenabled in set_termios())
746 */
747 serial_omap_clear_fifos(up);
748
749 /*
750 * Clear the interrupt registers.
751 */
752 (void) serial_in(up, UART_LSR);
753 if (serial_in(up, UART_LSR) & UART_LSR_DR)
754 (void) serial_in(up, UART_RX);
755 (void) serial_in(up, UART_IIR);
756 (void) serial_in(up, UART_MSR);
757
758 /*
759 * Now, initialize the UART
760 */
761 serial_out(up, UART_LCR, UART_LCR_WLEN8);
762 spin_lock_irqsave(&up->port.lock, flags);
763 /*
764 * Most PC uarts need OUT2 raised to enable interrupts.
765 */
766 up->port.mctrl |= TIOCM_OUT2;
767 serial_omap_set_mctrl(&up->port, up->port.mctrl);
768 spin_unlock_irqrestore(&up->port.lock, flags);
769
770 up->msr_saved_flags = 0;
771 /*
772 * Finally, enable interrupts. Note: Modem status interrupts
773 * are set via set_termios(), which will be occurring imminently
774 * anyway, so we don't enable them here.
775 */
776 up->ier = UART_IER_RLSI | UART_IER_RDI;
777 serial_out(up, UART_IER, up->ier);
778
779 /* Enable module level wake up */
780 up->wer = OMAP_UART_WER_MOD_WKUP;
781 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
782 up->wer |= OMAP_UART_TX_WAKEUP_EN;
783
784 serial_out(up, UART_OMAP_WER, up->wer);
785
786 pm_runtime_mark_last_busy(up->dev);
787 pm_runtime_put_autosuspend(up->dev);
788 up->port_activity = jiffies;
789 return 0;
790 }
791
792 static void serial_omap_shutdown(struct uart_port *port)
793 {
794 struct uart_omap_port *up = to_uart_omap_port(port);
795 unsigned long flags = 0;
796
797 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
798
799 pm_runtime_get_sync(up->dev);
800 /*
801 * Disable interrupts from this port
802 */
803 up->ier = 0;
804 serial_out(up, UART_IER, 0);
805
806 spin_lock_irqsave(&up->port.lock, flags);
807 up->port.mctrl &= ~TIOCM_OUT2;
808 serial_omap_set_mctrl(&up->port, up->port.mctrl);
809 spin_unlock_irqrestore(&up->port.lock, flags);
810
811 /*
812 * Disable break condition and FIFOs
813 */
814 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
815 serial_omap_clear_fifos(up);
816
817 /*
818 * Read data port to reset things, and then free the irq
819 */
820 if (serial_in(up, UART_LSR) & UART_LSR_DR)
821 (void) serial_in(up, UART_RX);
822
823 pm_runtime_mark_last_busy(up->dev);
824 pm_runtime_put_autosuspend(up->dev);
825 free_irq(up->port.irq, up);
826 dev_pm_clear_wake_irq(up->dev);
827 }
828
829 static void serial_omap_uart_qos_work(struct work_struct *work)
830 {
831 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
832 qos_work);
833
834 pm_qos_update_request(&up->pm_qos_request, up->latency);
835 }
836
837 static void
838 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
839 struct ktermios *old)
840 {
841 struct uart_omap_port *up = to_uart_omap_port(port);
842 unsigned char cval = 0;
843 unsigned long flags = 0;
844 unsigned int baud, quot;
845
846 switch (termios->c_cflag & CSIZE) {
847 case CS5:
848 cval = UART_LCR_WLEN5;
849 break;
850 case CS6:
851 cval = UART_LCR_WLEN6;
852 break;
853 case CS7:
854 cval = UART_LCR_WLEN7;
855 break;
856 default:
857 case CS8:
858 cval = UART_LCR_WLEN8;
859 break;
860 }
861
862 if (termios->c_cflag & CSTOPB)
863 cval |= UART_LCR_STOP;
864 if (termios->c_cflag & PARENB)
865 cval |= UART_LCR_PARITY;
866 if (!(termios->c_cflag & PARODD))
867 cval |= UART_LCR_EPAR;
868 if (termios->c_cflag & CMSPAR)
869 cval |= UART_LCR_SPAR;
870
871 /*
872 * Ask the core to calculate the divisor for us.
873 */
874
875 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
876 quot = serial_omap_get_divisor(port, baud);
877
878 /* calculate wakeup latency constraint */
879 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
880 up->latency = up->calc_latency;
881 schedule_work(&up->qos_work);
882
883 up->dll = quot & 0xff;
884 up->dlh = quot >> 8;
885 up->mdr1 = UART_OMAP_MDR1_DISABLE;
886
887 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
888 UART_FCR_ENABLE_FIFO;
889
890 /*
891 * Ok, we're now changing the port state. Do it with
892 * interrupts disabled.
893 */
894 pm_runtime_get_sync(up->dev);
895 spin_lock_irqsave(&up->port.lock, flags);
896
897 /*
898 * Update the per-port timeout.
899 */
900 uart_update_timeout(port, termios->c_cflag, baud);
901
902 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
903 if (termios->c_iflag & INPCK)
904 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
905 if (termios->c_iflag & (BRKINT | PARMRK))
906 up->port.read_status_mask |= UART_LSR_BI;
907
908 /*
909 * Characters to ignore
910 */
911 up->port.ignore_status_mask = 0;
912 if (termios->c_iflag & IGNPAR)
913 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
914 if (termios->c_iflag & IGNBRK) {
915 up->port.ignore_status_mask |= UART_LSR_BI;
916 /*
917 * If we're ignoring parity and break indicators,
918 * ignore overruns too (for real raw support).
919 */
920 if (termios->c_iflag & IGNPAR)
921 up->port.ignore_status_mask |= UART_LSR_OE;
922 }
923
924 /*
925 * ignore all characters if CREAD is not set
926 */
927 if ((termios->c_cflag & CREAD) == 0)
928 up->port.ignore_status_mask |= UART_LSR_DR;
929
930 /*
931 * Modem status interrupts
932 */
933 up->ier &= ~UART_IER_MSI;
934 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
935 up->ier |= UART_IER_MSI;
936 serial_out(up, UART_IER, up->ier);
937 serial_out(up, UART_LCR, cval); /* reset DLAB */
938 up->lcr = cval;
939 up->scr = 0;
940
941 /* FIFOs and DMA Settings */
942
943 /* FCR can be changed only when the
944 * baud clock is not running
945 * DLL_REG and DLH_REG set to 0.
946 */
947 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
948 serial_out(up, UART_DLL, 0);
949 serial_out(up, UART_DLM, 0);
950 serial_out(up, UART_LCR, 0);
951
952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
953
954 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
955 up->efr &= ~UART_EFR_SCD;
956 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
957
958 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
959 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
960 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
961 /* FIFO ENABLE, DMA MODE */
962
963 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
964 /*
965 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
966 * sets Enables the granularity of 1 for TRIGGER RX
967 * level. Along with setting RX FIFO trigger level
968 * to 1 (as noted below, 16 characters) and TLR[3:0]
969 * to zero this will result RX FIFO threshold level
970 * to 1 character, instead of 16 as noted in comment
971 * below.
972 */
973
974 /* Set receive FIFO threshold to 16 characters and
975 * transmit FIFO threshold to 32 spaces
976 */
977 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
978 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
979 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
980 UART_FCR_ENABLE_FIFO;
981
982 serial_out(up, UART_FCR, up->fcr);
983 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
984
985 serial_out(up, UART_OMAP_SCR, up->scr);
986
987 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
989 serial_out(up, UART_MCR, up->mcr);
990 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
991 serial_out(up, UART_EFR, up->efr);
992 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
993
994 /* Protocol, Baud Rate, and Interrupt Settings */
995
996 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
997 serial_omap_mdr1_errataset(up, up->mdr1);
998 else
999 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1000
1001 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1002 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1003
1004 serial_out(up, UART_LCR, 0);
1005 serial_out(up, UART_IER, 0);
1006 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1007
1008 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1009 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1010
1011 serial_out(up, UART_LCR, 0);
1012 serial_out(up, UART_IER, up->ier);
1013 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1014
1015 serial_out(up, UART_EFR, up->efr);
1016 serial_out(up, UART_LCR, cval);
1017
1018 if (!serial_omap_baud_is_mode16(port, baud))
1019 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1020 else
1021 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1022
1023 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1024 serial_omap_mdr1_errataset(up, up->mdr1);
1025 else
1026 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1027
1028 /* Configure flow control */
1029 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1030
1031 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1032 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1033 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1034
1035 /* Enable access to TCR/TLR */
1036 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1037 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1038 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1039
1040 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1041
1042 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1043
1044 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1045 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1046 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1047 up->efr |= UART_EFR_CTS;
1048 } else {
1049 /* Disable AUTORTS and AUTOCTS */
1050 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1051 }
1052
1053 if (up->port.flags & UPF_SOFT_FLOW) {
1054 /* clear SW control mode bits */
1055 up->efr &= OMAP_UART_SW_CLR;
1056
1057 /*
1058 * IXON Flag:
1059 * Enable XON/XOFF flow control on input.
1060 * Receiver compares XON1, XOFF1.
1061 */
1062 if (termios->c_iflag & IXON)
1063 up->efr |= OMAP_UART_SW_RX;
1064
1065 /*
1066 * IXOFF Flag:
1067 * Enable XON/XOFF flow control on output.
1068 * Transmit XON1, XOFF1
1069 */
1070 if (termios->c_iflag & IXOFF) {
1071 up->port.status |= UPSTAT_AUTOXOFF;
1072 up->efr |= OMAP_UART_SW_TX;
1073 }
1074
1075 /*
1076 * IXANY Flag:
1077 * Enable any character to restart output.
1078 * Operation resumes after receiving any
1079 * character after recognition of the XOFF character
1080 */
1081 if (termios->c_iflag & IXANY)
1082 up->mcr |= UART_MCR_XONANY;
1083 else
1084 up->mcr &= ~UART_MCR_XONANY;
1085 }
1086 serial_out(up, UART_MCR, up->mcr);
1087 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1088 serial_out(up, UART_EFR, up->efr);
1089 serial_out(up, UART_LCR, up->lcr);
1090
1091 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1092
1093 spin_unlock_irqrestore(&up->port.lock, flags);
1094 pm_runtime_mark_last_busy(up->dev);
1095 pm_runtime_put_autosuspend(up->dev);
1096 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1097 }
1098
1099 static void
1100 serial_omap_pm(struct uart_port *port, unsigned int state,
1101 unsigned int oldstate)
1102 {
1103 struct uart_omap_port *up = to_uart_omap_port(port);
1104 unsigned char efr;
1105
1106 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1107
1108 pm_runtime_get_sync(up->dev);
1109 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1110 efr = serial_in(up, UART_EFR);
1111 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1112 serial_out(up, UART_LCR, 0);
1113
1114 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1115 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1116 serial_out(up, UART_EFR, efr);
1117 serial_out(up, UART_LCR, 0);
1118
1119 pm_runtime_mark_last_busy(up->dev);
1120 pm_runtime_put_autosuspend(up->dev);
1121 }
1122
1123 static void serial_omap_release_port(struct uart_port *port)
1124 {
1125 dev_dbg(port->dev, "serial_omap_release_port+\n");
1126 }
1127
1128 static int serial_omap_request_port(struct uart_port *port)
1129 {
1130 dev_dbg(port->dev, "serial_omap_request_port+\n");
1131 return 0;
1132 }
1133
1134 static void serial_omap_config_port(struct uart_port *port, int flags)
1135 {
1136 struct uart_omap_port *up = to_uart_omap_port(port);
1137
1138 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1139 up->port.line);
1140 up->port.type = PORT_OMAP;
1141 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1142 }
1143
1144 static int
1145 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1146 {
1147 /* we don't want the core code to modify any port params */
1148 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1149 return -EINVAL;
1150 }
1151
1152 static const char *
1153 serial_omap_type(struct uart_port *port)
1154 {
1155 struct uart_omap_port *up = to_uart_omap_port(port);
1156
1157 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1158 return up->name;
1159 }
1160
1161 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1162
1163 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1164 {
1165 unsigned int status, tmout = 10000;
1166
1167 /* Wait up to 10ms for the character(s) to be sent. */
1168 do {
1169 status = serial_in(up, UART_LSR);
1170
1171 if (status & UART_LSR_BI)
1172 up->lsr_break_flag = UART_LSR_BI;
1173
1174 if (--tmout == 0)
1175 break;
1176 udelay(1);
1177 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1178
1179 /* Wait up to 1s for flow control if necessary */
1180 if (up->port.flags & UPF_CONS_FLOW) {
1181 tmout = 1000000;
1182 for (tmout = 1000000; tmout; tmout--) {
1183 unsigned int msr = serial_in(up, UART_MSR);
1184
1185 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1186 if (msr & UART_MSR_CTS)
1187 break;
1188
1189 udelay(1);
1190 }
1191 }
1192 }
1193
1194 #ifdef CONFIG_CONSOLE_POLL
1195
1196 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1197 {
1198 struct uart_omap_port *up = to_uart_omap_port(port);
1199
1200 pm_runtime_get_sync(up->dev);
1201 wait_for_xmitr(up);
1202 serial_out(up, UART_TX, ch);
1203 pm_runtime_mark_last_busy(up->dev);
1204 pm_runtime_put_autosuspend(up->dev);
1205 }
1206
1207 static int serial_omap_poll_get_char(struct uart_port *port)
1208 {
1209 struct uart_omap_port *up = to_uart_omap_port(port);
1210 unsigned int status;
1211
1212 pm_runtime_get_sync(up->dev);
1213 status = serial_in(up, UART_LSR);
1214 if (!(status & UART_LSR_DR)) {
1215 status = NO_POLL_CHAR;
1216 goto out;
1217 }
1218
1219 status = serial_in(up, UART_RX);
1220
1221 out:
1222 pm_runtime_mark_last_busy(up->dev);
1223 pm_runtime_put_autosuspend(up->dev);
1224
1225 return status;
1226 }
1227
1228 #endif /* CONFIG_CONSOLE_POLL */
1229
1230 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1231
1232 #ifdef CONFIG_SERIAL_EARLYCON
1233 static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1234 {
1235 offset <<= port->regshift;
1236 return readw(port->membase + offset);
1237 }
1238
1239 static void omap_serial_early_out(struct uart_port *port, int offset,
1240 int value)
1241 {
1242 offset <<= port->regshift;
1243 writew(value, port->membase + offset);
1244 }
1245
1246 static void omap_serial_early_putc(struct uart_port *port, int c)
1247 {
1248 unsigned int status;
1249
1250 for (;;) {
1251 status = omap_serial_early_in(port, UART_LSR);
1252 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1253 break;
1254 cpu_relax();
1255 }
1256 omap_serial_early_out(port, UART_TX, c);
1257 }
1258
1259 static void early_omap_serial_write(struct console *console, const char *s,
1260 unsigned int count)
1261 {
1262 struct earlycon_device *device = console->data;
1263 struct uart_port *port = &device->port;
1264
1265 uart_console_write(port, s, count, omap_serial_early_putc);
1266 }
1267
1268 static int __init early_omap_serial_setup(struct earlycon_device *device,
1269 const char *options)
1270 {
1271 struct uart_port *port = &device->port;
1272
1273 if (!(device->port.membase || device->port.iobase))
1274 return -ENODEV;
1275
1276 port->regshift = 2;
1277 device->con->write = early_omap_serial_write;
1278 return 0;
1279 }
1280
1281 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1282 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1283 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1284 #endif /* CONFIG_SERIAL_EARLYCON */
1285
1286 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1287
1288 static struct uart_driver serial_omap_reg;
1289
1290 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1291 {
1292 struct uart_omap_port *up = to_uart_omap_port(port);
1293
1294 wait_for_xmitr(up);
1295 serial_out(up, UART_TX, ch);
1296 }
1297
1298 static void
1299 serial_omap_console_write(struct console *co, const char *s,
1300 unsigned int count)
1301 {
1302 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1303 unsigned long flags;
1304 unsigned int ier;
1305 int locked = 1;
1306
1307 pm_runtime_get_sync(up->dev);
1308
1309 local_irq_save(flags);
1310 if (up->port.sysrq)
1311 locked = 0;
1312 else if (oops_in_progress)
1313 locked = spin_trylock(&up->port.lock);
1314 else
1315 spin_lock(&up->port.lock);
1316
1317 /*
1318 * First save the IER then disable the interrupts
1319 */
1320 ier = serial_in(up, UART_IER);
1321 serial_out(up, UART_IER, 0);
1322
1323 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1324
1325 /*
1326 * Finally, wait for transmitter to become empty
1327 * and restore the IER
1328 */
1329 wait_for_xmitr(up);
1330 serial_out(up, UART_IER, ier);
1331 /*
1332 * The receive handling will happen properly because the
1333 * receive ready bit will still be set; it is not cleared
1334 * on read. However, modem control will not, we must
1335 * call it if we have saved something in the saved flags
1336 * while processing with interrupts off.
1337 */
1338 if (up->msr_saved_flags)
1339 check_modem_status(up);
1340
1341 pm_runtime_mark_last_busy(up->dev);
1342 pm_runtime_put_autosuspend(up->dev);
1343 if (locked)
1344 spin_unlock(&up->port.lock);
1345 local_irq_restore(flags);
1346 }
1347
1348 static int __init
1349 serial_omap_console_setup(struct console *co, char *options)
1350 {
1351 struct uart_omap_port *up;
1352 int baud = 115200;
1353 int bits = 8;
1354 int parity = 'n';
1355 int flow = 'n';
1356
1357 if (serial_omap_console_ports[co->index] == NULL)
1358 return -ENODEV;
1359 up = serial_omap_console_ports[co->index];
1360
1361 if (options)
1362 uart_parse_options(options, &baud, &parity, &bits, &flow);
1363
1364 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1365 }
1366
1367 static struct console serial_omap_console = {
1368 .name = OMAP_SERIAL_NAME,
1369 .write = serial_omap_console_write,
1370 .device = uart_console_device,
1371 .setup = serial_omap_console_setup,
1372 .flags = CON_PRINTBUFFER,
1373 .index = -1,
1374 .data = &serial_omap_reg,
1375 };
1376
1377 static void serial_omap_add_console_port(struct uart_omap_port *up)
1378 {
1379 serial_omap_console_ports[up->port.line] = up;
1380 }
1381
1382 #define OMAP_CONSOLE (&serial_omap_console)
1383
1384 #else
1385
1386 #define OMAP_CONSOLE NULL
1387
1388 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1389 {}
1390
1391 #endif
1392
1393 /* Enable or disable the rs485 support */
1394 static int
1395 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1396 {
1397 struct uart_omap_port *up = to_uart_omap_port(port);
1398 unsigned int mode;
1399 int val;
1400
1401 pm_runtime_get_sync(up->dev);
1402
1403 /* Disable interrupts from this port */
1404 mode = up->ier;
1405 up->ier = 0;
1406 serial_out(up, UART_IER, 0);
1407
1408 /* Clamp the delays to [0, 100ms] */
1409 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1410 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
1411
1412 /* store new config */
1413 port->rs485 = *rs485;
1414
1415 /*
1416 * Just as a precaution, only allow rs485
1417 * to be enabled if the gpio pin is valid
1418 */
1419 if (gpio_is_valid(up->rts_gpio)) {
1420 /* enable / disable rts */
1421 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1422 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1423 val = (port->rs485.flags & val) ? 1 : 0;
1424 gpio_set_value(up->rts_gpio, val);
1425 } else
1426 port->rs485.flags &= ~SER_RS485_ENABLED;
1427
1428 /* Enable interrupts */
1429 up->ier = mode;
1430 serial_out(up, UART_IER, up->ier);
1431
1432 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1433 * TX FIFO is below the trigger level.
1434 */
1435 if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1436 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1437 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1438 serial_out(up, UART_OMAP_SCR, up->scr);
1439 }
1440
1441 pm_runtime_mark_last_busy(up->dev);
1442 pm_runtime_put_autosuspend(up->dev);
1443
1444 return 0;
1445 }
1446
1447 static const struct uart_ops serial_omap_pops = {
1448 .tx_empty = serial_omap_tx_empty,
1449 .set_mctrl = serial_omap_set_mctrl,
1450 .get_mctrl = serial_omap_get_mctrl,
1451 .stop_tx = serial_omap_stop_tx,
1452 .start_tx = serial_omap_start_tx,
1453 .throttle = serial_omap_throttle,
1454 .unthrottle = serial_omap_unthrottle,
1455 .stop_rx = serial_omap_stop_rx,
1456 .enable_ms = serial_omap_enable_ms,
1457 .break_ctl = serial_omap_break_ctl,
1458 .startup = serial_omap_startup,
1459 .shutdown = serial_omap_shutdown,
1460 .set_termios = serial_omap_set_termios,
1461 .pm = serial_omap_pm,
1462 .type = serial_omap_type,
1463 .release_port = serial_omap_release_port,
1464 .request_port = serial_omap_request_port,
1465 .config_port = serial_omap_config_port,
1466 .verify_port = serial_omap_verify_port,
1467 #ifdef CONFIG_CONSOLE_POLL
1468 .poll_put_char = serial_omap_poll_put_char,
1469 .poll_get_char = serial_omap_poll_get_char,
1470 #endif
1471 };
1472
1473 static struct uart_driver serial_omap_reg = {
1474 .owner = THIS_MODULE,
1475 .driver_name = "OMAP-SERIAL",
1476 .dev_name = OMAP_SERIAL_NAME,
1477 .nr = OMAP_MAX_HSUART_PORTS,
1478 .cons = OMAP_CONSOLE,
1479 };
1480
1481 #ifdef CONFIG_PM_SLEEP
1482 static int serial_omap_prepare(struct device *dev)
1483 {
1484 struct uart_omap_port *up = dev_get_drvdata(dev);
1485
1486 up->is_suspending = true;
1487
1488 return 0;
1489 }
1490
1491 static void serial_omap_complete(struct device *dev)
1492 {
1493 struct uart_omap_port *up = dev_get_drvdata(dev);
1494
1495 up->is_suspending = false;
1496 }
1497
1498 static int serial_omap_suspend(struct device *dev)
1499 {
1500 struct uart_omap_port *up = dev_get_drvdata(dev);
1501
1502 uart_suspend_port(&serial_omap_reg, &up->port);
1503 flush_work(&up->qos_work);
1504
1505 if (device_may_wakeup(dev))
1506 serial_omap_enable_wakeup(up, true);
1507 else
1508 serial_omap_enable_wakeup(up, false);
1509
1510 return 0;
1511 }
1512
1513 static int serial_omap_resume(struct device *dev)
1514 {
1515 struct uart_omap_port *up = dev_get_drvdata(dev);
1516
1517 if (device_may_wakeup(dev))
1518 serial_omap_enable_wakeup(up, false);
1519
1520 uart_resume_port(&serial_omap_reg, &up->port);
1521
1522 return 0;
1523 }
1524 #else
1525 #define serial_omap_prepare NULL
1526 #define serial_omap_complete NULL
1527 #endif /* CONFIG_PM_SLEEP */
1528
1529 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1530 {
1531 u32 mvr, scheme;
1532 u16 revision, major, minor;
1533
1534 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1535
1536 /* Check revision register scheme */
1537 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1538
1539 switch (scheme) {
1540 case 0: /* Legacy Scheme: OMAP2/3 */
1541 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1542 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1543 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1544 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1545 break;
1546 case 1:
1547 /* New Scheme: OMAP4+ */
1548 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1549 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1550 OMAP_UART_MVR_MAJ_SHIFT;
1551 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1552 break;
1553 default:
1554 dev_warn(up->dev,
1555 "Unknown %s revision, defaulting to highest\n",
1556 up->name);
1557 /* highest possible revision */
1558 major = 0xff;
1559 minor = 0xff;
1560 }
1561
1562 /* normalize revision for the driver */
1563 revision = UART_BUILD_REVISION(major, minor);
1564
1565 switch (revision) {
1566 case OMAP_UART_REV_46:
1567 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1568 UART_ERRATA_i291_DMA_FORCEIDLE);
1569 break;
1570 case OMAP_UART_REV_52:
1571 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1572 UART_ERRATA_i291_DMA_FORCEIDLE);
1573 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1574 break;
1575 case OMAP_UART_REV_63:
1576 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1577 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1578 break;
1579 default:
1580 break;
1581 }
1582 }
1583
1584 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1585 {
1586 struct omap_uart_port_info *omap_up_info;
1587
1588 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1589 if (!omap_up_info)
1590 return NULL; /* out of memory */
1591
1592 of_property_read_u32(dev->of_node, "clock-frequency",
1593 &omap_up_info->uartclk);
1594
1595 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1596
1597 return omap_up_info;
1598 }
1599
1600 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1601 struct device_node *np)
1602 {
1603 struct serial_rs485 *rs485conf = &up->port.rs485;
1604 int ret;
1605
1606 rs485conf->flags = 0;
1607 up->rts_gpio = -EINVAL;
1608
1609 if (!np)
1610 return 0;
1611
1612 uart_get_rs485_mode(up->dev, rs485conf);
1613
1614 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1615 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1616 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1617 } else {
1618 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1619 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1620 }
1621
1622 /* check for tx enable gpio */
1623 up->rts_gpio = of_get_named_gpio(np, "rts-gpio", 0);
1624 if (gpio_is_valid(up->rts_gpio)) {
1625 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1626 if (ret < 0)
1627 return ret;
1628 ret = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0;
1629 ret = gpio_direction_output(up->rts_gpio, ret);
1630 if (ret < 0)
1631 return ret;
1632 } else if (up->rts_gpio == -EPROBE_DEFER) {
1633 return -EPROBE_DEFER;
1634 } else {
1635 up->rts_gpio = -EINVAL;
1636 }
1637
1638 return 0;
1639 }
1640
1641 static int serial_omap_probe(struct platform_device *pdev)
1642 {
1643 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1644 struct uart_omap_port *up;
1645 struct resource *mem;
1646 void __iomem *base;
1647 int uartirq = 0;
1648 int wakeirq = 0;
1649 int ret;
1650
1651 /* The optional wakeirq may be specified in the board dts file */
1652 if (pdev->dev.of_node) {
1653 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1654 if (!uartirq)
1655 return -EPROBE_DEFER;
1656 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1657 omap_up_info = of_get_uart_port_info(&pdev->dev);
1658 pdev->dev.platform_data = omap_up_info;
1659 } else {
1660 uartirq = platform_get_irq(pdev, 0);
1661 if (uartirq < 0)
1662 return -EPROBE_DEFER;
1663 }
1664
1665 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1666 if (!up)
1667 return -ENOMEM;
1668
1669 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670 base = devm_ioremap_resource(&pdev->dev, mem);
1671 if (IS_ERR(base))
1672 return PTR_ERR(base);
1673
1674 up->dev = &pdev->dev;
1675 up->port.dev = &pdev->dev;
1676 up->port.type = PORT_OMAP;
1677 up->port.iotype = UPIO_MEM;
1678 up->port.irq = uartirq;
1679 up->port.regshift = 2;
1680 up->port.fifosize = 64;
1681 up->port.ops = &serial_omap_pops;
1682 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1683
1684 if (pdev->dev.of_node)
1685 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1686 else
1687 ret = pdev->id;
1688
1689 if (ret < 0) {
1690 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1691 ret);
1692 goto err_port_line;
1693 }
1694 up->port.line = ret;
1695
1696 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1697 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1698 OMAP_MAX_HSUART_PORTS);
1699 ret = -ENXIO;
1700 goto err_port_line;
1701 }
1702
1703 up->wakeirq = wakeirq;
1704 if (!up->wakeirq)
1705 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1706 up->port.line);
1707
1708 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1709 if (ret < 0)
1710 goto err_rs485;
1711
1712 sprintf(up->name, "OMAP UART%d", up->port.line);
1713 up->port.mapbase = mem->start;
1714 up->port.membase = base;
1715 up->port.flags = omap_up_info->flags;
1716 up->port.uartclk = omap_up_info->uartclk;
1717 up->port.rs485_config = serial_omap_config_rs485;
1718 if (!up->port.uartclk) {
1719 up->port.uartclk = DEFAULT_CLK_SPEED;
1720 dev_warn(&pdev->dev,
1721 "No clock speed specified: using default: %d\n",
1722 DEFAULT_CLK_SPEED);
1723 }
1724
1725 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1726 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1727 pm_qos_add_request(&up->pm_qos_request,
1728 PM_QOS_CPU_DMA_LATENCY, up->latency);
1729 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1730
1731 platform_set_drvdata(pdev, up);
1732 if (omap_up_info->autosuspend_timeout == 0)
1733 omap_up_info->autosuspend_timeout = -1;
1734
1735 device_init_wakeup(up->dev, true);
1736 pm_runtime_use_autosuspend(&pdev->dev);
1737 pm_runtime_set_autosuspend_delay(&pdev->dev,
1738 omap_up_info->autosuspend_timeout);
1739
1740 pm_runtime_irq_safe(&pdev->dev);
1741 pm_runtime_enable(&pdev->dev);
1742
1743 pm_runtime_get_sync(&pdev->dev);
1744
1745 omap_serial_fill_features_erratas(up);
1746
1747 ui[up->port.line] = up;
1748 serial_omap_add_console_port(up);
1749
1750 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1751 if (ret != 0)
1752 goto err_add_port;
1753
1754 pm_runtime_mark_last_busy(up->dev);
1755 pm_runtime_put_autosuspend(up->dev);
1756 return 0;
1757
1758 err_add_port:
1759 pm_runtime_dont_use_autosuspend(&pdev->dev);
1760 pm_runtime_put_sync(&pdev->dev);
1761 pm_runtime_disable(&pdev->dev);
1762 pm_qos_remove_request(&up->pm_qos_request);
1763 device_init_wakeup(up->dev, false);
1764 err_rs485:
1765 err_port_line:
1766 return ret;
1767 }
1768
1769 static int serial_omap_remove(struct platform_device *dev)
1770 {
1771 struct uart_omap_port *up = platform_get_drvdata(dev);
1772
1773 pm_runtime_get_sync(up->dev);
1774
1775 uart_remove_one_port(&serial_omap_reg, &up->port);
1776
1777 pm_runtime_dont_use_autosuspend(up->dev);
1778 pm_runtime_put_sync(up->dev);
1779 pm_runtime_disable(up->dev);
1780 pm_qos_remove_request(&up->pm_qos_request);
1781 device_init_wakeup(&dev->dev, false);
1782
1783 return 0;
1784 }
1785
1786 /*
1787 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1788 * The access to uart register after MDR1 Access
1789 * causes UART to corrupt data.
1790 *
1791 * Need a delay =
1792 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1793 * give 10 times as much
1794 */
1795 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1796 {
1797 u8 timeout = 255;
1798
1799 serial_out(up, UART_OMAP_MDR1, mdr1);
1800 udelay(2);
1801 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1802 UART_FCR_CLEAR_RCVR);
1803 /*
1804 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1805 * TX_FIFO_E bit is 1.
1806 */
1807 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1808 (UART_LSR_THRE | UART_LSR_DR))) {
1809 timeout--;
1810 if (!timeout) {
1811 /* Should *never* happen. we warn and carry on */
1812 dev_crit(up->dev, "Errata i202: timedout %x\n",
1813 serial_in(up, UART_LSR));
1814 break;
1815 }
1816 udelay(1);
1817 }
1818 }
1819
1820 #ifdef CONFIG_PM
1821 static void serial_omap_restore_context(struct uart_omap_port *up)
1822 {
1823 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1824 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1825 else
1826 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1827
1828 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1829 serial_out(up, UART_EFR, UART_EFR_ECB);
1830 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1831 serial_out(up, UART_IER, 0x0);
1832 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1833 serial_out(up, UART_DLL, up->dll);
1834 serial_out(up, UART_DLM, up->dlh);
1835 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1836 serial_out(up, UART_IER, up->ier);
1837 serial_out(up, UART_FCR, up->fcr);
1838 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1839 serial_out(up, UART_MCR, up->mcr);
1840 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1841 serial_out(up, UART_OMAP_SCR, up->scr);
1842 serial_out(up, UART_EFR, up->efr);
1843 serial_out(up, UART_LCR, up->lcr);
1844 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1845 serial_omap_mdr1_errataset(up, up->mdr1);
1846 else
1847 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1848 serial_out(up, UART_OMAP_WER, up->wer);
1849 }
1850
1851 static int serial_omap_runtime_suspend(struct device *dev)
1852 {
1853 struct uart_omap_port *up = dev_get_drvdata(dev);
1854
1855 if (!up)
1856 return -EINVAL;
1857
1858 /*
1859 * When using 'no_console_suspend', the console UART must not be
1860 * suspended. Since driver suspend is managed by runtime suspend,
1861 * preventing runtime suspend (by returning error) will keep device
1862 * active during suspend.
1863 */
1864 if (up->is_suspending && !console_suspend_enabled &&
1865 uart_console(&up->port))
1866 return -EBUSY;
1867
1868 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1869
1870 serial_omap_enable_wakeup(up, true);
1871
1872 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1873 schedule_work(&up->qos_work);
1874
1875 return 0;
1876 }
1877
1878 static int serial_omap_runtime_resume(struct device *dev)
1879 {
1880 struct uart_omap_port *up = dev_get_drvdata(dev);
1881
1882 int loss_cnt = serial_omap_get_context_loss_count(up);
1883
1884 serial_omap_enable_wakeup(up, false);
1885
1886 if (loss_cnt < 0) {
1887 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1888 loss_cnt);
1889 serial_omap_restore_context(up);
1890 } else if (up->context_loss_cnt != loss_cnt) {
1891 serial_omap_restore_context(up);
1892 }
1893 up->latency = up->calc_latency;
1894 schedule_work(&up->qos_work);
1895
1896 return 0;
1897 }
1898 #endif
1899
1900 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1901 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1902 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1903 serial_omap_runtime_resume, NULL)
1904 .prepare = serial_omap_prepare,
1905 .complete = serial_omap_complete,
1906 };
1907
1908 #if defined(CONFIG_OF)
1909 static const struct of_device_id omap_serial_of_match[] = {
1910 { .compatible = "ti,omap2-uart" },
1911 { .compatible = "ti,omap3-uart" },
1912 { .compatible = "ti,omap4-uart" },
1913 {},
1914 };
1915 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1916 #endif
1917
1918 static struct platform_driver serial_omap_driver = {
1919 .probe = serial_omap_probe,
1920 .remove = serial_omap_remove,
1921 .driver = {
1922 .name = OMAP_SERIAL_DRIVER_NAME,
1923 .pm = &serial_omap_dev_pm_ops,
1924 .of_match_table = of_match_ptr(omap_serial_of_match),
1925 },
1926 };
1927
1928 static int __init serial_omap_init(void)
1929 {
1930 int ret;
1931
1932 ret = uart_register_driver(&serial_omap_reg);
1933 if (ret != 0)
1934 return ret;
1935 ret = platform_driver_register(&serial_omap_driver);
1936 if (ret != 0)
1937 uart_unregister_driver(&serial_omap_reg);
1938 return ret;
1939 }
1940
1941 static void __exit serial_omap_exit(void)
1942 {
1943 platform_driver_unregister(&serial_omap_driver);
1944 uart_unregister_driver(&serial_omap_reg);
1945 }
1946
1947 module_init(serial_omap_init);
1948 module_exit(serial_omap_exit);
1949
1950 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1951 MODULE_LICENSE("GPL");
1952 MODULE_AUTHOR("Texas Instruments Inc");
Linux with added FPC-III support