drivers/usb/cdns3/gadget.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * USBSS device controller driver header file
   4  *
   5  * Copyright (C) 2018-2019 Cadence.
   6  * Copyright (C) 2017-2018 NXP
   7  *
   8  * Author: Pawel Laszczak <pawell@cadence.com>
   9  *         Pawel Jez <pjez@cadence.com>
  10  *         Peter Chen <peter.chen@nxp.com>
  11  */
  12 #ifndef __LINUX_CDNS3_GADGET
  13 #define __LINUX_CDNS3_GADGET
  14 #include <linux/usb/gadget.h>
  15
  16 /*
  17  * USBSS-DEV register interface.
  18  * This corresponds to the USBSS Device Controller Interface
  19  */
  20
  21 /**
  22  * struct cdns3_usb_regs - device controller registers.
  23  * @usb_conf:      Global Configuration.
  24  * @usb_sts:       Global Status.
  25  * @usb_cmd:       Global Command.
  26  * @usb_itpn:      ITP/SOF number.
  27  * @usb_lpm:       Global Command.
  28  * @usb_ien:       USB Interrupt Enable.
  29  * @usb_ists:      USB Interrupt Status.
  30  * @ep_sel:        Endpoint Select.
  31  * @ep_traddr:     Endpoint Transfer Ring Address.
  32  * @ep_cfg:        Endpoint Configuration.
  33  * @ep_cmd:        Endpoint Command.
  34  * @ep_sts:        Endpoint Status.
  35  * @ep_sts_sid:    Endpoint Status.
  36  * @ep_sts_en:     Endpoint Status Enable.
  37  * @drbl:          Doorbell.
  38  * @ep_ien:        EP Interrupt Enable.
  39  * @ep_ists:       EP Interrupt Status.
  40  * @usb_pwr:       Global Power Configuration.
  41  * @usb_conf2:     Global Configuration 2.
  42  * @usb_cap1:      Capability 1.
  43  * @usb_cap2:      Capability 2.
  44  * @usb_cap3:      Capability 3.
  45  * @usb_cap4:      Capability 4.
  46  * @usb_cap5:      Capability 5.
  47  * @usb_cap6:      Capability 6.
  48  * @usb_cpkt1:     Custom Packet 1.
  49  * @usb_cpkt2:     Custom Packet 2.
  50  * @usb_cpkt3:     Custom Packet 3.
  51  * @ep_dma_ext_addr: Upper address for DMA operations.
  52  * @buf_addr:      Address for On-chip Buffer operations.
  53  * @buf_data:      Data for On-chip Buffer operations.
  54  * @buf_ctrl:      On-chip Buffer Access Control.
  55  * @dtrans:        DMA Transfer Mode.
  56  * @tdl_from_trb:  Source of TD Configuration.
  57  * @tdl_beh:       TDL Behavior Configuration.
  58  * @ep_tdl:        Endpoint TDL.
  59  * @tdl_beh2:      TDL Behavior 2 Configuration.
  60  * @dma_adv_td:    DMA Advance TD Configuration.
  61  * @reserved1:     Reserved.
  62  * @cfg_regs:      Configuration.
  63  * @reserved2:     Reserved.
  64  * @dma_axi_ctrl:  AXI Control.
  65  * @dma_axi_id:    AXI ID register.
  66  * @dma_axi_cap:   AXI Capability.
  67  * @dma_axi_ctrl0: AXI Control 0.
  68  * @dma_axi_ctrl1: AXI Control 1.
  69  */
  70 struct cdns3_usb_regs {
  71         __le32 usb_conf;
  72         __le32 usb_sts;
  73         __le32 usb_cmd;
  74         __le32 usb_itpn;
  75         __le32 usb_lpm;
  76         __le32 usb_ien;
  77         __le32 usb_ists;
  78         __le32 ep_sel;
  79         __le32 ep_traddr;
  80         __le32 ep_cfg;
  81         __le32 ep_cmd;
  82         __le32 ep_sts;
  83         __le32 ep_sts_sid;
  84         __le32 ep_sts_en;
  85         __le32 drbl;
  86         __le32 ep_ien;
  87         __le32 ep_ists;
  88         __le32 usb_pwr;
  89         __le32 usb_conf2;
  90         __le32 usb_cap1;
  91         __le32 usb_cap2;
  92         __le32 usb_cap3;
  93         __le32 usb_cap4;
  94         __le32 usb_cap5;
  95         __le32 usb_cap6;
  96         __le32 usb_cpkt1;
  97         __le32 usb_cpkt2;
  98         __le32 usb_cpkt3;
  99         __le32 ep_dma_ext_addr;
 100         __le32 buf_addr;
 101         __le32 buf_data;
 102         __le32 buf_ctrl;
 103         __le32 dtrans;
 104         __le32 tdl_from_trb;
 105         __le32 tdl_beh;
 106         __le32 ep_tdl;
 107         __le32 tdl_beh2;
 108         __le32 dma_adv_td;
 109         __le32 reserved1[26];
 110         __le32 cfg_reg1;
 111         __le32 dbg_link1;
 112         __le32 dbg_link2;
 113         __le32 cfg_regs[74];
 114         __le32 reserved2[51];
 115         __le32 dma_axi_ctrl;
 116         __le32 dma_axi_id;
 117         __le32 dma_axi_cap;
 118         __le32 dma_axi_ctrl0;
 119         __le32 dma_axi_ctrl1;
 120 };
 121
 122 /* USB_CONF - bitmasks */
 123 /* Reset USB device configuration. */
 124 #define USB_CONF_CFGRST         BIT(0)
 125 /* Set Configuration. */
 126 #define USB_CONF_CFGSET         BIT(1)
 127 /* Disconnect USB device in SuperSpeed. */
 128 #define USB_CONF_USB3DIS        BIT(3)
 129 /* Disconnect USB device in HS/FS */
 130 #define USB_CONF_USB2DIS        BIT(4)
 131 /* Little Endian access - default */
 132 #define USB_CONF_LENDIAN        BIT(5)
 133 /*
 134  * Big Endian access. Driver assume that byte order for
 135  * SFRs access always is as Little Endian so this bit
 136  * is not used.
 137  */
 138 #define USB_CONF_BENDIAN        BIT(6)
 139 /* Device software reset. */
 140 #define USB_CONF_SWRST          BIT(7)
 141 /* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/
 142 #define USB_CONF_DSING          BIT(8)
 143 /* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */
 144 #define USB_CONF_DMULT          BIT(9)
 145 /* DMA clock turn-off enable. */
 146 #define USB_CONF_DMAOFFEN       BIT(10)
 147 /* DMA clock turn-off disable. */
 148 #define USB_CONF_DMAOFFDS       BIT(11)
 149 /* Clear Force Full Speed. */
 150 #define USB_CONF_CFORCE_FS      BIT(12)
 151 /* Set Force Full Speed. */
 152 #define USB_CONF_SFORCE_FS      BIT(13)
 153 /* Device enable. */
 154 #define USB_CONF_DEVEN          BIT(14)
 155 /* Device disable. */
 156 #define USB_CONF_DEVDS          BIT(15)
 157 /* L1 LPM state entry enable (used in HS/FS mode). */
 158 #define USB_CONF_L1EN           BIT(16)
 159 /* L1 LPM state entry disable (used in HS/FS mode). */
 160 #define USB_CONF_L1DS           BIT(17)
 161 /* USB 2.0 clock gate disable. */
 162 #define USB_CONF_CLK2OFFEN      BIT(18)
 163 /* USB 2.0 clock gate enable. */
 164 #define USB_CONF_CLK2OFFDS      BIT(19)
 165 /* L0 LPM state entry request (used in HS/FS mode). */
 166 #define USB_CONF_LGO_L0         BIT(20)
 167 /* USB 3.0 clock gate disable. */
 168 #define USB_CONF_CLK3OFFEN      BIT(21)
 169 /* USB 3.0 clock gate enable. */
 170 #define USB_CONF_CLK3OFFDS      BIT(22)
 171 /* Bit 23 is reserved*/
 172 /* U1 state entry enable (used in SS mode). */
 173 #define USB_CONF_U1EN           BIT(24)
 174 /* U1 state entry disable (used in SS mode). */
 175 #define USB_CONF_U1DS           BIT(25)
 176 /* U2 state entry enable (used in SS mode). */
 177 #define USB_CONF_U2EN           BIT(26)
 178 /* U2 state entry disable (used in SS mode). */
 179 #define USB_CONF_U2DS           BIT(27)
 180 /* U0 state entry request (used in SS mode). */
 181 #define USB_CONF_LGO_U0         BIT(28)
 182 /* U1 state entry request (used in SS mode). */
 183 #define USB_CONF_LGO_U1         BIT(29)
 184 /* U2 state entry request (used in SS mode). */
 185 #define USB_CONF_LGO_U2         BIT(30)
 186 /* SS.Inactive state entry request (used in SS mode) */
 187 #define USB_CONF_LGO_SSINACT    BIT(31)
 188
 189 /* USB_STS - bitmasks */
 190 /*
 191  * Configuration status.
 192  * 1 - device is in the configured state.
 193  * 0 - device is not configured.
 194  */
 195 #define USB_STS_CFGSTS_MASK     BIT(0)
 196 #define USB_STS_CFGSTS(p)       ((p) & USB_STS_CFGSTS_MASK)
 197 /*
 198  * On-chip memory overflow.
 199  * 0 - On-chip memory status OK.
 200  * 1 - On-chip memory overflow.
 201  */
 202 #define USB_STS_OV_MASK         BIT(1)
 203 #define USB_STS_OV(p)           ((p) & USB_STS_OV_MASK)
 204 /*
 205  * SuperSpeed connection status.
 206  * 0 - USB in SuperSpeed mode disconnected.
 207  * 1 - USB in SuperSpeed mode connected.
 208  */
 209 #define USB_STS_USB3CONS_MASK   BIT(2)
 210 #define USB_STS_USB3CONS(p)     ((p) & USB_STS_USB3CONS_MASK)
 211 /*
 212  * DMA transfer configuration status.
 213  * 0 - single request.
 214  * 1 - multiple TRB chain
 215  * Supported only for controller version <  DEV_VER_V3
 216  */
 217 #define USB_STS_DTRANS_MASK     BIT(3)
 218 #define USB_STS_DTRANS(p)       ((p) & USB_STS_DTRANS_MASK)
 219 /*
 220  * Device speed.
 221  * 0 - Undefined (value after reset).
 222  * 1 - Low speed
 223  * 2 - Full speed
 224  * 3 - High speed
 225  * 4 - Super speed
 226  */
 227 #define USB_STS_USBSPEED_MASK   GENMASK(6, 4)
 228 #define USB_STS_USBSPEED(p)     (((p) & USB_STS_USBSPEED_MASK) >> 4)
 229 #define USB_STS_LS              (0x1 << 4)
 230 #define USB_STS_FS              (0x2 << 4)
 231 #define USB_STS_HS              (0x3 << 4)
 232 #define USB_STS_SS              (0x4 << 4)
 233 #define DEV_UNDEFSPEED(p)       (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
 234 #define DEV_LOWSPEED(p)         (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
 235 #define DEV_FULLSPEED(p)        (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
 236 #define DEV_HIGHSPEED(p)        (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
 237 #define DEV_SUPERSPEED(p)       (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
 238 /*
 239  * Endianness for SFR access.
 240  * 0 - Little Endian order (default after hardware reset).
 241  * 1 - Big Endian order
 242  */
 243 #define USB_STS_ENDIAN_MASK     BIT(7)
 244 #define USB_STS_ENDIAN(p)       ((p) & USB_STS_ENDIAN_MASK)
 245 /*
 246  * HS/FS clock turn-off status.
 247  * 0 - hsfs clock is always on.
 248  * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
 249  *          (default after hardware reset).
 250  */
 251 #define USB_STS_CLK2OFF_MASK    BIT(8)
 252 #define USB_STS_CLK2OFF(p)      ((p) & USB_STS_CLK2OFF_MASK)
 253 /*
 254  * PCLK clock turn-off status.
 255  * 0 - pclk clock is always on.
 256  * 1 - pclk clock turn-off in U3 (SS mode) is enabled
 257  *          (default after hardware reset).
 258  */
 259 #define USB_STS_CLK3OFF_MASK    BIT(9)
 260 #define USB_STS_CLK3OFF(p)      ((p) & USB_STS_CLK3OFF_MASK)
 261 /*
 262  * Controller in reset state.
 263  * 0 - Internal reset is active.
 264  * 1 - Internal reset is not active and controller is fully operational.
 265  */
 266 #define USB_STS_IN_RST_MASK     BIT(10)
 267 #define USB_STS_IN_RST(p)       ((p) & USB_STS_IN_RST_MASK)
 268 /*
 269  * Status of the "TDL calculation basing on TRB" feature.
 270  * 0 - disabled
 271  * 1 - enabled
 272  * Supported only for DEV_VER_V2 controller version.
 273  */
 274 #define USB_STS_TDL_TRB_ENABLED BIT(11)
 275 /*
 276  * Device enable Status.
 277  * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
 278  * 1 - USB device is enabled (VBUS input is connected to the internal logic).
 279  */
 280 #define USB_STS_DEVS_MASK       BIT(14)
 281 #define USB_STS_DEVS(p)         ((p) & USB_STS_DEVS_MASK)
 282 /*
 283  * Address status.
 284  * 0 - USB device is default state.
 285  * 1 - USB device is at least in address state.
 286  */
 287 #define USB_STS_ADDRESSED_MASK  BIT(15)
 288 #define USB_STS_ADDRESSED(p)    ((p) & USB_STS_ADDRESSED_MASK)
 289 /*
 290  * L1 LPM state enable status (used in HS/FS mode).
 291  * 0 - Entering to L1 LPM state disabled.
 292  * 1 - Entering to L1 LPM state enabled.
 293  */
 294 #define USB_STS_L1ENS_MASK      BIT(16)
 295 #define USB_STS_L1ENS(p)        ((p) & USB_STS_L1ENS_MASK)
 296 /*
 297  * Internal VBUS connection status (used both in HS/FS  and SS mode).
 298  * 0 - internal VBUS is not detected.
 299  * 1 - internal VBUS is detected.
 300  */
 301 #define USB_STS_VBUSS_MASK      BIT(17)
 302 #define USB_STS_VBUSS(p)        ((p) & USB_STS_VBUSS_MASK)
 303 /*
 304  * HS/FS LPM  state (used in FS/HS mode).
 305  * 0 - L0 State
 306  * 1 - L1 State
 307  * 2 - L2 State
 308  * 3 - L3 State
 309  */
 310 #define USB_STS_LPMST_MASK      GENMASK(19, 18)
 311 #define DEV_L0_STATE(p)         (((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
 312 #define DEV_L1_STATE(p)         (((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
 313 #define DEV_L2_STATE(p)         (((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
 314 #define DEV_L3_STATE(p)         (((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
 315 /*
 316  * Disable HS status (used in FS/HS mode).
 317  * 0 - the disconnect bit for HS/FS mode is set .
 318  * 1 - the disconnect bit for HS/FS mode is not set.
 319  */
 320 #define USB_STS_USB2CONS_MASK   BIT(20)
 321 #define USB_STS_USB2CONS(p)     ((p) & USB_STS_USB2CONS_MASK)
 322 /*
 323  * HS/FS mode connection status (used in FS/HS mode).
 324  * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
 325  * 1 - High Speed operations in USB2.0 (FS/HS).
 326  */
 327 #define USB_STS_DISABLE_HS_MASK BIT(21)
 328 #define USB_STS_DISABLE_HS(p)   ((p) & USB_STS_DISABLE_HS_MASK)
 329 /*
 330  * U1 state enable status (used in SS mode).
 331  * 0 - Entering to  U1 state disabled.
 332  * 1 - Entering to  U1 state enabled.
 333  */
 334 #define USB_STS_U1ENS_MASK      BIT(24)
 335 #define USB_STS_U1ENS(p)        ((p) & USB_STS_U1ENS_MASK)
 336 /*
 337  * U2 state enable status (used in SS mode).
 338  * 0 - Entering to  U2 state disabled.
 339  * 1 - Entering to  U2 state enabled.
 340  */
 341 #define USB_STS_U2ENS_MASK      BIT(25)
 342 #define USB_STS_U2ENS(p)        ((p) & USB_STS_U2ENS_MASK)
 343 /*
 344  * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
 345  * SuperSpeed link state
 346  */
 347 #define USB_STS_LST_MASK        GENMASK(29, 26)
 348 #define DEV_LST_U0              (((p) & USB_STS_LST_MASK) == (0x0 << 26))
 349 #define DEV_LST_U1              (((p) & USB_STS_LST_MASK) == (0x1 << 26))
 350 #define DEV_LST_U2              (((p) & USB_STS_LST_MASK) == (0x2 << 26))
 351 #define DEV_LST_U3              (((p) & USB_STS_LST_MASK) == (0x3 << 26))
 352 #define DEV_LST_DISABLED        (((p) & USB_STS_LST_MASK) == (0x4 << 26))
 353 #define DEV_LST_RXDETECT        (((p) & USB_STS_LST_MASK) == (0x5 << 26))
 354 #define DEV_LST_INACTIVE        (((p) & USB_STS_LST_MASK) == (0x6 << 26))
 355 #define DEV_LST_POLLING         (((p) & USB_STS_LST_MASK) == (0x7 << 26))
 356 #define DEV_LST_RECOVERY        (((p) & USB_STS_LST_MASK) == (0x8 << 26))
 357 #define DEV_LST_HOT_RESET       (((p) & USB_STS_LST_MASK) == (0x9 << 26))
 358 #define DEV_LST_COMP_MODE       (((p) & USB_STS_LST_MASK) == (0xa << 26))
 359 #define DEV_LST_LB_STATE        (((p) & USB_STS_LST_MASK) == (0xb << 26))
 360 /*
 361  * DMA clock turn-off status.
 362  * 0 - DMA clock is always on (default after hardware reset).
 363  * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
 364  */
 365 #define USB_STS_DMAOFF_MASK     BIT(30)
 366 #define USB_STS_DMAOFF(p)       ((p) & USB_STS_DMAOFF_MASK)
 367 /*
 368  * SFR Endian status.
 369  * 0 - Little Endian order (default after hardware reset).
 370  * 1 - Big Endian order.
 371  */
 372 #define USB_STS_ENDIAN2_MASK    BIT(31)
 373 #define USB_STS_ENDIAN2(p)      ((p) & USB_STS_ENDIAN2_MASK)
 374
 375 /* USB_CMD -  bitmasks */
 376 /* Set Function Address */
 377 #define USB_CMD_SET_ADDR        BIT(0)
 378 /*
 379  * Function Address This field is saved to the device only when the field
 380  * SET_ADDR is set '1 ' during write to USB_CMD register.
 381  * Software is responsible for entering the address of the device during
 382  * SET_ADDRESS request service. This field should be set immediately after
 383  * the SETUP packet is decoded, and prior to confirmation of the status phase
 384  */
 385 #define USB_CMD_FADDR_MASK      GENMASK(7, 1)
 386 #define USB_CMD_FADDR(p)        (((p) << 1) & USB_CMD_FADDR_MASK)
 387 /* Send Function Wake Device Notification TP (used only in SS mode). */
 388 #define USB_CMD_SDNFW           BIT(8)
 389 /* Set Test Mode (used only in HS/FS mode). */
 390 #define USB_CMD_STMODE          BIT(9)
 391 /* Test mode selector (used only in HS/FS mode) */
 392 #define USB_STS_TMODE_SEL_MASK  GENMASK(11, 10)
 393 #define USB_STS_TMODE_SEL(p)    (((p) << 10) & USB_STS_TMODE_SEL_MASK)
 394 /*
 395  *  Send Latency Tolerance Message Device Notification TP (used only
 396  *  in SS mode).
 397  */
 398 #define USB_CMD_SDNLTM          BIT(12)
 399 /* Send Custom Transaction Packet (used only in SS mode) */
 400 #define USB_CMD_SPKT            BIT(13)
 401 /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
 402 #define USB_CMD_DNFW_INT_MASK   GENMASK(23, 16)
 403 #define USB_STS_DNFW_INT(p)     (((p) << 16) & USB_CMD_DNFW_INT_MASK)
 404 /*
 405  * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
 406  * (used only in SS mode).
 407  */
 408 #define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
 409 #define USB_STS_DNLTM_BELT(p)   (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
 410
 411 /* USB_ITPN - bitmasks */
 412 /*
 413  * ITP(SS) / SOF (HS/FS) number
 414  * In SS mode this field represent number of last ITP received from host.
 415  * In HS/FS mode this field represent number of last SOF received from host.
 416  */
 417 #define USB_ITPN_MASK           GENMASK(13, 0)
 418 #define USB_ITPN(p)             ((p) & USB_ITPN_MASK)
 419
 420 /* USB_LPM - bitmasks */
 421 /* Host Initiated Resume Duration. */
 422 #define USB_LPM_HIRD_MASK       GENMASK(3, 0)
 423 #define USB_LPM_HIRD(p)         ((p) & USB_LPM_HIRD_MASK)
 424 /* Remote Wakeup Enable (bRemoteWake). */
 425 #define USB_LPM_BRW             BIT(4)
 426
 427 /* USB_IEN - bitmasks */
 428 /* SS connection interrupt enable */
 429 #define USB_IEN_CONIEN          BIT(0)
 430 /* SS disconnection interrupt enable. */
 431 #define USB_IEN_DISIEN          BIT(1)
 432 /* USB SS warm reset interrupt enable. */
 433 #define USB_IEN_UWRESIEN        BIT(2)
 434 /* USB SS hot reset interrupt enable */
 435 #define USB_IEN_UHRESIEN        BIT(3)
 436 /* SS link U3 state enter interrupt enable (suspend).*/
 437 #define USB_IEN_U3ENTIEN        BIT(4)
 438 /* SS link U3 state exit interrupt enable (wakeup). */
 439 #define USB_IEN_U3EXTIEN        BIT(5)
 440 /* SS link U2 state enter interrupt enable.*/
 441 #define USB_IEN_U2ENTIEN        BIT(6)
 442 /* SS link U2 state exit interrupt enable.*/
 443 #define USB_IEN_U2EXTIEN        BIT(7)
 444 /* SS link U1 state enter interrupt enable.*/
 445 #define USB_IEN_U1ENTIEN        BIT(8)
 446 /* SS link U1 state exit interrupt enable.*/
 447 #define USB_IEN_U1EXTIEN        BIT(9)
 448 /* ITP/SOF packet detected interrupt enable.*/
 449 #define USB_IEN_ITPIEN          BIT(10)
 450 /* Wakeup interrupt enable.*/
 451 #define USB_IEN_WAKEIEN         BIT(11)
 452 /* Send Custom Packet interrupt enable.*/
 453 #define USB_IEN_SPKTIEN         BIT(12)
 454 /* HS/FS mode connection interrupt enable.*/
 455 #define USB_IEN_CON2IEN         BIT(16)
 456 /* HS/FS mode disconnection interrupt enable.*/
 457 #define USB_IEN_DIS2IEN         BIT(17)
 458 /* USB reset (HS/FS mode) interrupt enable.*/
 459 #define USB_IEN_U2RESIEN        BIT(18)
 460 /* LPM L2 state enter interrupt enable.*/
 461 #define USB_IEN_L2ENTIEN        BIT(20)
 462 /* LPM  L2 state exit interrupt enable.*/
 463 #define USB_IEN_L2EXTIEN        BIT(21)
 464 /* LPM L1 state enter interrupt enable.*/
 465 #define USB_IEN_L1ENTIEN        BIT(24)
 466 /* LPM  L1 state exit interrupt enable.*/
 467 #define USB_IEN_L1EXTIEN        BIT(25)
 468 /* Configuration reset interrupt enable.*/
 469 #define USB_IEN_CFGRESIEN       BIT(26)
 470 /* Start of the USB SS warm reset interrupt enable.*/
 471 #define USB_IEN_UWRESSIEN       BIT(28)
 472 /* End of the USB SS warm reset interrupt enable.*/
 473 #define USB_IEN_UWRESEIEN       BIT(29)
 474
 475 #define USB_IEN_INIT  (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
 476                        | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
 477                        | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
 478                        | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
 479
 480 /* USB_ISTS - bitmasks */
 481 /* SS Connection detected. */
 482 #define USB_ISTS_CONI           BIT(0)
 483 /* SS Disconnection detected. */
 484 #define USB_ISTS_DISI           BIT(1)
 485 /* UUSB warm reset detectede. */
 486 #define USB_ISTS_UWRESI         BIT(2)
 487 /* USB hot reset detected. */
 488 #define USB_ISTS_UHRESI         BIT(3)
 489 /* U3 link state enter detected (suspend).*/
 490 #define USB_ISTS_U3ENTI         BIT(4)
 491 /* U3 link state exit detected (wakeup). */
 492 #define USB_ISTS_U3EXTI         BIT(5)
 493 /* U2 link state enter detected.*/
 494 #define USB_ISTS_U2ENTI         BIT(6)
 495 /* U2 link state exit detected.*/
 496 #define USB_ISTS_U2EXTI         BIT(7)
 497 /* U1 link state enter detected.*/
 498 #define USB_ISTS_U1ENTI         BIT(8)
 499 /* U1 link state exit detected.*/
 500 #define USB_ISTS_U1EXTI         BIT(9)
 501 /* ITP/SOF packet detected.*/
 502 #define USB_ISTS_ITPI           BIT(10)
 503 /* Wakeup detected.*/
 504 #define USB_ISTS_WAKEI          BIT(11)
 505 /* Send Custom Packet detected.*/
 506 #define USB_ISTS_SPKTI          BIT(12)
 507 /* HS/FS mode connection detected.*/
 508 #define USB_ISTS_CON2I          BIT(16)
 509 /* HS/FS mode disconnection detected.*/
 510 #define USB_ISTS_DIS2I          BIT(17)
 511 /* USB reset (HS/FS mode) detected.*/
 512 #define USB_ISTS_U2RESI         BIT(18)
 513 /* LPM L2 state enter detected.*/
 514 #define USB_ISTS_L2ENTI         BIT(20)
 515 /* LPM  L2 state exit detected.*/
 516 #define USB_ISTS_L2EXTI         BIT(21)
 517 /* LPM L1 state enter detected.*/
 518 #define USB_ISTS_L1ENTI         BIT(24)
 519 /* LPM L1 state exit detected.*/
 520 #define USB_ISTS_L1EXTI         BIT(25)
 521 /* USB configuration reset detected.*/
 522 #define USB_ISTS_CFGRESI        BIT(26)
 523 /* Start of the USB warm reset detected.*/
 524 #define USB_ISTS_UWRESSI        BIT(28)
 525 /* End of the USB warm reset detected.*/
 526 #define USB_ISTS_UWRESEI        BIT(29)
 527
 528 /* USB_SEL - bitmasks */
 529 #define EP_SEL_EPNO_MASK        GENMASK(3, 0)
 530 /* Endpoint number. */
 531 #define EP_SEL_EPNO(p)          ((p) & EP_SEL_EPNO_MASK)
 532 /* Endpoint direction bit - 0 - OUT, 1 - IN. */
 533 #define EP_SEL_DIR              BIT(7)
 534
 535 #define select_ep_in(nr)        (EP_SEL_EPNO(p) | EP_SEL_DIR)
 536 #define select_ep_out           (EP_SEL_EPNO(p))
 537
 538 /* EP_TRADDR - bitmasks */
 539 /* Transfer Ring address. */
 540 #define EP_TRADDR_TRADDR(p)     ((p))
 541
 542 /* EP_CFG - bitmasks */
 543 /* Endpoint enable */
 544 #define EP_CFG_ENABLE           BIT(0)
 545 /*
 546  *  Endpoint type.
 547  * 1 - isochronous
 548  * 2 - bulk
 549  * 3 - interrupt
 550  */
 551 #define EP_CFG_EPTYPE_MASK      GENMASK(2, 1)
 552 #define EP_CFG_EPTYPE(p)        (((p) << 1)  & EP_CFG_EPTYPE_MASK)
 553 /* Stream support enable (only in SS mode). */
 554 #define EP_CFG_STREAM_EN        BIT(3)
 555 /* TDL check (only in SS mode for BULK EP). */
 556 #define EP_CFG_TDL_CHK          BIT(4)
 557 /* SID check (only in SS mode for BULK OUT EP). */
 558 #define EP_CFG_SID_CHK          BIT(5)
 559 /* DMA transfer endianness. */
 560 #define EP_CFG_EPENDIAN         BIT(7)
 561 /* Max burst size (used only in SS mode). */
 562 #define EP_CFG_MAXBURST_MASK    GENMASK(11, 8)
 563 #define EP_CFG_MAXBURST(p)      (((p) << 8) & EP_CFG_MAXBURST_MASK)
 564 /* ISO max burst. */
 565 #define EP_CFG_MULT_MASK        GENMASK(15, 14)
 566 #define EP_CFG_MULT(p)          (((p) << 14) & EP_CFG_MULT_MASK)
 567 /* ISO max burst. */
 568 #define EP_CFG_MAXPKTSIZE_MASK  GENMASK(26, 16)
 569 #define EP_CFG_MAXPKTSIZE(p)    (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
 570 /* Max number of buffered packets. */
 571 #define EP_CFG_BUFFERING_MASK   GENMASK(31, 27)
 572 #define EP_CFG_BUFFERING(p)     (((p) << 27) & EP_CFG_BUFFERING_MASK)
 573
 574 /* EP_CMD - bitmasks */
 575 /* Endpoint reset. */
 576 #define EP_CMD_EPRST            BIT(0)
 577 /* Endpoint STALL set. */
 578 #define EP_CMD_SSTALL           BIT(1)
 579 /* Endpoint STALL clear. */
 580 #define EP_CMD_CSTALL           BIT(2)
 581 /* Send ERDY TP. */
 582 #define EP_CMD_ERDY             BIT(3)
 583 /* Request complete. */
 584 #define EP_CMD_REQ_CMPL         BIT(5)
 585 /* Transfer descriptor ready. */
 586 #define EP_CMD_DRDY             BIT(6)
 587 /* Data flush. */
 588 #define EP_CMD_DFLUSH           BIT(7)
 589 /*
 590  * Transfer Descriptor Length write  (used only for Bulk Stream capable
 591  * endpoints in SS mode).
 592  * Bit Removed from DEV_VER_V3 controller version.
 593  */
 594 #define EP_CMD_STDL             BIT(8)
 595 /*
 596  * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
 597  * Bits Removed from DEV_VER_V3 controller version.
 598  */
 599 #define EP_CMD_TDL_MASK         GENMASK(15, 9)
 600 #define EP_CMD_TDL_SET(p)       (((p) << 9) & EP_CMD_TDL_MASK)
 601 #define EP_CMD_TDL_GET(p)       (((p) & EP_CMD_TDL_MASK) >> 9)
 602 #define EP_CMD_TDL_MAX          (EP_CMD_TDL_MASK >> 9)
 603
 604 /* ERDY Stream ID value (used in SS mode). */
 605 #define EP_CMD_ERDY_SID_MASK    GENMASK(31, 16)
 606 #define EP_CMD_ERDY_SID(p)      (((p) << 16) & EP_CMD_ERDY_SID_MASK)
 607
 608 /* EP_STS - bitmasks */
 609 /* Setup transfer complete. */
 610 #define EP_STS_SETUP            BIT(0)
 611 /* Endpoint STALL status. */
 612 #define EP_STS_STALL(p)         ((p) & BIT(1))
 613 /* Interrupt On Complete. */
 614 #define EP_STS_IOC              BIT(2)
 615 /* Interrupt on Short Packet. */
 616 #define EP_STS_ISP              BIT(3)
 617 /* Transfer descriptor missing. */
 618 #define EP_STS_DESCMIS          BIT(4)
 619 /* Stream Rejected (used only in SS mode) */
 620 #define EP_STS_STREAMR          BIT(5)
 621 /* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
 622 #define EP_STS_MD_EXIT          BIT(6)
 623 /* TRB error. */
 624 #define EP_STS_TRBERR           BIT(7)
 625 /* Not ready (used only in SS mode). */
 626 #define EP_STS_NRDY             BIT(8)
 627 /* DMA busy bit. */
 628 #define EP_STS_DBUSY            BIT(9)
 629 /* Endpoint Buffer Empty */
 630 #define EP_STS_BUFFEMPTY(p)     ((p) & BIT(10))
 631 /* Current Cycle Status */
 632 #define EP_STS_CCS(p)           ((p) & BIT(11))
 633 /* Prime (used only in SS mode. */
 634 #define EP_STS_PRIME            BIT(12)
 635 /* Stream error (used only in SS mode). */
 636 #define EP_STS_SIDERR           BIT(13)
 637 /* OUT size mismatch. */
 638 #define EP_STS_OUTSMM           BIT(14)
 639 /* ISO transmission error. */
 640 #define EP_STS_ISOERR           BIT(15)
 641 /* Host Packet Pending (only for SS mode). */
 642 #define EP_STS_HOSTPP(p)        ((p) & BIT(16))
 643 /* Stream Protocol State Machine State (only for Bulk stream endpoints). */
 644 #define EP_STS_SPSMST_MASK              GENMASK(18, 17)
 645 #define EP_STS_SPSMST_DISABLED(p)       (((p) & EP_STS_SPSMST_MASK) >> 17)
 646 #define EP_STS_SPSMST_IDLE(p)           (((p) & EP_STS_SPSMST_MASK) >> 17)
 647 #define EP_STS_SPSMST_START_STREAM(p)   (((p) & EP_STS_SPSMST_MASK) >> 17)
 648 #define EP_STS_SPSMST_MOVE_DATA(p)      (((p) & EP_STS_SPSMST_MASK) >> 17)
 649 /* Interrupt On Transfer complete. */
 650 #define EP_STS_IOT              BIT(19)
 651 /* OUT queue endpoint number. */
 652 #define EP_STS_OUTQ_NO_MASK     GENMASK(27, 24)
 653 #define EP_STS_OUTQ_NO(p)       (((p) & EP_STS_OUTQ_NO_MASK) >> 24)
 654 /* OUT queue valid flag. */
 655 #define EP_STS_OUTQ_VAL_MASK    BIT(28)
 656 #define EP_STS_OUTQ_VAL(p)      ((p) & EP_STS_OUTQ_VAL_MASK)
 657 /* SETUP WAIT. */
 658 #define EP_STS_STPWAIT          BIT(31)
 659
 660 /* EP_STS_SID - bitmasks */
 661 /* Stream ID (used only in SS mode). */
 662 #define EP_STS_SID_MASK         GENMASK(15, 0)
 663 #define EP_STS_SID(p)           ((p) & EP_STS_SID_MASK)
 664
 665 /* EP_STS_EN - bitmasks */
 666 /* SETUP interrupt enable. */
 667 #define EP_STS_EN_SETUPEN       BIT(0)
 668 /* OUT transfer missing descriptor enable. */
 669 #define EP_STS_EN_DESCMISEN     BIT(4)
 670 /* Stream Rejected enable. */
 671 #define EP_STS_EN_STREAMREN     BIT(5)
 672 /* Move Data Exit enable.*/
 673 #define EP_STS_EN_MD_EXITEN     BIT(6)
 674 /* TRB enable. */
 675 #define EP_STS_EN_TRBERREN      BIT(7)
 676 /* NRDY enable. */
 677 #define EP_STS_EN_NRDYEN        BIT(8)
 678 /* Prime enable. */
 679 #define EP_STS_EN_PRIMEEEN      BIT(12)
 680 /* Stream error enable. */
 681 #define EP_STS_EN_SIDERREN      BIT(13)
 682 /* OUT size mismatch enable. */
 683 #define EP_STS_EN_OUTSMMEN      BIT(14)
 684 /* ISO transmission error enable. */
 685 #define EP_STS_EN_ISOERREN      BIT(15)
 686 /* Interrupt on Transmission complete enable. */
 687 #define EP_STS_EN_IOTEN         BIT(19)
 688 /* Setup Wait interrupt enable. */
 689 #define EP_STS_EN_STPWAITEN     BIT(31)
 690
 691 /* DRBL- bitmasks */
 692 #define DB_VALUE_BY_INDEX(index) (1 << (index))
 693 #define DB_VALUE_EP0_OUT        BIT(0)
 694 #define DB_VALUE_EP0_IN         BIT(16)
 695
 696 /* EP_IEN - bitmasks */
 697 #define EP_IEN(index)           (1 << (index))
 698 #define EP_IEN_EP_OUT0          BIT(0)
 699 #define EP_IEN_EP_IN0           BIT(16)
 700
 701 /* EP_ISTS - bitmasks */
 702 #define EP_ISTS(index)          (1 << (index))
 703 #define EP_ISTS_EP_OUT0         BIT(0)
 704 #define EP_ISTS_EP_IN0          BIT(16)
 705
 706 /* USB_PWR- bitmasks */
 707 /*Power Shut Off capability enable*/
 708 #define PUSB_PWR_PSO_EN         BIT(0)
 709 /*Power Shut Off capability disable*/
 710 #define PUSB_PWR_PSO_DS         BIT(1)
 711 /*
 712  * Enables turning-off Reference Clock.
 713  * This bit is optional and implemented only when support for OTG is
 714  * implemented (indicated by OTG_READY bit set to '1').
 715  */
 716 #define PUSB_PWR_STB_CLK_SWITCH_EN      BIT(8)
 717 /*
 718  * Status bit indicating that operation required by STB_CLK_SWITCH_EN write
 719  * is completed
 720  */
 721 #define PUSB_PWR_STB_CLK_SWITCH_DONE    BIT(9)
 722 /* This bit informs if Fast Registers Access is enabled. */
 723 #define PUSB_PWR_FST_REG_ACCESS_STAT    BIT(30)
 724 /* Fast Registers Access Enable. */
 725 #define PUSB_PWR_FST_REG_ACCESS         BIT(31)
 726
 727 /* USB_CONF2- bitmasks */
 728 /*
 729  * Writing 1 disables TDL calculation basing on TRB feature in controller
 730  * for DMULT mode.
 731  * Bit supported only for DEV_VER_V2 version.
 732  */
 733 #define USB_CONF2_DIS_TDL_TRB           BIT(1)
 734 /*
 735  * Writing 1 enables TDL calculation basing on TRB feature in controller
 736  * for DMULT mode.
 737  * Bit supported only for DEV_VER_V2 version.
 738  */
 739 #define USB_CONF2_EN_TDL_TRB            BIT(2)
 740
 741 /* USB_CAP1- bitmasks */
 742 /*
 743  * SFR Interface type
 744  * These field reflects type of SFR interface implemented:
 745  * 0x0 - OCP
 746  * 0x1 - AHB,
 747  * 0x2 - PLB
 748  * 0x3 - AXI
 749  * 0x4-0xF - reserved
 750  */
 751 #define USB_CAP1_SFR_TYPE_MASK  GENMASK(3, 0)
 752 #define DEV_SFR_TYPE_OCP(p)     (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
 753 #define DEV_SFR_TYPE_AHB(p)     (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
 754 #define DEV_SFR_TYPE_PLB(p)     (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
 755 #define DEV_SFR_TYPE_AXI(p)     (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
 756 /*
 757  * SFR Interface width
 758  * These field reflects width of SFR interface implemented:
 759  * 0x0 - 8 bit interface,
 760  * 0x1 - 16 bit interface,
 761  * 0x2 - 32 bit interface
 762  * 0x3 - 64 bit interface
 763  * 0x4-0xF - reserved
 764  */
 765 #define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)
 766 #define DEV_SFR_WIDTH_8(p)      (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
 767 #define DEV_SFR_WIDTH_16(p)     (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
 768 #define DEV_SFR_WIDTH_32(p)     (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
 769 #define DEV_SFR_WIDTH_64(p)     (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
 770 /*
 771  * DMA Interface type
 772  * These field reflects type of DMA interface implemented:
 773  * 0x0 - OCP
 774  * 0x1 - AHB,
 775  * 0x2 - PLB
 776  * 0x3 - AXI
 777  * 0x4-0xF - reserved
 778  */
 779 #define USB_CAP1_DMA_TYPE_MASK  GENMASK(11, 8)
 780 #define DEV_DMA_TYPE_OCP(p)     (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
 781 #define DEV_DMA_TYPE_AHB(p)     (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
 782 #define DEV_DMA_TYPE_PLB(p)     (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
 783 #define DEV_DMA_TYPE_AXI(p)     (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
 784 /*
 785  * DMA Interface width
 786  * These field reflects width of DMA interface implemented:
 787  * 0x0 - reserved,
 788  * 0x1 - reserved,
 789  * 0x2 - 32 bit interface
 790  * 0x3 - 64 bit interface
 791  * 0x4-0xF - reserved
 792  */
 793 #define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)
 794 #define DEV_DMA_WIDTH_32(p)     (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
 795 #define DEV_DMA_WIDTH_64(p)     (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
 796 /*
 797  * USB3 PHY Interface type
 798  * These field reflects type of USB3 PHY interface implemented:
 799  * 0x0 - USB PIPE,
 800  * 0x1 - RMMI,
 801  * 0x2-0xF - reserved
 802  */
 803 #define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
 804 #define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
 805 #define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
 806 /*
 807  * USB3 PHY Interface width
 808  * These field reflects width of USB3 PHY interface implemented:
 809  * 0x0 - 8 bit PIPE interface,
 810  * 0x1 - 16 bit PIPE interface,
 811  * 0x2 - 32 bit PIPE interface,
 812  * 0x3 - 64 bit PIPE interface
 813  * 0x4-0xF - reserved
 814  * Note: When SSIC interface is implemented this field shows the width of
 815  * internal PIPE interface. The RMMI interface is always 20bit wide.
 816  */
 817 #define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
 818 #define DEV_U3PHY_WIDTH_8(p) \
 819         (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
 820 #define DEV_U3PHY_WIDTH_16(p) \
 821         (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
 822 #define DEV_U3PHY_WIDTH_32(p) \
 823         (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
 824 #define DEV_U3PHY_WIDTH_64(p) \
 825         (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
 826
 827 /*
 828  * USB2 PHY Interface enable
 829  * These field informs if USB2 PHY interface is implemented:
 830  * 0x0 - interface NOT implemented,
 831  * 0x1 - interface implemented
 832  */
 833 #define USB_CAP1_U2PHY_EN(p)    ((p) & BIT(24))
 834 /*
 835  * USB2 PHY Interface type
 836  * These field reflects type of USB2 PHY interface implemented:
 837  * 0x0 - UTMI,
 838  * 0x1 - ULPI
 839  */
 840 #define DEV_U2PHY_ULPI(p)       ((p) & BIT(25))
 841 /*
 842  * USB2 PHY Interface width
 843  * These field reflects width of USB2 PHY interface implemented:
 844  * 0x0 - 8 bit interface,
 845  * 0x1 - 16 bit interface,
 846  * Note: The ULPI interface is always 8bit wide.
 847  */
 848 #define DEV_U2PHY_WIDTH_16(p)   ((p) & BIT(26))
 849 /*
 850  * OTG Ready
 851  * 0x0 - pure device mode
 852  * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
 853  */
 854 #define USB_CAP1_OTG_READY(p)   ((p) & BIT(27))
 855
 856 /*
 857  * When set, indicates that controller supports automatic internal TDL
 858  * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode
 859  * Supported only for DEV_VER_V2 controller version.
 860  */
 861 #define USB_CAP1_TDL_FROM_TRB(p)        ((p) & BIT(28))
 862
 863 /* USB_CAP2- bitmasks */
 864 /*
 865  * The actual size of the connected On-chip RAM memory in kB:
 866  * - 0 means 256 kB (max supported mem size)
 867  * - value other than 0 reflects the mem size in kB
 868  */
 869 #define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
 870 /*
 871  * Max supported mem size
 872  * These field reflects width of on-chip RAM address bus width,
 873  * which determines max supported mem size:
 874  * 0x0-0x7 - reserved,
 875  * 0x8 - support for 4kB mem,
 876  * 0x9 - support for 8kB mem,
 877  * 0xA - support for 16kB mem,
 878  * 0xB - support for 32kB mem,
 879  * 0xC - support for 64kB mem,
 880  * 0xD - support for 128kB mem,
 881  * 0xE - support for 256kB mem,
 882  * 0xF - reserved
 883  */
 884 #define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
 885
 886 /* USB_CAP3- bitmasks */
 887 #define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
 888
 889 /* USB_CAP4- bitmasks */
 890 #define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
 891
 892 /* USB_CAP5- bitmasks */
 893 #define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
 894
 895 /* USB_CAP6- bitmasks */
 896 /* The USBSS-DEV Controller  Internal build number. */
 897 #define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
 898 /* The USBSS-DEV Controller version number. */
 899 #define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
 900
 901 #define DEV_VER_NXP_V1          0x00024502
 902 #define DEV_VER_TI_V1           0x00024509
 903 #define DEV_VER_V2              0x0002450C
 904 #define DEV_VER_V3              0x0002450d
 905
 906 /* DBG_LINK1- bitmasks */
 907 /*
 908  * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum
 909  * time required for decoding the received LFPS as an LFPS.U1_Exit.
 910  */
 911 #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p)       ((p) & GENMASK(7, 0))
 912 /*
 913  * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for
 914  * phytxelecidle deassertion when LFPS.U1_Exit
 915  */
 916 #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK     GENMASK(15, 8)
 917 #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p)       (((p) << 8) & GENMASK(15, 8))
 918 /*
 919  * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
 920  * Receiver termination detection sequence:
 921  * 0: it is possible that USBSS_DEV will terminate Farend receiver
 922  *    termination detection sequence
 923  * 1: USBSS_DEV will not terminate Far-end receiver termination
 924  *    detection sequence
 925  */
 926 #define DBG_LINK1_RXDET_BREAK_DIS               BIT(16)
 927 /* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */
 928 #define DBG_LINK1_LFPS_GEN_PING(p)              (((p) << 17) & GENMASK(21, 17))
 929 /*
 930  * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
 931  * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically
 932  * cleared. Writing '0' has no effect
 933  */
 934 #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET      BIT(24)
 935 /*
 936  * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
 937  * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically
 938  * cleared. Writing '0' has no effect
 939  */
 940 #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET      BIT(25)
 941 /*
 942  * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
 943  * the RXDET_BREAK_DIS field value to the device. This bit is automatically
 944  * cleared. Writing '0' has no effect
 945  */
 946 #define DBG_LINK1_RXDET_BREAK_DIS_SET           BIT(26)
 947 /*
 948  * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
 949  * the LFPS_GEN_PING field value to the device. This bit is automatically
 950  * cleared. Writing '0' has no effect."
 951  */
 952 #define DBG_LINK1_LFPS_GEN_PING_SET             BIT(27)
 953
 954 /* DMA_AXI_CTRL- bitmasks */
 955 /* The mawprot pin configuration. */
 956 #define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
 957 /* The marprot pin configuration. */
 958 #define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
 959 #define DMA_AXI_CTRL_NON_SECURE 0x02
 960
 961 #define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
 962
 963 #define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
 964
 965 /*-------------------------------------------------------------------------*/
 966 /*
 967  * USBSS-DEV DMA interface.
 968  */
 969 #define TRBS_PER_SEGMENT        40
 970
 971 #define ISO_MAX_INTERVAL        10
 972
 973 #define MAX_TRB_LENGTH          BIT(16)
 974
 975 #if TRBS_PER_SEGMENT < 2
 976 #error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
 977 #endif
 978
 979 #define TRBS_PER_STREAM_SEGMENT 2
 980
 981 #if TRBS_PER_STREAM_SEGMENT < 2
 982 #error "Incorrect TRBS_PER_STREAMS_SEGMENT. Minimal Transfer Ring size is 2."
 983 #endif
 984
 985 /*
 986  *Only for ISOC endpoints - maximum number of TRBs is calculated as
 987  * pow(2, bInterval-1) * number of usb requests. It is limitation made by
 988  * driver to save memory. Controller must prepare TRB for each ITP even
 989  * if bInterval > 1. It's the reason why driver needs so many TRBs for
 990  * isochronous endpoints.
 991  */
 992 #define TRBS_PER_ISOC_SEGMENT   (ISO_MAX_INTERVAL * 8)
 993
 994 #define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
 995                                       TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
 996 /**
 997  * struct cdns3_trb - represent Transfer Descriptor block.
 998  * @buffer:     pointer to buffer data
 999  * @length:     length of data
1000  * @control:    control flags.
1001  *
1002  * This structure describes transfer block serviced by DMA module.
1003  */
1004 struct cdns3_trb {
1005         __le32 buffer;
1006         __le32 length;
1007         __le32 control;
1008 };
1009
1010 #define TRB_SIZE                (sizeof(struct cdns3_trb))
1011 #define TRB_RING_SIZE           (TRB_SIZE * TRBS_PER_SEGMENT)
1012 #define TRB_STREAM_RING_SIZE    (TRB_SIZE * TRBS_PER_STREAM_SEGMENT)
1013 #define TRB_ISO_RING_SIZE       (TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
1014 #define TRB_CTRL_RING_SIZE      (TRB_SIZE * 2)
1015
1016 /* TRB bit mask */
1017 #define TRB_TYPE_BITMASK        GENMASK(15, 10)
1018 #define TRB_TYPE(p)             ((p) << 10)
1019 #define TRB_FIELD_TO_TYPE(p)    (((p) & TRB_TYPE_BITMASK) >> 10)
1020
1021 /* TRB type IDs */
1022 /* bulk, interrupt, isoc , and control data stage */
1023 #define TRB_NORMAL              1
1024 /* TRB for linking ring segments */
1025 #define TRB_LINK                6
1026
1027 /* Cycle bit - indicates TRB ownership by driver or hw*/
1028 #define TRB_CYCLE               BIT(0)
1029 /*
1030  * When set to '1', the device will toggle its interpretation of the Cycle bit
1031  */
1032 #define TRB_TOGGLE              BIT(1)
1033
1034 /*
1035  * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
1036  * processed while USB short packet was received. No more buffers defined by
1037  * the TD will be used. DMA will automatically advance to next TD.
1038  * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1039  * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1040  *   is detected independent if ISP is set or not.
1041  */
1042 #define TRB_SP                  BIT(1)
1043
1044 /* Interrupt on short packet*/
1045 #define TRB_ISP                 BIT(2)
1046 /*Setting this bit enables FIFO DMA operation mode*/
1047 #define TRB_FIFO_MODE           BIT(3)
1048 /* Set PCIe no snoop attribute */
1049 #define TRB_CHAIN               BIT(4)
1050 /* Interrupt on completion */
1051 #define TRB_IOC                 BIT(5)
1052
1053 /* stream ID bitmasks. */
1054 #define TRB_STREAM_ID_BITMASK           GENMASK(31, 16)
1055 #define TRB_STREAM_ID(p)                ((p) << 16)
1056 #define TRB_FIELD_TO_STREAMID(p)        (((p) & TRB_STREAM_ID_BITMASK) >> 16)
1057
1058 /* Size of TD expressed in USB packets for HS/FS mode. */
1059 #define TRB_TDL_HS_SIZE(p)      (((p) << 16) & GENMASK(31, 16))
1060 #define TRB_TDL_HS_SIZE_GET(p)  (((p) & GENMASK(31, 16)) >> 16)
1061
1062 /* transfer_len bitmasks. */
1063 #define TRB_LEN(p)              ((p) & GENMASK(16, 0))
1064
1065 /* Size of TD expressed in USB packets for SS mode. */
1066 #define TRB_TDL_SS_SIZE(p)      (((p) << 17) & GENMASK(23, 17))
1067 #define TRB_TDL_SS_SIZE_GET(p)  (((p) & GENMASK(23, 17)) >> 17)
1068
1069 /* transfer_len bitmasks - bits 31:24 */
1070 #define TRB_BURST_LEN(p)        (((p) << 24) & GENMASK(31, 24))
1071 #define TRB_BURST_LEN_GET(p)    (((p) & GENMASK(31, 24)) >> 24)
1072
1073 /* Data buffer pointer bitmasks*/
1074 #define TRB_BUFFER(p)           ((p) & GENMASK(31, 0))
1075
1076 /*-------------------------------------------------------------------------*/
1077 /* Driver numeric constants */
1078
1079 /* Such declaration should be added to ch9.h */
1080 #define USB_DEVICE_MAX_ADDRESS          127
1081
1082 /* Endpoint init values */
1083 #define CDNS3_EP_MAX_PACKET_LIMIT       1024
1084 #define CDNS3_EP_MAX_STREAMS            15
1085 #define CDNS3_EP0_MAX_PACKET_LIMIT      512
1086
1087 /* All endpoints including EP0 */
1088 #define CDNS3_ENDPOINTS_MAX_COUNT       32
1089 #define CDNS3_EP_ZLP_BUF_SIZE           1024
1090
1091 #define CDNS3_EP_BUF_SIZE               4       /* KB */
1092 #define CDNS3_EP_ISO_HS_MULT            3
1093 #define CDNS3_EP_ISO_SS_BURST           3
1094 #define CDNS3_MAX_NUM_DESCMISS_BUF      32
1095 #define CDNS3_DESCMIS_BUF_SIZE          2048    /* Bytes */
1096 #define CDNS3_WA2_NUM_BUFFERS           128
1097 /*-------------------------------------------------------------------------*/
1098 /* Used structs */
1099
1100 struct cdns3_device;
1101
1102 /**
1103  * struct cdns3_endpoint - extended device side representation of USB endpoint.
1104  * @endpoint: usb endpoint
1105  * @pending_req_list: list of requests queuing on transfer ring.
1106  * @deferred_req_list: list of requests waiting for queuing on transfer ring.
1107  * @wa2_descmiss_req_list: list of requests internally allocated by driver.
1108  * @trb_pool: transfer ring - array of transaction buffers
1109  * @trb_pool_dma: dma address of transfer ring
1110  * @cdns3_dev: device associated with this endpoint
1111  * @name: a human readable name e.g. ep1out
1112  * @flags: specify the current state of endpoint
1113  * @descmis_req: internal transfer object used for getting data from on-chip
1114  *     buffer. It can happen only if function driver doesn't send usb_request
1115  *     object on time.
1116  * @dir: endpoint direction
1117  * @num: endpoint number (1 - 15)
1118  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
1119  * @interval: interval between packets used for ISOC endpoint.
1120  * @free_trbs: number of free TRBs in transfer ring
1121  * @num_trbs: number of all TRBs in transfer ring
1122  * @alloc_ring_size: size of the allocated TRB ring
1123  * @pcs: producer cycle state
1124  * @ccs: consumer cycle state
1125  * @enqueue: enqueue index in transfer ring
1126  * @dequeue: dequeue index in transfer ring
1127  * @trb_burst_size: number of burst used in trb.
1128  */
1129 struct cdns3_endpoint {
1130         struct usb_ep           endpoint;
1131         struct list_head        pending_req_list;
1132         struct list_head        deferred_req_list;
1133         struct list_head        wa2_descmiss_req_list;
1134         int                     wa2_counter;
1135
1136         struct cdns3_trb        *trb_pool;
1137         dma_addr_t              trb_pool_dma;
1138
1139         struct cdns3_device     *cdns3_dev;
1140         char                    name[20];
1141
1142 #define EP_ENABLED              BIT(0)
1143 #define EP_STALLED              BIT(1)
1144 #define EP_STALL_PENDING        BIT(2)
1145 #define EP_WEDGE                BIT(3)
1146 #define EP_TRANSFER_STARTED     BIT(4)
1147 #define EP_UPDATE_EP_TRBADDR    BIT(5)
1148 #define EP_PENDING_REQUEST      BIT(6)
1149 #define EP_RING_FULL            BIT(7)
1150 #define EP_CLAIMED              BIT(8)
1151 #define EP_DEFERRED_DRDY        BIT(9)
1152 #define EP_QUIRK_ISO_OUT_EN     BIT(10)
1153 #define EP_QUIRK_END_TRANSFER   BIT(11)
1154 #define EP_QUIRK_EXTRA_BUF_DET  BIT(12)
1155 #define EP_QUIRK_EXTRA_BUF_EN   BIT(13)
1156 #define EP_TDLCHK_EN            BIT(15)
1157         u32                     flags;
1158
1159         struct cdns3_request    *descmis_req;
1160
1161         u8                      dir;
1162         u8                      num;
1163         u8                      type;
1164         int                     interval;
1165
1166         int                     free_trbs;
1167         int                     num_trbs;
1168         int                     alloc_ring_size;
1169         u8                      pcs;
1170         u8                      ccs;
1171         int                     enqueue;
1172         int                     dequeue;
1173         u8                      trb_burst_size;
1174
1175         unsigned int            wa1_set:1;
1176         struct cdns3_trb        *wa1_trb;
1177         unsigned int            wa1_trb_index;
1178         unsigned int            wa1_cycle_bit:1;
1179
1180         /* Stream related */
1181         unsigned int            use_streams:1;
1182         unsigned int            prime_flag:1;
1183         u32                     ep_sts_pending;
1184         u16                     last_stream_id;
1185         u16                     pending_tdl;
1186         unsigned int            stream_sg_idx;
1187 };
1188
1189 /**
1190  * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1191  * @buf: aligned to 8 bytes data buffer. Buffer address used in
1192  *       TRB shall be aligned to 8.
1193  * @dma: dma address
1194  * @size: size of buffer
1195  * @in_use: inform if this buffer is associated with usb_request
1196  * @list: used to adding instance of this object to list
1197  */
1198 struct cdns3_aligned_buf {
1199         void                    *buf;
1200         dma_addr_t              dma;
1201         u32                     size;
1202         int                     in_use:1;
1203         struct list_head        list;
1204 };
1205
1206 /**
1207  * struct cdns3_request - extended device side representation of usb_request
1208  *                        object .
1209  * @request: generic usb_request object describing single I/O request.
1210  * @priv_ep: extended representation of usb_ep object
1211  * @trb: the first TRB association with this request
1212  * @start_trb: number of the first TRB in transfer ring
1213  * @end_trb: number of the last TRB in transfer ring
1214  * @aligned_buf: object holds information about aligned buffer associated whit
1215  *               this endpoint
1216  * @flags: flag specifying special usage of request
1217  * @list: used by internally allocated request to add to wa2_descmiss_req_list.
1218  */
1219 struct cdns3_request {
1220         struct usb_request              request;
1221         struct cdns3_endpoint           *priv_ep;
1222         struct cdns3_trb                *trb;
1223         int                             start_trb;
1224         int                             end_trb;
1225         struct cdns3_aligned_buf        *aligned_buf;
1226 #define REQUEST_PENDING                 BIT(0)
1227 #define REQUEST_INTERNAL                BIT(1)
1228 #define REQUEST_INTERNAL_CH             BIT(2)
1229 #define REQUEST_ZLP                     BIT(3)
1230 #define REQUEST_UNALIGNED               BIT(4)
1231         u32                             flags;
1232         struct list_head                list;
1233 };
1234
1235 #define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
1236
1237 /*Stages used during enumeration process.*/
1238 #define CDNS3_SETUP_STAGE               0x0
1239 #define CDNS3_DATA_STAGE                0x1
1240 #define CDNS3_STATUS_STAGE              0x2
1241
1242 /**
1243  * struct cdns3_device - represent USB device.
1244  * @dev: pointer to device structure associated whit this controller
1245  * @sysdev: pointer to the DMA capable device
1246  * @gadget: device side representation of the peripheral controller
1247  * @gadget_driver: pointer to the gadget driver
1248  * @dev_ver: device controller version.
1249  * @lock: for synchronizing
1250  * @regs: base address for device side registers
1251  * @setup_buf: used while processing usb control requests
1252  * @setup_dma: dma address for setup_buf
1253  * @zlp_buf - zlp buffer
1254  * @ep0_stage: ep0 stage during enumeration process.
1255  * @ep0_data_dir: direction for control transfer
1256  * @eps: array of pointers to all endpoints with exclusion ep0
1257  * @aligned_buf_list: list of aligned buffers internally allocated by driver
1258  * @aligned_buf_wq: workqueue freeing  no longer used aligned buf.
1259  * @selected_ep: actually selected endpoint. It's used only to improve
1260  *               performance.
1261  * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
1262  * @u1_allowed: allow device transition to u1 state
1263  * @u2_allowed: allow device transition to u2 state
1264  * @is_selfpowered: device is self powered
1265  * @setup_pending: setup packet is processing by gadget driver
1266  * @hw_configured_flag: hardware endpoint configuration was set.
1267  * @wake_up_flag: allow device to remote up the host
1268  * @status_completion_no_call: indicate that driver is waiting for status s
1269  *     stage completion. It's used in deferred SET_CONFIGURATION request.
1270  * @onchip_buffers: number of available on-chip buffers.
1271  * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1272  * @pending_status_wq: workqueue handling status stage for deferred requests.
1273  * @pending_status_request: request for which status stage was deferred
1274  */
1275 struct cdns3_device {
1276         struct device                   *dev;
1277         struct device                   *sysdev;
1278
1279         struct usb_gadget               gadget;
1280         struct usb_gadget_driver        *gadget_driver;
1281
1282 #define CDNS_REVISION_V0                0x00024501
1283 #define CDNS_REVISION_V1                0x00024509
1284         u32                             dev_ver;
1285
1286         /* generic spin-lock for drivers */
1287         spinlock_t                      lock;
1288
1289         struct cdns3_usb_regs           __iomem *regs;
1290
1291         struct usb_ctrlrequest          *setup_buf;
1292         dma_addr_t                      setup_dma;
1293         void                            *zlp_buf;
1294
1295         u8                              ep0_stage;
1296         int                             ep0_data_dir;
1297
1298         struct cdns3_endpoint           *eps[CDNS3_ENDPOINTS_MAX_COUNT];
1299
1300         struct list_head                aligned_buf_list;
1301         struct work_struct              aligned_buf_wq;
1302
1303         u32                             selected_ep;
1304         u16                             isoch_delay;
1305
1306         unsigned                        wait_for_setup:1;
1307         unsigned                        u1_allowed:1;
1308         unsigned                        u2_allowed:1;
1309         unsigned                        is_selfpowered:1;
1310         unsigned                        setup_pending:1;
1311         int                             hw_configured_flag:1;
1312         int                             wake_up_flag:1;
1313         unsigned                        status_completion_no_call:1;
1314         unsigned                        using_streams:1;
1315         int                             out_mem_is_allocated;
1316
1317         struct work_struct              pending_status_wq;
1318         struct usb_request              *pending_status_request;
1319
1320         /*in KB */
1321         u16                             onchip_buffers;
1322         u16                             onchip_used_size;
1323 };
1324
1325 void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
1326 dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
1327                                  struct cdns3_trb *trb);
1328 enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
1329 void cdns3_pending_setup_status_handler(struct work_struct *work);
1330 void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
1331 void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
1332 void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
1333 void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
1334 struct usb_request *cdns3_next_request(struct list_head *list);
1335 void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
1336 int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
1337 u8 cdns3_ep_addr_to_index(u8 ep_addr);
1338 int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
1339 int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
1340 void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
1341 int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
1342 struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1343                                                   gfp_t gfp_flags);
1344 void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1345                                   struct usb_request *request);
1346 int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
1347 void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
1348                            struct cdns3_request *priv_req,
1349                            int status);
1350
1351 int cdns3_init_ep0(struct cdns3_device *priv_dev,
1352                    struct cdns3_endpoint *priv_ep);
1353 void cdns3_ep0_config(struct cdns3_device *priv_dev);
1354 void cdns3_ep_config(struct cdns3_endpoint *priv_ep);
1355 void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
1356 int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
1357
1358 #endif /* __LINUX_CDNS3_GADGET */