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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / vfio / pci / vfio_pci_config.c
blob90c0b80f8acf971addcdaa5d7262fc84cdfc14b7
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * VFIO PCI config space virtualization
4 *
5 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
6 * Author: Alex Williamson <alex.williamson@redhat.com>
7 *
8 * Derived from original vfio:
9 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
10 * Author: Tom Lyon, pugs@cisco.com
11 */
12
13 /*
14 * This code handles reading and writing of PCI configuration registers.
15 * This is hairy because we want to allow a lot of flexibility to the
16 * user driver, but cannot trust it with all of the config fields.
17 * Tables determine which fields can be read and written, as well as
18 * which fields are 'virtualized' - special actions and translations to
19 * make it appear to the user that he has control, when in fact things
20 * must be negotiated with the underlying OS.
21 */
22
23 #include <linux/fs.h>
24 #include <linux/pci.h>
25 #include <linux/uaccess.h>
26 #include <linux/vfio.h>
27 #include <linux/slab.h>
28
29 #include "vfio_pci_private.h"
30
31 /* Fake capability ID for standard config space */
32 #define PCI_CAP_ID_BASIC 0
33
34 #define is_bar(offset) \
35 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
36 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
37
38 /*
39 * Lengths of PCI Config Capabilities
40 * 0: Removed from the user visible capability list
41 * FF: Variable length
42 */
43 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
44 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
45 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
46 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
47 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
48 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
49 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
50 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
51 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
52 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
53 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */
54 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */
55 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
56 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
57 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
58 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
59 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
60 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
61 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
62 [PCI_CAP_ID_SATA] = 0xFF,
63 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
64 };
65
66 /*
67 * Lengths of PCIe/PCI-X Extended Config Capabilities
68 * 0: Removed or masked from the user visible capability list
69 * FF: Variable length
70 */
71 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
72 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
73 [PCI_EXT_CAP_ID_VC] = 0xFF,
74 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
75 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
76 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
77 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
78 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
79 [PCI_EXT_CAP_ID_MFVC] = 0xFF,
80 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
81 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
82 [PCI_EXT_CAP_ID_VNDR] = 0xFF,
83 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
84 [PCI_EXT_CAP_ID_ACS] = 0xFF,
85 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
86 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
87 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
88 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
89 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
90 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
91 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
92 [PCI_EXT_CAP_ID_REBAR] = 0xFF,
93 [PCI_EXT_CAP_ID_DPA] = 0xFF,
94 [PCI_EXT_CAP_ID_TPH] = 0xFF,
95 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
96 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
97 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
98 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
99 };
100
101 /*
102 * Read/Write Permission Bits - one bit for each bit in capability
103 * Any field can be read if it exists, but what is read depends on
104 * whether the field is 'virtualized', or just pass thru to the
105 * hardware. Any virtualized field is also virtualized for writes.
106 * Writes are only permitted if they have a 1 bit here.
107 */
108 struct perm_bits {
109 u8 *virt; /* read/write virtual data, not hw */
110 u8 *write; /* writeable bits */
111 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
112 struct perm_bits *perm, int offset, __le32 *val);
113 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
114 struct perm_bits *perm, int offset, __le32 val);
115 };
116
117 #define NO_VIRT 0
118 #define ALL_VIRT 0xFFFFFFFFU
119 #define NO_WRITE 0
120 #define ALL_WRITE 0xFFFFFFFFU
121
122 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
123 __le32 *val, int count)
124 {
125 int ret = -EINVAL;
126 u32 tmp_val = 0;
127
128 switch (count) {
129 case 1:
130 {
131 u8 tmp;
132 ret = pci_user_read_config_byte(pdev, offset, &tmp);
133 tmp_val = tmp;
134 break;
135 }
136 case 2:
137 {
138 u16 tmp;
139 ret = pci_user_read_config_word(pdev, offset, &tmp);
140 tmp_val = tmp;
141 break;
142 }
143 case 4:
144 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
145 break;
146 }
147
148 *val = cpu_to_le32(tmp_val);
149
150 return ret;
151 }
152
153 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
154 __le32 val, int count)
155 {
156 int ret = -EINVAL;
157 u32 tmp_val = le32_to_cpu(val);
158
159 switch (count) {
160 case 1:
161 ret = pci_user_write_config_byte(pdev, offset, tmp_val);
162 break;
163 case 2:
164 ret = pci_user_write_config_word(pdev, offset, tmp_val);
165 break;
166 case 4:
167 ret = pci_user_write_config_dword(pdev, offset, tmp_val);
168 break;
169 }
170
171 return ret;
172 }
173
174 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
175 int count, struct perm_bits *perm,
176 int offset, __le32 *val)
177 {
178 __le32 virt = 0;
179
180 memcpy(val, vdev->vconfig + pos, count);
181
182 memcpy(&virt, perm->virt + offset, count);
183
184 /* Any non-virtualized bits? */
185 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
186 struct pci_dev *pdev = vdev->pdev;
187 __le32 phys_val = 0;
188 int ret;
189
190 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
191 if (ret)
192 return ret;
193
194 *val = (phys_val & ~virt) | (*val & virt);
195 }
196
197 return count;
198 }
199
200 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
201 int count, struct perm_bits *perm,
202 int offset, __le32 val)
203 {
204 __le32 virt = 0, write = 0;
205
206 memcpy(&write, perm->write + offset, count);
207
208 if (!write)
209 return count; /* drop, no writable bits */
210
211 memcpy(&virt, perm->virt + offset, count);
212
213 /* Virtualized and writable bits go to vconfig */
214 if (write & virt) {
215 __le32 virt_val = 0;
216
217 memcpy(&virt_val, vdev->vconfig + pos, count);
218
219 virt_val &= ~(write & virt);
220 virt_val |= (val & (write & virt));
221
222 memcpy(vdev->vconfig + pos, &virt_val, count);
223 }
224
225 /* Non-virtualzed and writable bits go to hardware */
226 if (write & ~virt) {
227 struct pci_dev *pdev = vdev->pdev;
228 __le32 phys_val = 0;
229 int ret;
230
231 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
232 if (ret)
233 return ret;
234
235 phys_val &= ~(write & ~virt);
236 phys_val |= (val & (write & ~virt));
237
238 ret = vfio_user_config_write(pdev, pos, phys_val, count);
239 if (ret)
240 return ret;
241 }
242
243 return count;
244 }
245
246 /* Allow direct read from hardware, except for capability next pointer */
247 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
248 int count, struct perm_bits *perm,
249 int offset, __le32 *val)
250 {
251 int ret;
252
253 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
254 if (ret)
255 return ret;
256
257 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
258 if (offset < 4)
259 memcpy(val, vdev->vconfig + pos, count);
260 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
261 if (offset == PCI_CAP_LIST_ID && count > 1)
262 memcpy(val, vdev->vconfig + pos,
263 min(PCI_CAP_FLAGS, count));
264 else if (offset == PCI_CAP_LIST_NEXT)
265 memcpy(val, vdev->vconfig + pos, 1);
266 }
267
268 return count;
269 }
270
271 /* Raw access skips any kind of virtualization */
272 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
273 int count, struct perm_bits *perm,
274 int offset, __le32 val)
275 {
276 int ret;
277
278 ret = vfio_user_config_write(vdev->pdev, pos, val, count);
279 if (ret)
280 return ret;
281
282 return count;
283 }
284
285 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
286 int count, struct perm_bits *perm,
287 int offset, __le32 *val)
288 {
289 int ret;
290
291 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
292 if (ret)
293 return ret;
294
295 return count;
296 }
297
298 /* Virt access uses only virtualization */
299 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos,
300 int count, struct perm_bits *perm,
301 int offset, __le32 val)
302 {
303 memcpy(vdev->vconfig + pos, &val, count);
304 return count;
305 }
306
307 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos,
308 int count, struct perm_bits *perm,
309 int offset, __le32 *val)
310 {
311 memcpy(val, vdev->vconfig + pos, count);
312 return count;
313 }
314
315 /* Default capability regions to read-only, no-virtualization */
316 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
317 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
318 };
319 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
320 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
321 };
322 /*
323 * Default unassigned regions to raw read-write access. Some devices
324 * require this to function as they hide registers between the gaps in
325 * config space (be2net). Like MMIO and I/O port registers, we have
326 * to trust the hardware isolation.
327 */
328 static struct perm_bits unassigned_perms = {
329 .readfn = vfio_raw_config_read,
330 .writefn = vfio_raw_config_write
331 };
332
333 static struct perm_bits virt_perms = {
334 .readfn = vfio_virt_config_read,
335 .writefn = vfio_virt_config_write
336 };
337
338 static void free_perm_bits(struct perm_bits *perm)
339 {
340 kfree(perm->virt);
341 kfree(perm->write);
342 perm->virt = NULL;
343 perm->write = NULL;
344 }
345
346 static int alloc_perm_bits(struct perm_bits *perm, int size)
347 {
348 /*
349 * Round up all permission bits to the next dword, this lets us
350 * ignore whether a read/write exceeds the defined capability
351 * structure. We can do this because:
352 * - Standard config space is already dword aligned
353 * - Capabilities are all dword aligned (bits 0:1 of next reserved)
354 * - Express capabilities defined as dword aligned
355 */
356 size = round_up(size, 4);
357
358 /*
359 * Zero state is
360 * - All Readable, None Writeable, None Virtualized
361 */
362 perm->virt = kzalloc(size, GFP_KERNEL);
363 perm->write = kzalloc(size, GFP_KERNEL);
364 if (!perm->virt || !perm->write) {
365 free_perm_bits(perm);
366 return -ENOMEM;
367 }
368
369 perm->readfn = vfio_default_config_read;
370 perm->writefn = vfio_default_config_write;
371
372 return 0;
373 }
374
375 /*
376 * Helper functions for filling in permission tables
377 */
378 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
379 {
380 p->virt[off] = virt;
381 p->write[off] = write;
382 }
383
384 /* Handle endian-ness - pci and tables are little-endian */
385 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
386 {
387 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
388 *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
389 }
390
391 /* Handle endian-ness - pci and tables are little-endian */
392 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
393 {
394 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
395 *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
396 }
397
398 /*
399 * Restore the *real* BARs after we detect a FLR or backdoor reset.
400 * (backdoor = some device specific technique that we didn't catch)
401 */
402 static void vfio_bar_restore(struct vfio_pci_device *vdev)
403 {
404 struct pci_dev *pdev = vdev->pdev;
405 u32 *rbar = vdev->rbar;
406 u16 cmd;
407 int i;
408
409 if (pdev->is_virtfn)
410 return;
411
412 pci_info(pdev, "%s: reset recovery - restoring BARs\n", __func__);
413
414 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
415 pci_user_write_config_dword(pdev, i, *rbar);
416
417 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
418
419 if (vdev->nointx) {
420 pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
421 cmd |= PCI_COMMAND_INTX_DISABLE;
422 pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
423 }
424 }
425
426 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
427 {
428 unsigned long flags = pci_resource_flags(pdev, bar);
429 u32 val;
430
431 if (flags & IORESOURCE_IO)
432 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
433
434 val = PCI_BASE_ADDRESS_SPACE_MEMORY;
435
436 if (flags & IORESOURCE_PREFETCH)
437 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
438
439 if (flags & IORESOURCE_MEM_64)
440 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
441
442 return cpu_to_le32(val);
443 }
444
445 /*
446 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
447 * to reflect the hardware capabilities. This implements BAR sizing.
448 */
449 static void vfio_bar_fixup(struct vfio_pci_device *vdev)
450 {
451 struct pci_dev *pdev = vdev->pdev;
452 int i;
453 __le32 *vbar;
454 u64 mask;
455
456 vbar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
457
458 for (i = 0; i < PCI_STD_NUM_BARS; i++, vbar++) {
459 int bar = i + PCI_STD_RESOURCES;
460
461 if (!pci_resource_start(pdev, bar)) {
462 *vbar = 0; /* Unmapped by host = unimplemented to user */
463 continue;
464 }
465
466 mask = ~(pci_resource_len(pdev, bar) - 1);
467
468 *vbar &= cpu_to_le32((u32)mask);
469 *vbar |= vfio_generate_bar_flags(pdev, bar);
470
471 if (*vbar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
472 vbar++;
473 *vbar &= cpu_to_le32((u32)(mask >> 32));
474 i++;
475 }
476 }
477
478 vbar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
479
480 /*
481 * NB. REGION_INFO will have reported zero size if we weren't able
482 * to read the ROM, but we still return the actual BAR size here if
483 * it exists (or the shadow ROM space).
484 */
485 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
486 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
487 mask |= PCI_ROM_ADDRESS_ENABLE;
488 *vbar &= cpu_to_le32((u32)mask);
489 } else if (pdev->resource[PCI_ROM_RESOURCE].flags &
490 IORESOURCE_ROM_SHADOW) {
491 mask = ~(0x20000 - 1);
492 mask |= PCI_ROM_ADDRESS_ENABLE;
493 *vbar &= cpu_to_le32((u32)mask);
494 } else
495 *vbar = 0;
496
497 vdev->bardirty = false;
498 }
499
500 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
501 int count, struct perm_bits *perm,
502 int offset, __le32 *val)
503 {
504 if (is_bar(offset)) /* pos == offset for basic config */
505 vfio_bar_fixup(vdev);
506
507 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
508
509 /* Mask in virtual memory enable for SR-IOV devices */
510 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
511 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
512 u32 tmp_val = le32_to_cpu(*val);
513
514 tmp_val |= cmd & PCI_COMMAND_MEMORY;
515 *val = cpu_to_le32(tmp_val);
516 }
517
518 return count;
519 }
520
521 /* Test whether BARs match the value we think they should contain */
522 static bool vfio_need_bar_restore(struct vfio_pci_device *vdev)
523 {
524 int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
525 u32 bar;
526
527 for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
528 if (vdev->rbar[i]) {
529 ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
530 if (ret || vdev->rbar[i] != bar)
531 return true;
532 }
533 }
534
535 return false;
536 }
537
538 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
539 int count, struct perm_bits *perm,
540 int offset, __le32 val)
541 {
542 struct pci_dev *pdev = vdev->pdev;
543 __le16 *virt_cmd;
544 u16 new_cmd = 0;
545 int ret;
546
547 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
548
549 if (offset == PCI_COMMAND) {
550 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
551 u16 phys_cmd;
552
553 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
554 if (ret)
555 return ret;
556
557 new_cmd = le32_to_cpu(val);
558
559 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
560 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
561 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
562
563 phys_io = !!(phys_cmd & PCI_COMMAND_IO);
564 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
565 new_io = !!(new_cmd & PCI_COMMAND_IO);
566
567 /*
568 * If the user is writing mem/io enable (new_mem/io) and we
569 * think it's already enabled (virt_mem/io), but the hardware
570 * shows it disabled (phys_mem/io, then the device has
571 * undergone some kind of backdoor reset and needs to be
572 * restored before we allow it to enable the bars.
573 * SR-IOV devices will trigger this, but we catch them later
574 */
575 if ((new_mem && virt_mem && !phys_mem) ||
576 (new_io && virt_io && !phys_io) ||
577 vfio_need_bar_restore(vdev))
578 vfio_bar_restore(vdev);
579 }
580
581 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
582 if (count < 0)
583 return count;
584
585 /*
586 * Save current memory/io enable bits in vconfig to allow for
587 * the test above next time.
588 */
589 if (offset == PCI_COMMAND) {
590 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
591
592 *virt_cmd &= cpu_to_le16(~mask);
593 *virt_cmd |= cpu_to_le16(new_cmd & mask);
594 }
595
596 /* Emulate INTx disable */
597 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
598 bool virt_intx_disable;
599
600 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
601 PCI_COMMAND_INTX_DISABLE);
602
603 if (virt_intx_disable && !vdev->virq_disabled) {
604 vdev->virq_disabled = true;
605 vfio_pci_intx_mask(vdev);
606 } else if (!virt_intx_disable && vdev->virq_disabled) {
607 vdev->virq_disabled = false;
608 vfio_pci_intx_unmask(vdev);
609 }
610 }
611
612 if (is_bar(offset))
613 vdev->bardirty = true;
614
615 return count;
616 }
617
618 /* Permissions for the Basic PCI Header */
619 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
620 {
621 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
622 return -ENOMEM;
623
624 perm->readfn = vfio_basic_config_read;
625 perm->writefn = vfio_basic_config_write;
626
627 /* Virtualized for SR-IOV functions, which just have FFFF */
628 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
629 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
630
631 /*
632 * Virtualize INTx disable, we use it internally for interrupt
633 * control and can emulate it for non-PCI 2.3 devices.
634 */
635 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
636
637 /* Virtualize capability list, we might want to skip/disable */
638 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
639
640 /* No harm to write */
641 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
642 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
643 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
644
645 /* Virtualize all bars, can't touch the real ones */
646 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
647 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
648 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
649 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
650 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
651 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
652 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
653
654 /* Allow us to adjust capability chain */
655 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
656
657 /* Sometimes used by sw, just virtualize */
658 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
659
660 /* Virtualize interrupt pin to allow hiding INTx */
661 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
662
663 return 0;
664 }
665
666 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
667 int count, struct perm_bits *perm,
668 int offset, __le32 val)
669 {
670 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
671 if (count < 0)
672 return count;
673
674 if (offset == PCI_PM_CTRL) {
675 pci_power_t state;
676
677 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
678 case 0:
679 state = PCI_D0;
680 break;
681 case 1:
682 state = PCI_D1;
683 break;
684 case 2:
685 state = PCI_D2;
686 break;
687 case 3:
688 state = PCI_D3hot;
689 break;
690 }
691
692 vfio_pci_set_power_state(vdev, state);
693 }
694
695 return count;
696 }
697
698 /* Permissions for the Power Management capability */
699 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
700 {
701 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
702 return -ENOMEM;
703
704 perm->writefn = vfio_pm_config_write;
705
706 /*
707 * We always virtualize the next field so we can remove
708 * capabilities from the chain if we want to.
709 */
710 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
711
712 /*
713 * Power management is defined *per function*, so we can let
714 * the user change power state, but we trap and initiate the
715 * change ourselves, so the state bits are read-only.
716 */
717 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
718 return 0;
719 }
720
721 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
722 int count, struct perm_bits *perm,
723 int offset, __le32 val)
724 {
725 struct pci_dev *pdev = vdev->pdev;
726 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
727 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
728 u16 addr;
729 u32 data;
730
731 /*
732 * Write through to emulation. If the write includes the upper byte
733 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
734 * have work to do.
735 */
736 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
737 if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
738 offset + count <= PCI_VPD_ADDR + 1)
739 return count;
740
741 addr = le16_to_cpu(*paddr);
742
743 if (addr & PCI_VPD_ADDR_F) {
744 data = le32_to_cpu(*pdata);
745 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
746 return count;
747 } else {
748 data = 0;
749 if (pci_read_vpd(pdev, addr, 4, &data) < 0)
750 return count;
751 *pdata = cpu_to_le32(data);
752 }
753
754 /*
755 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
756 * signal completion. If an error occurs above, we assume that not
757 * toggling this bit will induce a driver timeout.
758 */
759 addr ^= PCI_VPD_ADDR_F;
760 *paddr = cpu_to_le16(addr);
761
762 return count;
763 }
764
765 /* Permissions for Vital Product Data capability */
766 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
767 {
768 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
769 return -ENOMEM;
770
771 perm->writefn = vfio_vpd_config_write;
772
773 /*
774 * We always virtualize the next field so we can remove
775 * capabilities from the chain if we want to.
776 */
777 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
778
779 /*
780 * Both the address and data registers are virtualized to
781 * enable access through the pci_vpd_read/write functions
782 */
783 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
784 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
785
786 return 0;
787 }
788
789 /* Permissions for PCI-X capability */
790 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
791 {
792 /* Alloc 24, but only 8 are used in v0 */
793 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
794 return -ENOMEM;
795
796 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
797
798 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
799 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
800 return 0;
801 }
802
803 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
804 int count, struct perm_bits *perm,
805 int offset, __le32 val)
806 {
807 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
808 offset + PCI_EXP_DEVCTL);
809 int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
810
811 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
812 if (count < 0)
813 return count;
814
815 /*
816 * The FLR bit is virtualized, if set and the device supports PCIe
817 * FLR, issue a reset_function. Regardless, clear the bit, the spec
818 * requires it to be always read as zero. NB, reset_function might
819 * not use a PCIe FLR, we don't have that level of granularity.
820 */
821 if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
822 u32 cap;
823 int ret;
824
825 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
826
827 ret = pci_user_read_config_dword(vdev->pdev,
828 pos - offset + PCI_EXP_DEVCAP,
829 &cap);
830
831 if (!ret && (cap & PCI_EXP_DEVCAP_FLR))
832 pci_try_reset_function(vdev->pdev);
833 }
834
835 /*
836 * MPS is virtualized to the user, writes do not change the physical
837 * register since determining a proper MPS value requires a system wide
838 * device view. The MRRS is largely independent of MPS, but since the
839 * user does not have that system-wide view, they might set a safe, but
840 * inefficiently low value. Here we allow writes through to hardware,
841 * but we set the floor to the physical device MPS setting, so that
842 * we can at least use full TLPs, as defined by the MPS value.
843 *
844 * NB, if any devices actually depend on an artificially low MRRS
845 * setting, this will need to be revisited, perhaps with a quirk
846 * though pcie_set_readrq().
847 */
848 if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
849 readrq = 128 <<
850 ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
851 readrq = max(readrq, pcie_get_mps(vdev->pdev));
852
853 pcie_set_readrq(vdev->pdev, readrq);
854 }
855
856 return count;
857 }
858
859 /* Permissions for PCI Express capability */
860 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
861 {
862 /* Alloc largest of possible sizes */
863 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
864 return -ENOMEM;
865
866 perm->writefn = vfio_exp_config_write;
867
868 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
869
870 /*
871 * Allow writes to device control fields, except devctl_phantom,
872 * which could confuse IOMMU, MPS, which can break communication
873 * with other physical devices, and the ARI bit in devctl2, which
874 * is set at probe time. FLR and MRRS get virtualized via our
875 * writefn.
876 */
877 p_setw(perm, PCI_EXP_DEVCTL,
878 PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
879 PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
880 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
881 return 0;
882 }
883
884 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
885 int count, struct perm_bits *perm,
886 int offset, __le32 val)
887 {
888 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
889
890 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
891 if (count < 0)
892 return count;
893
894 /*
895 * The FLR bit is virtualized, if set and the device supports AF
896 * FLR, issue a reset_function. Regardless, clear the bit, the spec
897 * requires it to be always read as zero. NB, reset_function might
898 * not use an AF FLR, we don't have that level of granularity.
899 */
900 if (*ctrl & PCI_AF_CTRL_FLR) {
901 u8 cap;
902 int ret;
903
904 *ctrl &= ~PCI_AF_CTRL_FLR;
905
906 ret = pci_user_read_config_byte(vdev->pdev,
907 pos - offset + PCI_AF_CAP,
908 &cap);
909
910 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP))
911 pci_try_reset_function(vdev->pdev);
912 }
913
914 return count;
915 }
916
917 /* Permissions for Advanced Function capability */
918 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
919 {
920 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
921 return -ENOMEM;
922
923 perm->writefn = vfio_af_config_write;
924
925 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
926 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
927 return 0;
928 }
929
930 /* Permissions for Advanced Error Reporting extended capability */
931 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
932 {
933 u32 mask;
934
935 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
936 return -ENOMEM;
937
938 /*
939 * Virtualize the first dword of all express capabilities
940 * because it includes the next pointer. This lets us later
941 * remove capabilities from the chain if we need to.
942 */
943 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
944
945 /* Writable bits mask */
946 mask = PCI_ERR_UNC_UND | /* Undefined */
947 PCI_ERR_UNC_DLP | /* Data Link Protocol */
948 PCI_ERR_UNC_SURPDN | /* Surprise Down */
949 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
950 PCI_ERR_UNC_FCP | /* Flow Control Protocol */
951 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
952 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
953 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
954 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
955 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
956 PCI_ERR_UNC_ECRC | /* ECRC Error Status */
957 PCI_ERR_UNC_UNSUP | /* Unsupported Request */
958 PCI_ERR_UNC_ACSV | /* ACS Violation */
959 PCI_ERR_UNC_INTN | /* internal error */
960 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
961 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
962 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
963 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
964 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
965 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
966
967 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
968 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
969 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
970 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
971 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
972 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
973 PCI_ERR_COR_INTERNAL | /* Corrected Internal */
974 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
975 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
976 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
977
978 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
979 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
980 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
981 return 0;
982 }
983
984 /* Permissions for Power Budgeting extended capability */
985 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
986 {
987 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
988 return -ENOMEM;
989
990 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
991
992 /* Writing the data selector is OK, the info is still read-only */
993 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
994 return 0;
995 }
996
997 /*
998 * Initialize the shared permission tables
999 */
1000 void vfio_pci_uninit_perm_bits(void)
1001 {
1002 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
1003
1004 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
1005 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
1006 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
1007 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
1008 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
1009
1010 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1011 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1012 }
1013
1014 int __init vfio_pci_init_perm_bits(void)
1015 {
1016 int ret;
1017
1018 /* Basic config space */
1019 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
1020
1021 /* Capabilities */
1022 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
1023 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
1024 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
1025 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1026 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
1027 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
1028
1029 /* Extended capabilities */
1030 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1031 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1032 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1033
1034 if (ret)
1035 vfio_pci_uninit_perm_bits();
1036
1037 return ret;
1038 }
1039
1040 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
1041 {
1042 u8 cap;
1043 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
1044 PCI_STD_HEADER_SIZEOF;
1045 cap = vdev->pci_config_map[pos];
1046
1047 if (cap == PCI_CAP_ID_BASIC)
1048 return 0;
1049
1050 /* XXX Can we have to abutting capabilities of the same type? */
1051 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1052 pos--;
1053
1054 return pos;
1055 }
1056
1057 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
1058 int count, struct perm_bits *perm,
1059 int offset, __le32 *val)
1060 {
1061 /* Update max available queue size from msi_qmax */
1062 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1063 __le16 *flags;
1064 int start;
1065
1066 start = vfio_find_cap_start(vdev, pos);
1067
1068 flags = (__le16 *)&vdev->vconfig[start];
1069
1070 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
1071 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
1072 }
1073
1074 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1075 }
1076
1077 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
1078 int count, struct perm_bits *perm,
1079 int offset, __le32 val)
1080 {
1081 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1082 if (count < 0)
1083 return count;
1084
1085 /* Fixup and write configured queue size and enable to hardware */
1086 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1087 __le16 *pflags;
1088 u16 flags;
1089 int start, ret;
1090
1091 start = vfio_find_cap_start(vdev, pos);
1092
1093 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1094
1095 flags = le16_to_cpu(*pflags);
1096
1097 /* MSI is enabled via ioctl */
1098 if (!is_msi(vdev))
1099 flags &= ~PCI_MSI_FLAGS_ENABLE;
1100
1101 /* Check queue size */
1102 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1103 flags &= ~PCI_MSI_FLAGS_QSIZE;
1104 flags |= vdev->msi_qmax << 4;
1105 }
1106
1107 /* Write back to virt and to hardware */
1108 *pflags = cpu_to_le16(flags);
1109 ret = pci_user_write_config_word(vdev->pdev,
1110 start + PCI_MSI_FLAGS,
1111 flags);
1112 if (ret)
1113 return ret;
1114 }
1115
1116 return count;
1117 }
1118
1119 /*
1120 * MSI determination is per-device, so this routine gets used beyond
1121 * initialization time. Don't add __init
1122 */
1123 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1124 {
1125 if (alloc_perm_bits(perm, len))
1126 return -ENOMEM;
1127
1128 perm->readfn = vfio_msi_config_read;
1129 perm->writefn = vfio_msi_config_write;
1130
1131 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1132
1133 /*
1134 * The upper byte of the control register is reserved,
1135 * just setup the lower byte.
1136 */
1137 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1138 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1139 if (flags & PCI_MSI_FLAGS_64BIT) {
1140 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1141 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1142 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1143 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1144 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1145 }
1146 } else {
1147 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1148 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1149 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1150 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1151 }
1152 }
1153 return 0;
1154 }
1155
1156 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1157 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
1158 {
1159 struct pci_dev *pdev = vdev->pdev;
1160 int len, ret;
1161 u16 flags;
1162
1163 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1164 if (ret)
1165 return pcibios_err_to_errno(ret);
1166
1167 len = 10; /* Minimum size */
1168 if (flags & PCI_MSI_FLAGS_64BIT)
1169 len += 4;
1170 if (flags & PCI_MSI_FLAGS_MASKBIT)
1171 len += 10;
1172
1173 if (vdev->msi_perm)
1174 return len;
1175
1176 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1177 if (!vdev->msi_perm)
1178 return -ENOMEM;
1179
1180 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1181 if (ret) {
1182 kfree(vdev->msi_perm);
1183 return ret;
1184 }
1185
1186 return len;
1187 }
1188
1189 /* Determine extended capability length for VC (2 & 9) and MFVC */
1190 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
1191 {
1192 struct pci_dev *pdev = vdev->pdev;
1193 u32 tmp;
1194 int ret, evcc, phases, vc_arb;
1195 int len = PCI_CAP_VC_BASE_SIZEOF;
1196
1197 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1198 if (ret)
1199 return pcibios_err_to_errno(ret);
1200
1201 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1202 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1203 if (ret)
1204 return pcibios_err_to_errno(ret);
1205
1206 if (tmp & PCI_VC_CAP2_128_PHASE)
1207 phases = 128;
1208 else if (tmp & PCI_VC_CAP2_64_PHASE)
1209 phases = 64;
1210 else if (tmp & PCI_VC_CAP2_32_PHASE)
1211 phases = 32;
1212 else
1213 phases = 0;
1214
1215 vc_arb = phases * 4;
1216
1217 /*
1218 * Port arbitration tables are root & switch only;
1219 * function arbitration tables are function 0 only.
1220 * In either case, we'll never let user write them so
1221 * we don't care how big they are
1222 */
1223 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1224 if (vc_arb) {
1225 len = round_up(len, 16);
1226 len += vc_arb / 8;
1227 }
1228 return len;
1229 }
1230
1231 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
1232 {
1233 struct pci_dev *pdev = vdev->pdev;
1234 u32 dword;
1235 u16 word;
1236 u8 byte;
1237 int ret;
1238
1239 switch (cap) {
1240 case PCI_CAP_ID_MSI:
1241 return vfio_msi_cap_len(vdev, pos);
1242 case PCI_CAP_ID_PCIX:
1243 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1244 if (ret)
1245 return pcibios_err_to_errno(ret);
1246
1247 if (PCI_X_CMD_VERSION(word)) {
1248 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1249 /* Test for extended capabilities */
1250 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
1251 &dword);
1252 vdev->extended_caps = (dword != 0);
1253 }
1254 return PCI_CAP_PCIX_SIZEOF_V2;
1255 } else
1256 return PCI_CAP_PCIX_SIZEOF_V0;
1257 case PCI_CAP_ID_VNDR:
1258 /* length follows next field */
1259 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1260 if (ret)
1261 return pcibios_err_to_errno(ret);
1262
1263 return byte;
1264 case PCI_CAP_ID_EXP:
1265 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1266 /* Test for extended capabilities */
1267 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1268 vdev->extended_caps = (dword != 0);
1269 }
1270
1271 /* length based on version and type */
1272 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) {
1273 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1274 return 0xc; /* "All Devices" only, no link */
1275 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1276 } else {
1277 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1278 return 0x2c; /* No link */
1279 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1280 }
1281 case PCI_CAP_ID_HT:
1282 ret = pci_read_config_byte(pdev, pos + 3, &byte);
1283 if (ret)
1284 return pcibios_err_to_errno(ret);
1285
1286 return (byte & HT_3BIT_CAP_MASK) ?
1287 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1288 case PCI_CAP_ID_SATA:
1289 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1290 if (ret)
1291 return pcibios_err_to_errno(ret);
1292
1293 byte &= PCI_SATA_REGS_MASK;
1294 if (byte == PCI_SATA_REGS_INLINE)
1295 return PCI_SATA_SIZEOF_LONG;
1296 else
1297 return PCI_SATA_SIZEOF_SHORT;
1298 default:
1299 pci_warn(pdev, "%s: unknown length for PCI cap %#x@%#x\n",
1300 __func__, cap, pos);
1301 }
1302
1303 return 0;
1304 }
1305
1306 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
1307 {
1308 struct pci_dev *pdev = vdev->pdev;
1309 u8 byte;
1310 u32 dword;
1311 int ret;
1312
1313 switch (ecap) {
1314 case PCI_EXT_CAP_ID_VNDR:
1315 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1316 if (ret)
1317 return pcibios_err_to_errno(ret);
1318
1319 return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1320 case PCI_EXT_CAP_ID_VC:
1321 case PCI_EXT_CAP_ID_VC9:
1322 case PCI_EXT_CAP_ID_MFVC:
1323 return vfio_vc_cap_len(vdev, epos);
1324 case PCI_EXT_CAP_ID_ACS:
1325 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1326 if (ret)
1327 return pcibios_err_to_errno(ret);
1328
1329 if (byte & PCI_ACS_EC) {
1330 int bits;
1331
1332 ret = pci_read_config_byte(pdev,
1333 epos + PCI_ACS_EGRESS_BITS,
1334 &byte);
1335 if (ret)
1336 return pcibios_err_to_errno(ret);
1337
1338 bits = byte ? round_up(byte, 32) : 256;
1339 return 8 + (bits / 8);
1340 }
1341 return 8;
1342
1343 case PCI_EXT_CAP_ID_REBAR:
1344 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1345 if (ret)
1346 return pcibios_err_to_errno(ret);
1347
1348 byte &= PCI_REBAR_CTRL_NBAR_MASK;
1349 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1350
1351 return 4 + (byte * 8);
1352 case PCI_EXT_CAP_ID_DPA:
1353 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1354 if (ret)
1355 return pcibios_err_to_errno(ret);
1356
1357 byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1358 return PCI_DPA_BASE_SIZEOF + byte + 1;
1359 case PCI_EXT_CAP_ID_TPH:
1360 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1361 if (ret)
1362 return pcibios_err_to_errno(ret);
1363
1364 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1365 int sts;
1366
1367 sts = dword & PCI_TPH_CAP_ST_MASK;
1368 sts >>= PCI_TPH_CAP_ST_SHIFT;
1369 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1370 }
1371 return PCI_TPH_BASE_SIZEOF;
1372 default:
1373 pci_warn(pdev, "%s: unknown length for PCI ecap %#x@%#x\n",
1374 __func__, ecap, epos);
1375 }
1376
1377 return 0;
1378 }
1379
1380 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
1381 int offset, int size)
1382 {
1383 struct pci_dev *pdev = vdev->pdev;
1384 int ret = 0;
1385
1386 /*
1387 * We try to read physical config space in the largest chunks
1388 * we can, assuming that all of the fields support dword access.
1389 * pci_save_state() makes this same assumption and seems to do ok.
1390 */
1391 while (size) {
1392 int filled;
1393
1394 if (size >= 4 && !(offset % 4)) {
1395 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1396 u32 dword;
1397
1398 ret = pci_read_config_dword(pdev, offset, &dword);
1399 if (ret)
1400 return ret;
1401 *dwordp = cpu_to_le32(dword);
1402 filled = 4;
1403 } else if (size >= 2 && !(offset % 2)) {
1404 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1405 u16 word;
1406
1407 ret = pci_read_config_word(pdev, offset, &word);
1408 if (ret)
1409 return ret;
1410 *wordp = cpu_to_le16(word);
1411 filled = 2;
1412 } else {
1413 u8 *byte = &vdev->vconfig[offset];
1414 ret = pci_read_config_byte(pdev, offset, byte);
1415 if (ret)
1416 return ret;
1417 filled = 1;
1418 }
1419
1420 offset += filled;
1421 size -= filled;
1422 }
1423
1424 return ret;
1425 }
1426
1427 static int vfio_cap_init(struct vfio_pci_device *vdev)
1428 {
1429 struct pci_dev *pdev = vdev->pdev;
1430 u8 *map = vdev->pci_config_map;
1431 u16 status;
1432 u8 pos, *prev, cap;
1433 int loops, ret, caps = 0;
1434
1435 /* Any capabilities? */
1436 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1437 if (ret)
1438 return ret;
1439
1440 if (!(status & PCI_STATUS_CAP_LIST))
1441 return 0; /* Done */
1442
1443 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1444 if (ret)
1445 return ret;
1446
1447 /* Mark the previous position in case we want to skip a capability */
1448 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1449
1450 /* We can bound our loop, capabilities are dword aligned */
1451 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1452 while (pos && loops--) {
1453 u8 next;
1454 int i, len = 0;
1455
1456 ret = pci_read_config_byte(pdev, pos, &cap);
1457 if (ret)
1458 return ret;
1459
1460 ret = pci_read_config_byte(pdev,
1461 pos + PCI_CAP_LIST_NEXT, &next);
1462 if (ret)
1463 return ret;
1464
1465 if (cap <= PCI_CAP_ID_MAX) {
1466 len = pci_cap_length[cap];
1467 if (len == 0xFF) { /* Variable length */
1468 len = vfio_cap_len(vdev, cap, pos);
1469 if (len < 0)
1470 return len;
1471 }
1472 }
1473
1474 if (!len) {
1475 pci_info(pdev, "%s: hiding cap %#x@%#x\n", __func__,
1476 cap, pos);
1477 *prev = next;
1478 pos = next;
1479 continue;
1480 }
1481
1482 /* Sanity check, do we overlap other capabilities? */
1483 for (i = 0; i < len; i++) {
1484 if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1485 continue;
1486
1487 pci_warn(pdev, "%s: PCI config conflict @%#x, was cap %#x now cap %#x\n",
1488 __func__, pos + i, map[pos + i], cap);
1489 }
1490
1491 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1492
1493 memset(map + pos, cap, len);
1494 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1495 if (ret)
1496 return ret;
1497
1498 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1499 pos = next;
1500 caps++;
1501 }
1502
1503 /* If we didn't fill any capabilities, clear the status flag */
1504 if (!caps) {
1505 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1506 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1507 }
1508
1509 return 0;
1510 }
1511
1512 static int vfio_ecap_init(struct vfio_pci_device *vdev)
1513 {
1514 struct pci_dev *pdev = vdev->pdev;
1515 u8 *map = vdev->pci_config_map;
1516 u16 epos;
1517 __le32 *prev = NULL;
1518 int loops, ret, ecaps = 0;
1519
1520 if (!vdev->extended_caps)
1521 return 0;
1522
1523 epos = PCI_CFG_SPACE_SIZE;
1524
1525 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1526
1527 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1528 u32 header;
1529 u16 ecap;
1530 int i, len = 0;
1531 bool hidden = false;
1532
1533 ret = pci_read_config_dword(pdev, epos, &header);
1534 if (ret)
1535 return ret;
1536
1537 ecap = PCI_EXT_CAP_ID(header);
1538
1539 if (ecap <= PCI_EXT_CAP_ID_MAX) {
1540 len = pci_ext_cap_length[ecap];
1541 if (len == 0xFF) {
1542 len = vfio_ext_cap_len(vdev, ecap, epos);
1543 if (len < 0)
1544 return ret;
1545 }
1546 }
1547
1548 if (!len) {
1549 pci_info(pdev, "%s: hiding ecap %#x@%#x\n",
1550 __func__, ecap, epos);
1551
1552 /* If not the first in the chain, we can skip over it */
1553 if (prev) {
1554 u32 val = epos = PCI_EXT_CAP_NEXT(header);
1555 *prev &= cpu_to_le32(~(0xffcU << 20));
1556 *prev |= cpu_to_le32(val << 20);
1557 continue;
1558 }
1559
1560 /*
1561 * Otherwise, fill in a placeholder, the direct
1562 * readfn will virtualize this automatically
1563 */
1564 len = PCI_CAP_SIZEOF;
1565 hidden = true;
1566 }
1567
1568 for (i = 0; i < len; i++) {
1569 if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1570 continue;
1571
1572 pci_warn(pdev, "%s: PCI config conflict @%#x, was ecap %#x now ecap %#x\n",
1573 __func__, epos + i, map[epos + i], ecap);
1574 }
1575
1576 /*
1577 * Even though ecap is 2 bytes, we're currently a long way
1578 * from exceeding 1 byte capabilities. If we ever make it
1579 * up to 0xFE we'll need to up this to a two-byte, byte map.
1580 */
1581 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1582
1583 memset(map + epos, ecap, len);
1584 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1585 if (ret)
1586 return ret;
1587
1588 /*
1589 * If we're just using this capability to anchor the list,
1590 * hide the real ID. Only count real ecaps. XXX PCI spec
1591 * indicates to use cap id = 0, version = 0, next = 0 if
1592 * ecaps are absent, hope users check all the way to next.
1593 */
1594 if (hidden)
1595 *(__le32 *)&vdev->vconfig[epos] &=
1596 cpu_to_le32((0xffcU << 20));
1597 else
1598 ecaps++;
1599
1600 prev = (__le32 *)&vdev->vconfig[epos];
1601 epos = PCI_EXT_CAP_NEXT(header);
1602 }
1603
1604 if (!ecaps)
1605 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1606
1607 return 0;
1608 }
1609
1610 /*
1611 * Nag about hardware bugs, hopefully to have vendors fix them, but at least
1612 * to collect a list of dependencies for the VF INTx pin quirk below.
1613 */
1614 static const struct pci_device_id known_bogus_vf_intx_pin[] = {
1615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) },
1616 {}
1617 };
1618
1619 /*
1620 * For each device we allocate a pci_config_map that indicates the
1621 * capability occupying each dword and thus the struct perm_bits we
1622 * use for read and write. We also allocate a virtualized config
1623 * space which tracks reads and writes to bits that we emulate for
1624 * the user. Initial values filled from device.
1625 *
1626 * Using shared struct perm_bits between all vfio-pci devices saves
1627 * us from allocating cfg_size buffers for virt and write for every
1628 * device. We could remove vconfig and allocate individual buffers
1629 * for each area requiring emulated bits, but the array of pointers
1630 * would be comparable in size (at least for standard config space).
1631 */
1632 int vfio_config_init(struct vfio_pci_device *vdev)
1633 {
1634 struct pci_dev *pdev = vdev->pdev;
1635 u8 *map, *vconfig;
1636 int ret;
1637
1638 /*
1639 * Config space, caps and ecaps are all dword aligned, so we could
1640 * use one byte per dword to record the type. However, there are
1641 * no requiremenst on the length of a capability, so the gap between
1642 * capabilities needs byte granularity.
1643 */
1644 map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1645 if (!map)
1646 return -ENOMEM;
1647
1648 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1649 if (!vconfig) {
1650 kfree(map);
1651 return -ENOMEM;
1652 }
1653
1654 vdev->pci_config_map = map;
1655 vdev->vconfig = vconfig;
1656
1657 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1658 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1659 pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1660
1661 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1662 if (ret)
1663 goto out;
1664
1665 vdev->bardirty = true;
1666
1667 /*
1668 * XXX can we just pci_load_saved_state/pci_restore_state?
1669 * may need to rebuild vconfig after that
1670 */
1671
1672 /* For restore after reset */
1673 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1674 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1675 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1676 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1677 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1678 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1679 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1680
1681 if (pdev->is_virtfn) {
1682 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1683 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1684
1685 /*
1686 * Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register
1687 * does not apply to VFs and VFs must implement this register
1688 * as read-only with value zero. Userspace is not readily able
1689 * to identify whether a device is a VF and thus that the pin
1690 * definition on the device is bogus should it violate this
1691 * requirement. We already virtualize the pin register for
1692 * other purposes, so we simply need to replace the bogus value
1693 * and consider VFs when we determine INTx IRQ count.
1694 */
1695 if (vconfig[PCI_INTERRUPT_PIN] &&
1696 !pci_match_id(known_bogus_vf_intx_pin, pdev))
1697 pci_warn(pdev,
1698 "Hardware bug: VF reports bogus INTx pin %d\n",
1699 vconfig[PCI_INTERRUPT_PIN]);
1700
1701 vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */
1702 }
1703
1704 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
1705 vconfig[PCI_INTERRUPT_PIN] = 0;
1706
1707 ret = vfio_cap_init(vdev);
1708 if (ret)
1709 goto out;
1710
1711 ret = vfio_ecap_init(vdev);
1712 if (ret)
1713 goto out;
1714
1715 return 0;
1716
1717 out:
1718 kfree(map);
1719 vdev->pci_config_map = NULL;
1720 kfree(vconfig);
1721 vdev->vconfig = NULL;
1722 return pcibios_err_to_errno(ret);
1723 }
1724
1725 void vfio_config_free(struct vfio_pci_device *vdev)
1726 {
1727 kfree(vdev->vconfig);
1728 vdev->vconfig = NULL;
1729 kfree(vdev->pci_config_map);
1730 vdev->pci_config_map = NULL;
1731 kfree(vdev->msi_perm);
1732 vdev->msi_perm = NULL;
1733 }
1734
1735 /*
1736 * Find the remaining number of bytes in a dword that match the given
1737 * position. Stop at either the end of the capability or the dword boundary.
1738 */
1739 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
1740 loff_t pos)
1741 {
1742 u8 cap = vdev->pci_config_map[pos];
1743 size_t i;
1744
1745 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1746 /* nop */;
1747
1748 return i;
1749 }
1750
1751 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
1752 size_t count, loff_t *ppos, bool iswrite)
1753 {
1754 struct pci_dev *pdev = vdev->pdev;
1755 struct perm_bits *perm;
1756 __le32 val = 0;
1757 int cap_start = 0, offset;
1758 u8 cap_id;
1759 ssize_t ret;
1760
1761 if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1762 *ppos + count > pdev->cfg_size)
1763 return -EFAULT;
1764
1765 /*
1766 * Chop accesses into aligned chunks containing no more than a
1767 * single capability. Caller increments to the next chunk.
1768 */
1769 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1770 if (count >= 4 && !(*ppos % 4))
1771 count = 4;
1772 else if (count >= 2 && !(*ppos % 2))
1773 count = 2;
1774 else
1775 count = 1;
1776
1777 ret = count;
1778
1779 cap_id = vdev->pci_config_map[*ppos];
1780
1781 if (cap_id == PCI_CAP_ID_INVALID) {
1782 perm = &unassigned_perms;
1783 cap_start = *ppos;
1784 } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
1785 perm = &virt_perms;
1786 cap_start = *ppos;
1787 } else {
1788 if (*ppos >= PCI_CFG_SPACE_SIZE) {
1789 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1790
1791 perm = &ecap_perms[cap_id];
1792 cap_start = vfio_find_cap_start(vdev, *ppos);
1793 } else {
1794 WARN_ON(cap_id > PCI_CAP_ID_MAX);
1795
1796 perm = &cap_perms[cap_id];
1797
1798 if (cap_id == PCI_CAP_ID_MSI)
1799 perm = vdev->msi_perm;
1800
1801 if (cap_id > PCI_CAP_ID_BASIC)
1802 cap_start = vfio_find_cap_start(vdev, *ppos);
1803 }
1804 }
1805
1806 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1807 WARN_ON(cap_start > *ppos);
1808
1809 offset = *ppos - cap_start;
1810
1811 if (iswrite) {
1812 if (!perm->writefn)
1813 return ret;
1814
1815 if (copy_from_user(&val, buf, count))
1816 return -EFAULT;
1817
1818 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1819 } else {
1820 if (perm->readfn) {
1821 ret = perm->readfn(vdev, *ppos, count,
1822 perm, offset, &val);
1823 if (ret < 0)
1824 return ret;
1825 }
1826
1827 if (copy_to_user(buf, &val, count))
1828 return -EFAULT;
1829 }
1830
1831 return ret;
1832 }
1833
1834 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
1835 size_t count, loff_t *ppos, bool iswrite)
1836 {
1837 size_t done = 0;
1838 int ret = 0;
1839 loff_t pos = *ppos;
1840
1841 pos &= VFIO_PCI_OFFSET_MASK;
1842
1843 while (count) {
1844 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);
1845 if (ret < 0)
1846 return ret;
1847
1848 count -= ret;
1849 done += ret;
1850 buf += ret;
1851 pos += ret;
1852 }
1853
1854 *ppos += done;
1855
1856 return done;
1857 }
Linux with added FPC-III support