include/uapi/drm/amdgpu_drm.h

   1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * Copyright 2014 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24  * OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32 #ifndef __AMDGPU_DRM_H__
  33 #define __AMDGPU_DRM_H__
  34
  35 #include "drm.h"
  36
  37 #if defined(__cplusplus)
  38 extern "C" {
  39 #endif
  40
  41 #define DRM_AMDGPU_GEM_CREATE           0x00
  42 #define DRM_AMDGPU_GEM_MMAP             0x01
  43 #define DRM_AMDGPU_CTX                  0x02
  44 #define DRM_AMDGPU_BO_LIST              0x03
  45 #define DRM_AMDGPU_CS                   0x04
  46 #define DRM_AMDGPU_INFO                 0x05
  47 #define DRM_AMDGPU_GEM_METADATA         0x06
  48 #define DRM_AMDGPU_GEM_WAIT_IDLE        0x07
  49 #define DRM_AMDGPU_GEM_VA               0x08
  50 #define DRM_AMDGPU_WAIT_CS              0x09
  51 #define DRM_AMDGPU_GEM_OP               0x10
  52 #define DRM_AMDGPU_GEM_USERPTR          0x11
  53 #define DRM_AMDGPU_WAIT_FENCES          0x12
  54 #define DRM_AMDGPU_VM                   0x13
  55 #define DRM_AMDGPU_FENCE_TO_HANDLE      0x14
  56 #define DRM_AMDGPU_SCHED                0x15
  57
  58 #define DRM_IOCTL_AMDGPU_GEM_CREATE     DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
  59 #define DRM_IOCTL_AMDGPU_GEM_MMAP       DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
  60 #define DRM_IOCTL_AMDGPU_CTX            DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
  61 #define DRM_IOCTL_AMDGPU_BO_LIST        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
  62 #define DRM_IOCTL_AMDGPU_CS             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
  63 #define DRM_IOCTL_AMDGPU_INFO           DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
  64 #define DRM_IOCTL_AMDGPU_GEM_METADATA   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
  65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
  66 #define DRM_IOCTL_AMDGPU_GEM_VA         DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
  67 #define DRM_IOCTL_AMDGPU_WAIT_CS        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
  68 #define DRM_IOCTL_AMDGPU_GEM_OP         DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
  69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
  70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
  71 #define DRM_IOCTL_AMDGPU_VM             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
  72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
  73 #define DRM_IOCTL_AMDGPU_SCHED          DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
  74
  75 /**
  76  * DOC: memory domains
  77  *
  78  * %AMDGPU_GEM_DOMAIN_CPU       System memory that is not GPU accessible.
  79  * Memory in this pool could be swapped out to disk if there is pressure.
  80  *
  81  * %AMDGPU_GEM_DOMAIN_GTT       GPU accessible system memory, mapped into the
  82  * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
  83  * pages of system memory, allows GPU access system memory in a linezrized
  84  * fashion.
  85  *
  86  * %AMDGPU_GEM_DOMAIN_VRAM      Local video memory. For APUs, it is memory
  87  * carved out by the BIOS.
  88  *
  89  * %AMDGPU_GEM_DOMAIN_GDS       Global on-chip data storage used to share data
  90  * across shader threads.
  91  *
  92  * %AMDGPU_GEM_DOMAIN_GWS       Global wave sync, used to synchronize the
  93  * execution of all the waves on a device.
  94  *
  95  * %AMDGPU_GEM_DOMAIN_OA        Ordered append, used by 3D or Compute engines
  96  * for appending data.
  97  */
  98 #define AMDGPU_GEM_DOMAIN_CPU           0x1
  99 #define AMDGPU_GEM_DOMAIN_GTT           0x2
 100 #define AMDGPU_GEM_DOMAIN_VRAM          0x4
 101 #define AMDGPU_GEM_DOMAIN_GDS           0x8
 102 #define AMDGPU_GEM_DOMAIN_GWS           0x10
 103 #define AMDGPU_GEM_DOMAIN_OA            0x20
 104 #define AMDGPU_GEM_DOMAIN_MASK          (AMDGPU_GEM_DOMAIN_CPU | \
 105                                          AMDGPU_GEM_DOMAIN_GTT | \
 106                                          AMDGPU_GEM_DOMAIN_VRAM | \
 107                                          AMDGPU_GEM_DOMAIN_GDS | \
 108                                          AMDGPU_GEM_DOMAIN_GWS | \
 109                                          AMDGPU_GEM_DOMAIN_OA)
 110
 111 /* Flag that CPU access will be required for the case of VRAM domain */
 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED   (1 << 0)
 113 /* Flag that CPU access will not work, this VRAM domain is invisible */
 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS         (1 << 1)
 115 /* Flag that USWC attributes should be used for GTT */
 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC          (1 << 2)
 117 /* Flag that the memory should be in VRAM and cleared */
 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED          (1 << 3)
 119 /* Flag that create shadow bo(GTT) while allocating vram bo */
 120 #define AMDGPU_GEM_CREATE_SHADOW                (1 << 4)
 121 /* Flag that allocating the BO should use linear VRAM */
 122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS       (1 << 5)
 123 /* Flag that BO is always valid in this VM */
 124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID       (1 << 6)
 125 /* Flag that BO sharing will be explicitly synchronized */
 126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC         (1 << 7)
 127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
 128  * for the second page onward should be set to NC.
 129  */
 130 #define AMDGPU_GEM_CREATE_MQD_GFX9              (1 << 8)
 131 /* Flag that BO may contain sensitive data that must be wiped before
 132  * releasing the memory
 133  */
 134 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE  (1 << 9)
 135
 136 struct drm_amdgpu_gem_create_in  {
 137         /** the requested memory size */
 138         __u64 bo_size;
 139         /** physical start_addr alignment in bytes for some HW requirements */
 140         __u64 alignment;
 141         /** the requested memory domains */
 142         __u64 domains;
 143         /** allocation flags */
 144         __u64 domain_flags;
 145 };
 146
 147 struct drm_amdgpu_gem_create_out  {
 148         /** returned GEM object handle */
 149         __u32 handle;
 150         __u32 _pad;
 151 };
 152
 153 union drm_amdgpu_gem_create {
 154         struct drm_amdgpu_gem_create_in         in;
 155         struct drm_amdgpu_gem_create_out        out;
 156 };
 157
 158 /** Opcode to create new residency list.  */
 159 #define AMDGPU_BO_LIST_OP_CREATE        0
 160 /** Opcode to destroy previously created residency list */
 161 #define AMDGPU_BO_LIST_OP_DESTROY       1
 162 /** Opcode to update resource information in the list */
 163 #define AMDGPU_BO_LIST_OP_UPDATE        2
 164
 165 struct drm_amdgpu_bo_list_in {
 166         /** Type of operation */
 167         __u32 operation;
 168         /** Handle of list or 0 if we want to create one */
 169         __u32 list_handle;
 170         /** Number of BOs in list  */
 171         __u32 bo_number;
 172         /** Size of each element describing BO */
 173         __u32 bo_info_size;
 174         /** Pointer to array describing BOs */
 175         __u64 bo_info_ptr;
 176 };
 177
 178 struct drm_amdgpu_bo_list_entry {
 179         /** Handle of BO */
 180         __u32 bo_handle;
 181         /** New (if specified) BO priority to be used during migration */
 182         __u32 bo_priority;
 183 };
 184
 185 struct drm_amdgpu_bo_list_out {
 186         /** Handle of resource list  */
 187         __u32 list_handle;
 188         __u32 _pad;
 189 };
 190
 191 union drm_amdgpu_bo_list {
 192         struct drm_amdgpu_bo_list_in in;
 193         struct drm_amdgpu_bo_list_out out;
 194 };
 195
 196 /* context related */
 197 #define AMDGPU_CTX_OP_ALLOC_CTX 1
 198 #define AMDGPU_CTX_OP_FREE_CTX  2
 199 #define AMDGPU_CTX_OP_QUERY_STATE       3
 200 #define AMDGPU_CTX_OP_QUERY_STATE2      4
 201
 202 /* GPU reset status */
 203 #define AMDGPU_CTX_NO_RESET             0
 204 /* this the context caused it */
 205 #define AMDGPU_CTX_GUILTY_RESET         1
 206 /* some other context caused it */
 207 #define AMDGPU_CTX_INNOCENT_RESET       2
 208 /* unknown cause */
 209 #define AMDGPU_CTX_UNKNOWN_RESET        3
 210
 211 /* indicate gpu reset occured after ctx created */
 212 #define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)
 213 /* indicate vram lost occured after ctx created */
 214 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
 215 /* indicate some job from this context once cause gpu hang */
 216 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
 217 /* indicate some errors are detected by RAS */
 218 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE   (1<<3)
 219 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE   (1<<4)
 220
 221 /* Context priority level */
 222 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
 223 #define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
 224 #define AMDGPU_CTX_PRIORITY_LOW         -512
 225 #define AMDGPU_CTX_PRIORITY_NORMAL      0
 226 /*
 227  * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
 228  * CAP_SYS_NICE or DRM_MASTER
 229 */
 230 #define AMDGPU_CTX_PRIORITY_HIGH        512
 231 #define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
 232
 233 struct drm_amdgpu_ctx_in {
 234         /** AMDGPU_CTX_OP_* */
 235         __u32   op;
 236         /** For future use, no flags defined so far */
 237         __u32   flags;
 238         __u32   ctx_id;
 239         /** AMDGPU_CTX_PRIORITY_* */
 240         __s32   priority;
 241 };
 242
 243 union drm_amdgpu_ctx_out {
 244                 struct {
 245                         __u32   ctx_id;
 246                         __u32   _pad;
 247                 } alloc;
 248
 249                 struct {
 250                         /** For future use, no flags defined so far */
 251                         __u64   flags;
 252                         /** Number of resets caused by this context so far. */
 253                         __u32   hangs;
 254                         /** Reset status since the last call of the ioctl. */
 255                         __u32   reset_status;
 256                 } state;
 257 };
 258
 259 union drm_amdgpu_ctx {
 260         struct drm_amdgpu_ctx_in in;
 261         union drm_amdgpu_ctx_out out;
 262 };
 263
 264 /* vm ioctl */
 265 #define AMDGPU_VM_OP_RESERVE_VMID       1
 266 #define AMDGPU_VM_OP_UNRESERVE_VMID     2
 267
 268 struct drm_amdgpu_vm_in {
 269         /** AMDGPU_VM_OP_* */
 270         __u32   op;
 271         __u32   flags;
 272 };
 273
 274 struct drm_amdgpu_vm_out {
 275         /** For future use, no flags defined so far */
 276         __u64   flags;
 277 };
 278
 279 union drm_amdgpu_vm {
 280         struct drm_amdgpu_vm_in in;
 281         struct drm_amdgpu_vm_out out;
 282 };
 283
 284 /* sched ioctl */
 285 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE       1
 286 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE       2
 287
 288 struct drm_amdgpu_sched_in {
 289         /* AMDGPU_SCHED_OP_* */
 290         __u32   op;
 291         __u32   fd;
 292         /** AMDGPU_CTX_PRIORITY_* */
 293         __s32   priority;
 294         __u32   ctx_id;
 295 };
 296
 297 union drm_amdgpu_sched {
 298         struct drm_amdgpu_sched_in in;
 299 };
 300
 301 /*
 302  * This is not a reliable API and you should expect it to fail for any
 303  * number of reasons and have fallback path that do not use userptr to
 304  * perform any operation.
 305  */
 306 #define AMDGPU_GEM_USERPTR_READONLY     (1 << 0)
 307 #define AMDGPU_GEM_USERPTR_ANONONLY     (1 << 1)
 308 #define AMDGPU_GEM_USERPTR_VALIDATE     (1 << 2)
 309 #define AMDGPU_GEM_USERPTR_REGISTER     (1 << 3)
 310
 311 struct drm_amdgpu_gem_userptr {
 312         __u64           addr;
 313         __u64           size;
 314         /* AMDGPU_GEM_USERPTR_* */
 315         __u32           flags;
 316         /* Resulting GEM handle */
 317         __u32           handle;
 318 };
 319
 320 /* SI-CI-VI: */
 321 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
 322 #define AMDGPU_TILING_ARRAY_MODE_SHIFT                  0
 323 #define AMDGPU_TILING_ARRAY_MODE_MASK                   0xf
 324 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT                 4
 325 #define AMDGPU_TILING_PIPE_CONFIG_MASK                  0x1f
 326 #define AMDGPU_TILING_TILE_SPLIT_SHIFT                  9
 327 #define AMDGPU_TILING_TILE_SPLIT_MASK                   0x7
 328 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT             12
 329 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK              0x7
 330 #define AMDGPU_TILING_BANK_WIDTH_SHIFT                  15
 331 #define AMDGPU_TILING_BANK_WIDTH_MASK                   0x3
 332 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT                 17
 333 #define AMDGPU_TILING_BANK_HEIGHT_MASK                  0x3
 334 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT           19
 335 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK            0x3
 336 #define AMDGPU_TILING_NUM_BANKS_SHIFT                   21
 337 #define AMDGPU_TILING_NUM_BANKS_MASK                    0x3
 338
 339 /* GFX9 and later: */
 340 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT                0
 341 #define AMDGPU_TILING_SWIZZLE_MODE_MASK                 0x1f
 342 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT             5
 343 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK              0xFFFFFF
 344 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT               29
 345 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK                0x3FFF
 346 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT         43
 347 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK          0x1
 348
 349 /* Set/Get helpers for tiling flags. */
 350 #define AMDGPU_TILING_SET(field, value) \
 351         (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 352 #define AMDGPU_TILING_GET(value, field) \
 353         (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 354
 355 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 356 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 357
 358 /** The same structure is shared for input/output */
 359 struct drm_amdgpu_gem_metadata {
 360         /** GEM Object handle */
 361         __u32   handle;
 362         /** Do we want get or set metadata */
 363         __u32   op;
 364         struct {
 365                 /** For future use, no flags defined so far */
 366                 __u64   flags;
 367                 /** family specific tiling info */
 368                 __u64   tiling_info;
 369                 __u32   data_size_bytes;
 370                 __u32   data[64];
 371         } data;
 372 };
 373
 374 struct drm_amdgpu_gem_mmap_in {
 375         /** the GEM object handle */
 376         __u32 handle;
 377         __u32 _pad;
 378 };
 379
 380 struct drm_amdgpu_gem_mmap_out {
 381         /** mmap offset from the vma offset manager */
 382         __u64 addr_ptr;
 383 };
 384
 385 union drm_amdgpu_gem_mmap {
 386         struct drm_amdgpu_gem_mmap_in   in;
 387         struct drm_amdgpu_gem_mmap_out out;
 388 };
 389
 390 struct drm_amdgpu_gem_wait_idle_in {
 391         /** GEM object handle */
 392         __u32 handle;
 393         /** For future use, no flags defined so far */
 394         __u32 flags;
 395         /** Absolute timeout to wait */
 396         __u64 timeout;
 397 };
 398
 399 struct drm_amdgpu_gem_wait_idle_out {
 400         /** BO status:  0 - BO is idle, 1 - BO is busy */
 401         __u32 status;
 402         /** Returned current memory domain */
 403         __u32 domain;
 404 };
 405
 406 union drm_amdgpu_gem_wait_idle {
 407         struct drm_amdgpu_gem_wait_idle_in  in;
 408         struct drm_amdgpu_gem_wait_idle_out out;
 409 };
 410
 411 struct drm_amdgpu_wait_cs_in {
 412         /* Command submission handle
 413          * handle equals 0 means none to wait for
 414          * handle equals ~0ull means wait for the latest sequence number
 415          */
 416         __u64 handle;
 417         /** Absolute timeout to wait */
 418         __u64 timeout;
 419         __u32 ip_type;
 420         __u32 ip_instance;
 421         __u32 ring;
 422         __u32 ctx_id;
 423 };
 424
 425 struct drm_amdgpu_wait_cs_out {
 426         /** CS status:  0 - CS completed, 1 - CS still busy */
 427         __u64 status;
 428 };
 429
 430 union drm_amdgpu_wait_cs {
 431         struct drm_amdgpu_wait_cs_in in;
 432         struct drm_amdgpu_wait_cs_out out;
 433 };
 434
 435 struct drm_amdgpu_fence {
 436         __u32 ctx_id;
 437         __u32 ip_type;
 438         __u32 ip_instance;
 439         __u32 ring;
 440         __u64 seq_no;
 441 };
 442
 443 struct drm_amdgpu_wait_fences_in {
 444         /** This points to uint64_t * which points to fences */
 445         __u64 fences;
 446         __u32 fence_count;
 447         __u32 wait_all;
 448         __u64 timeout_ns;
 449 };
 450
 451 struct drm_amdgpu_wait_fences_out {
 452         __u32 status;
 453         __u32 first_signaled;
 454 };
 455
 456 union drm_amdgpu_wait_fences {
 457         struct drm_amdgpu_wait_fences_in in;
 458         struct drm_amdgpu_wait_fences_out out;
 459 };
 460
 461 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO       0
 462 #define AMDGPU_GEM_OP_SET_PLACEMENT             1
 463
 464 /* Sets or returns a value associated with a buffer. */
 465 struct drm_amdgpu_gem_op {
 466         /** GEM object handle */
 467         __u32   handle;
 468         /** AMDGPU_GEM_OP_* */
 469         __u32   op;
 470         /** Input or return value */
 471         __u64   value;
 472 };
 473
 474 #define AMDGPU_VA_OP_MAP                        1
 475 #define AMDGPU_VA_OP_UNMAP                      2
 476 #define AMDGPU_VA_OP_CLEAR                      3
 477 #define AMDGPU_VA_OP_REPLACE                    4
 478
 479 /* Delay the page table update till the next CS */
 480 #define AMDGPU_VM_DELAY_UPDATE          (1 << 0)
 481
 482 /* Mapping flags */
 483 /* readable mapping */
 484 #define AMDGPU_VM_PAGE_READABLE         (1 << 1)
 485 /* writable mapping */
 486 #define AMDGPU_VM_PAGE_WRITEABLE        (1 << 2)
 487 /* executable mapping, new for VI */
 488 #define AMDGPU_VM_PAGE_EXECUTABLE       (1 << 3)
 489 /* partially resident texture */
 490 #define AMDGPU_VM_PAGE_PRT              (1 << 4)
 491 /* MTYPE flags use bit 5 to 8 */
 492 #define AMDGPU_VM_MTYPE_MASK            (0xf << 5)
 493 /* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
 494 #define AMDGPU_VM_MTYPE_DEFAULT         (0 << 5)
 495 /* Use NC MTYPE instead of default MTYPE */
 496 #define AMDGPU_VM_MTYPE_NC              (1 << 5)
 497 /* Use WC MTYPE instead of default MTYPE */
 498 #define AMDGPU_VM_MTYPE_WC              (2 << 5)
 499 /* Use CC MTYPE instead of default MTYPE */
 500 #define AMDGPU_VM_MTYPE_CC              (3 << 5)
 501 /* Use UC MTYPE instead of default MTYPE */
 502 #define AMDGPU_VM_MTYPE_UC              (4 << 5)
 503 /* Use RW MTYPE instead of default MTYPE */
 504 #define AMDGPU_VM_MTYPE_RW              (5 << 5)
 505
 506 struct drm_amdgpu_gem_va {
 507         /** GEM object handle */
 508         __u32 handle;
 509         __u32 _pad;
 510         /** AMDGPU_VA_OP_* */
 511         __u32 operation;
 512         /** AMDGPU_VM_PAGE_* */
 513         __u32 flags;
 514         /** va address to assign . Must be correctly aligned.*/
 515         __u64 va_address;
 516         /** Specify offset inside of BO to assign. Must be correctly aligned.*/
 517         __u64 offset_in_bo;
 518         /** Specify mapping size. Must be correctly aligned. */
 519         __u64 map_size;
 520 };
 521
 522 #define AMDGPU_HW_IP_GFX          0
 523 #define AMDGPU_HW_IP_COMPUTE      1
 524 #define AMDGPU_HW_IP_DMA          2
 525 #define AMDGPU_HW_IP_UVD          3
 526 #define AMDGPU_HW_IP_VCE          4
 527 #define AMDGPU_HW_IP_UVD_ENC      5
 528 #define AMDGPU_HW_IP_VCN_DEC      6
 529 #define AMDGPU_HW_IP_VCN_ENC      7
 530 #define AMDGPU_HW_IP_VCN_JPEG     8
 531 #define AMDGPU_HW_IP_NUM          9
 532
 533 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 534
 535 #define AMDGPU_CHUNK_ID_IB              0x01
 536 #define AMDGPU_CHUNK_ID_FENCE           0x02
 537 #define AMDGPU_CHUNK_ID_DEPENDENCIES    0x03
 538 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN      0x04
 539 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
 540 #define AMDGPU_CHUNK_ID_BO_HANDLES      0x06
 541 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES  0x07
 542 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x08
 543 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x09
 544
 545 struct drm_amdgpu_cs_chunk {
 546         __u32           chunk_id;
 547         __u32           length_dw;
 548         __u64           chunk_data;
 549 };
 550
 551 struct drm_amdgpu_cs_in {
 552         /** Rendering context id */
 553         __u32           ctx_id;
 554         /**  Handle of resource list associated with CS */
 555         __u32           bo_list_handle;
 556         __u32           num_chunks;
 557         __u32           _pad;
 558         /** this points to __u64 * which point to cs chunks */
 559         __u64           chunks;
 560 };
 561
 562 struct drm_amdgpu_cs_out {
 563         __u64 handle;
 564 };
 565
 566 union drm_amdgpu_cs {
 567         struct drm_amdgpu_cs_in in;
 568         struct drm_amdgpu_cs_out out;
 569 };
 570
 571 /* Specify flags to be used for IB */
 572
 573 /* This IB should be submitted to CE */
 574 #define AMDGPU_IB_FLAG_CE       (1<<0)
 575
 576 /* Preamble flag, which means the IB could be dropped if no context switch */
 577 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 578
 579 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
 580 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
 581
 582 /* The IB fence should do the L2 writeback but not invalidate any shader
 583  * caches (L2/vL1/sL1/I$). */
 584 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
 585
 586 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
 587  * This will reset wave ID counters for the IB.
 588  */
 589 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
 590
 591 struct drm_amdgpu_cs_chunk_ib {
 592         __u32 _pad;
 593         /** AMDGPU_IB_FLAG_* */
 594         __u32 flags;
 595         /** Virtual address to begin IB execution */
 596         __u64 va_start;
 597         /** Size of submission */
 598         __u32 ib_bytes;
 599         /** HW IP to submit to */
 600         __u32 ip_type;
 601         /** HW IP index of the same type to submit to  */
 602         __u32 ip_instance;
 603         /** Ring index to submit to */
 604         __u32 ring;
 605 };
 606
 607 struct drm_amdgpu_cs_chunk_dep {
 608         __u32 ip_type;
 609         __u32 ip_instance;
 610         __u32 ring;
 611         __u32 ctx_id;
 612         __u64 handle;
 613 };
 614
 615 struct drm_amdgpu_cs_chunk_fence {
 616         __u32 handle;
 617         __u32 offset;
 618 };
 619
 620 struct drm_amdgpu_cs_chunk_sem {
 621         __u32 handle;
 622 };
 623
 624 struct drm_amdgpu_cs_chunk_syncobj {
 625        __u32 handle;
 626        __u32 flags;
 627        __u64 point;
 628 };
 629
 630 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ      0
 631 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD   1
 632 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
 633
 634 union drm_amdgpu_fence_to_handle {
 635         struct {
 636                 struct drm_amdgpu_fence fence;
 637                 __u32 what;
 638                 __u32 pad;
 639         } in;
 640         struct {
 641                 __u32 handle;
 642         } out;
 643 };
 644
 645 struct drm_amdgpu_cs_chunk_data {
 646         union {
 647                 struct drm_amdgpu_cs_chunk_ib           ib_data;
 648                 struct drm_amdgpu_cs_chunk_fence        fence_data;
 649         };
 650 };
 651
 652 /**
 653  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
 654  *
 655  */
 656 #define AMDGPU_IDS_FLAGS_FUSION         0x1
 657 #define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
 658
 659 /* indicate if acceleration can be working */
 660 #define AMDGPU_INFO_ACCEL_WORKING               0x00
 661 /* get the crtc_id from the mode object id? */
 662 #define AMDGPU_INFO_CRTC_FROM_ID                0x01
 663 /* query hw IP info */
 664 #define AMDGPU_INFO_HW_IP_INFO                  0x02
 665 /* query hw IP instance count for the specified type */
 666 #define AMDGPU_INFO_HW_IP_COUNT                 0x03
 667 /* timestamp for GL_ARB_timer_query */
 668 #define AMDGPU_INFO_TIMESTAMP                   0x05
 669 /* Query the firmware version */
 670 #define AMDGPU_INFO_FW_VERSION                  0x0e
 671         /* Subquery id: Query VCE firmware version */
 672         #define AMDGPU_INFO_FW_VCE              0x1
 673         /* Subquery id: Query UVD firmware version */
 674         #define AMDGPU_INFO_FW_UVD              0x2
 675         /* Subquery id: Query GMC firmware version */
 676         #define AMDGPU_INFO_FW_GMC              0x03
 677         /* Subquery id: Query GFX ME firmware version */
 678         #define AMDGPU_INFO_FW_GFX_ME           0x04
 679         /* Subquery id: Query GFX PFP firmware version */
 680         #define AMDGPU_INFO_FW_GFX_PFP          0x05
 681         /* Subquery id: Query GFX CE firmware version */
 682         #define AMDGPU_INFO_FW_GFX_CE           0x06
 683         /* Subquery id: Query GFX RLC firmware version */
 684         #define AMDGPU_INFO_FW_GFX_RLC          0x07
 685         /* Subquery id: Query GFX MEC firmware version */
 686         #define AMDGPU_INFO_FW_GFX_MEC          0x08
 687         /* Subquery id: Query SMC firmware version */
 688         #define AMDGPU_INFO_FW_SMC              0x0a
 689         /* Subquery id: Query SDMA firmware version */
 690         #define AMDGPU_INFO_FW_SDMA             0x0b
 691         /* Subquery id: Query PSP SOS firmware version */
 692         #define AMDGPU_INFO_FW_SOS              0x0c
 693         /* Subquery id: Query PSP ASD firmware version */
 694         #define AMDGPU_INFO_FW_ASD              0x0d
 695         /* Subquery id: Query VCN firmware version */
 696         #define AMDGPU_INFO_FW_VCN              0x0e
 697         /* Subquery id: Query GFX RLC SRLC firmware version */
 698         #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
 699         /* Subquery id: Query GFX RLC SRLG firmware version */
 700         #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
 701         /* Subquery id: Query GFX RLC SRLS firmware version */
 702         #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
 703         /* Subquery id: Query DMCU firmware version */
 704         #define AMDGPU_INFO_FW_DMCU             0x12
 705         #define AMDGPU_INFO_FW_TA               0x13
 706         /* Subquery id: Query DMCUB firmware version */
 707         #define AMDGPU_INFO_FW_DMCUB            0x14
 708
 709 /* number of bytes moved for TTM migration */
 710 #define AMDGPU_INFO_NUM_BYTES_MOVED             0x0f
 711 /* the used VRAM size */
 712 #define AMDGPU_INFO_VRAM_USAGE                  0x10
 713 /* the used GTT size */
 714 #define AMDGPU_INFO_GTT_USAGE                   0x11
 715 /* Information about GDS, etc. resource configuration */
 716 #define AMDGPU_INFO_GDS_CONFIG                  0x13
 717 /* Query information about VRAM and GTT domains */
 718 #define AMDGPU_INFO_VRAM_GTT                    0x14
 719 /* Query information about register in MMR address space*/
 720 #define AMDGPU_INFO_READ_MMR_REG                0x15
 721 /* Query information about device: rev id, family, etc. */
 722 #define AMDGPU_INFO_DEV_INFO                    0x16
 723 /* visible vram usage */
 724 #define AMDGPU_INFO_VIS_VRAM_USAGE              0x17
 725 /* number of TTM buffer evictions */
 726 #define AMDGPU_INFO_NUM_EVICTIONS               0x18
 727 /* Query memory about VRAM and GTT domains */
 728 #define AMDGPU_INFO_MEMORY                      0x19
 729 /* Query vce clock table */
 730 #define AMDGPU_INFO_VCE_CLOCK_TABLE             0x1A
 731 /* Query vbios related information */
 732 #define AMDGPU_INFO_VBIOS                       0x1B
 733         /* Subquery id: Query vbios size */
 734         #define AMDGPU_INFO_VBIOS_SIZE          0x1
 735         /* Subquery id: Query vbios image */
 736         #define AMDGPU_INFO_VBIOS_IMAGE         0x2
 737 /* Query UVD handles */
 738 #define AMDGPU_INFO_NUM_HANDLES                 0x1C
 739 /* Query sensor related information */
 740 #define AMDGPU_INFO_SENSOR                      0x1D
 741         /* Subquery id: Query GPU shader clock */
 742         #define AMDGPU_INFO_SENSOR_GFX_SCLK             0x1
 743         /* Subquery id: Query GPU memory clock */
 744         #define AMDGPU_INFO_SENSOR_GFX_MCLK             0x2
 745         /* Subquery id: Query GPU temperature */
 746         #define AMDGPU_INFO_SENSOR_GPU_TEMP             0x3
 747         /* Subquery id: Query GPU load */
 748         #define AMDGPU_INFO_SENSOR_GPU_LOAD             0x4
 749         /* Subquery id: Query average GPU power */
 750         #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER        0x5
 751         /* Subquery id: Query northbridge voltage */
 752         #define AMDGPU_INFO_SENSOR_VDDNB                0x6
 753         /* Subquery id: Query graphics voltage */
 754         #define AMDGPU_INFO_SENSOR_VDDGFX               0x7
 755         /* Subquery id: Query GPU stable pstate shader clock */
 756         #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK               0x8
 757         /* Subquery id: Query GPU stable pstate memory clock */
 758         #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK               0x9
 759 /* Number of VRAM page faults on CPU access. */
 760 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
 761 #define AMDGPU_INFO_VRAM_LOST_COUNTER           0x1F
 762 /* query ras mask of enabled features*/
 763 #define AMDGPU_INFO_RAS_ENABLED_FEATURES        0x20
 764
 765 /* RAS MASK: UMC (VRAM) */
 766 #define AMDGPU_INFO_RAS_ENABLED_UMC                     (1 << 0)
 767 /* RAS MASK: SDMA */
 768 #define AMDGPU_INFO_RAS_ENABLED_SDMA                    (1 << 1)
 769 /* RAS MASK: GFX */
 770 #define AMDGPU_INFO_RAS_ENABLED_GFX                     (1 << 2)
 771 /* RAS MASK: MMHUB */
 772 #define AMDGPU_INFO_RAS_ENABLED_MMHUB                   (1 << 3)
 773 /* RAS MASK: ATHUB */
 774 #define AMDGPU_INFO_RAS_ENABLED_ATHUB                   (1 << 4)
 775 /* RAS MASK: PCIE */
 776 #define AMDGPU_INFO_RAS_ENABLED_PCIE                    (1 << 5)
 777 /* RAS MASK: HDP */
 778 #define AMDGPU_INFO_RAS_ENABLED_HDP                     (1 << 6)
 779 /* RAS MASK: XGMI */
 780 #define AMDGPU_INFO_RAS_ENABLED_XGMI                    (1 << 7)
 781 /* RAS MASK: DF */
 782 #define AMDGPU_INFO_RAS_ENABLED_DF                      (1 << 8)
 783 /* RAS MASK: SMN */
 784 #define AMDGPU_INFO_RAS_ENABLED_SMN                     (1 << 9)
 785 /* RAS MASK: SEM */
 786 #define AMDGPU_INFO_RAS_ENABLED_SEM                     (1 << 10)
 787 /* RAS MASK: MP0 */
 788 #define AMDGPU_INFO_RAS_ENABLED_MP0                     (1 << 11)
 789 /* RAS MASK: MP1 */
 790 #define AMDGPU_INFO_RAS_ENABLED_MP1                     (1 << 12)
 791 /* RAS MASK: FUSE */
 792 #define AMDGPU_INFO_RAS_ENABLED_FUSE                    (1 << 13)
 793
 794 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT  0
 795 #define AMDGPU_INFO_MMR_SE_INDEX_MASK   0xff
 796 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT  8
 797 #define AMDGPU_INFO_MMR_SH_INDEX_MASK   0xff
 798
 799 struct drm_amdgpu_query_fw {
 800         /** AMDGPU_INFO_FW_* */
 801         __u32 fw_type;
 802         /**
 803          * Index of the IP if there are more IPs of
 804          * the same type.
 805          */
 806         __u32 ip_instance;
 807         /**
 808          * Index of the engine. Whether this is used depends
 809          * on the firmware type. (e.g. MEC, SDMA)
 810          */
 811         __u32 index;
 812         __u32 _pad;
 813 };
 814
 815 /* Input structure for the INFO ioctl */
 816 struct drm_amdgpu_info {
 817         /* Where the return value will be stored */
 818         __u64 return_pointer;
 819         /* The size of the return value. Just like "size" in "snprintf",
 820          * it limits how many bytes the kernel can write. */
 821         __u32 return_size;
 822         /* The query request id. */
 823         __u32 query;
 824
 825         union {
 826                 struct {
 827                         __u32 id;
 828                         __u32 _pad;
 829                 } mode_crtc;
 830
 831                 struct {
 832                         /** AMDGPU_HW_IP_* */
 833                         __u32 type;
 834                         /**
 835                          * Index of the IP if there are more IPs of the same
 836                          * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
 837                          */
 838                         __u32 ip_instance;
 839                 } query_hw_ip;
 840
 841                 struct {
 842                         __u32 dword_offset;
 843                         /** number of registers to read */
 844                         __u32 count;
 845                         __u32 instance;
 846                         /** For future use, no flags defined so far */
 847                         __u32 flags;
 848                 } read_mmr_reg;
 849
 850                 struct drm_amdgpu_query_fw query_fw;
 851
 852                 struct {
 853                         __u32 type;
 854                         __u32 offset;
 855                 } vbios_info;
 856
 857                 struct {
 858                         __u32 type;
 859                 } sensor_info;
 860         };
 861 };
 862
 863 struct drm_amdgpu_info_gds {
 864         /** GDS GFX partition size */
 865         __u32 gds_gfx_partition_size;
 866         /** GDS compute partition size */
 867         __u32 compute_partition_size;
 868         /** total GDS memory size */
 869         __u32 gds_total_size;
 870         /** GWS size per GFX partition */
 871         __u32 gws_per_gfx_partition;
 872         /** GSW size per compute partition */
 873         __u32 gws_per_compute_partition;
 874         /** OA size per GFX partition */
 875         __u32 oa_per_gfx_partition;
 876         /** OA size per compute partition */
 877         __u32 oa_per_compute_partition;
 878         __u32 _pad;
 879 };
 880
 881 struct drm_amdgpu_info_vram_gtt {
 882         __u64 vram_size;
 883         __u64 vram_cpu_accessible_size;
 884         __u64 gtt_size;
 885 };
 886
 887 struct drm_amdgpu_heap_info {
 888         /** max. physical memory */
 889         __u64 total_heap_size;
 890
 891         /** Theoretical max. available memory in the given heap */
 892         __u64 usable_heap_size;
 893
 894         /**
 895          * Number of bytes allocated in the heap. This includes all processes
 896          * and private allocations in the kernel. It changes when new buffers
 897          * are allocated, freed, and moved. It cannot be larger than
 898          * heap_size.
 899          */
 900         __u64 heap_usage;
 901
 902         /**
 903          * Theoretical possible max. size of buffer which
 904          * could be allocated in the given heap
 905          */
 906         __u64 max_allocation;
 907 };
 908
 909 struct drm_amdgpu_memory_info {
 910         struct drm_amdgpu_heap_info vram;
 911         struct drm_amdgpu_heap_info cpu_accessible_vram;
 912         struct drm_amdgpu_heap_info gtt;
 913 };
 914
 915 struct drm_amdgpu_info_firmware {
 916         __u32 ver;
 917         __u32 feature;
 918 };
 919
 920 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
 921 #define AMDGPU_VRAM_TYPE_GDDR1 1
 922 #define AMDGPU_VRAM_TYPE_DDR2  2
 923 #define AMDGPU_VRAM_TYPE_GDDR3 3
 924 #define AMDGPU_VRAM_TYPE_GDDR4 4
 925 #define AMDGPU_VRAM_TYPE_GDDR5 5
 926 #define AMDGPU_VRAM_TYPE_HBM   6
 927 #define AMDGPU_VRAM_TYPE_DDR3  7
 928 #define AMDGPU_VRAM_TYPE_DDR4  8
 929 #define AMDGPU_VRAM_TYPE_GDDR6 9
 930
 931 struct drm_amdgpu_info_device {
 932         /** PCI Device ID */
 933         __u32 device_id;
 934         /** Internal chip revision: A0, A1, etc.) */
 935         __u32 chip_rev;
 936         __u32 external_rev;
 937         /** Revision id in PCI Config space */
 938         __u32 pci_rev;
 939         __u32 family;
 940         __u32 num_shader_engines;
 941         __u32 num_shader_arrays_per_engine;
 942         /* in KHz */
 943         __u32 gpu_counter_freq;
 944         __u64 max_engine_clock;
 945         __u64 max_memory_clock;
 946         /* cu information */
 947         __u32 cu_active_number;
 948         /* NOTE: cu_ao_mask is INVALID, DON'T use it */
 949         __u32 cu_ao_mask;
 950         __u32 cu_bitmap[4][4];
 951         /** Render backend pipe mask. One render backend is CB+DB. */
 952         __u32 enabled_rb_pipes_mask;
 953         __u32 num_rb_pipes;
 954         __u32 num_hw_gfx_contexts;
 955         __u32 _pad;
 956         __u64 ids_flags;
 957         /** Starting virtual address for UMDs. */
 958         __u64 virtual_address_offset;
 959         /** The maximum virtual address */
 960         __u64 virtual_address_max;
 961         /** Required alignment of virtual addresses. */
 962         __u32 virtual_address_alignment;
 963         /** Page table entry - fragment size */
 964         __u32 pte_fragment_size;
 965         __u32 gart_page_size;
 966         /** constant engine ram size*/
 967         __u32 ce_ram_size;
 968         /** video memory type info*/
 969         __u32 vram_type;
 970         /** video memory bit width*/
 971         __u32 vram_bit_width;
 972         /* vce harvesting instance */
 973         __u32 vce_harvest_config;
 974         /* gfx double offchip LDS buffers */
 975         __u32 gc_double_offchip_lds_buf;
 976         /* NGG Primitive Buffer */
 977         __u64 prim_buf_gpu_addr;
 978         /* NGG Position Buffer */
 979         __u64 pos_buf_gpu_addr;
 980         /* NGG Control Sideband */
 981         __u64 cntl_sb_buf_gpu_addr;
 982         /* NGG Parameter Cache */
 983         __u64 param_buf_gpu_addr;
 984         __u32 prim_buf_size;
 985         __u32 pos_buf_size;
 986         __u32 cntl_sb_buf_size;
 987         __u32 param_buf_size;
 988         /* wavefront size*/
 989         __u32 wave_front_size;
 990         /* shader visible vgprs*/
 991         __u32 num_shader_visible_vgprs;
 992         /* CU per shader array*/
 993         __u32 num_cu_per_sh;
 994         /* number of tcc blocks*/
 995         __u32 num_tcc_blocks;
 996         /* gs vgt table depth*/
 997         __u32 gs_vgt_table_depth;
 998         /* gs primitive buffer depth*/
 999         __u32 gs_prim_buffer_depth;
1000         /* max gs wavefront per vgt*/
1001         __u32 max_gs_waves_per_vgt;
1002         __u32 _pad1;
1003         /* always on cu bitmap */
1004         __u32 cu_ao_bitmap[4][4];
1005         /** Starting high virtual address for UMDs. */
1006         __u64 high_va_offset;
1007         /** The maximum high virtual address */
1008         __u64 high_va_max;
1009         /* gfx10 pa_sc_tile_steering_override */
1010         __u32 pa_sc_tile_steering_override;
1011         /* disabled TCCs */
1012         __u64 tcc_disabled_mask;
1013 };
1014
1015 struct drm_amdgpu_info_hw_ip {
1016         /** Version of h/w IP */
1017         __u32  hw_ip_version_major;
1018         __u32  hw_ip_version_minor;
1019         /** Capabilities */
1020         __u64  capabilities_flags;
1021         /** command buffer address start alignment*/
1022         __u32  ib_start_alignment;
1023         /** command buffer size alignment*/
1024         __u32  ib_size_alignment;
1025         /** Bitmask of available rings. Bit 0 means ring 0, etc. */
1026         __u32  available_rings;
1027         __u32  _pad;
1028 };
1029
1030 struct drm_amdgpu_info_num_handles {
1031         /** Max handles as supported by firmware for UVD */
1032         __u32  uvd_max_handles;
1033         /** Handles currently in use for UVD */
1034         __u32  uvd_used_handles;
1035 };
1036
1037 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES          6
1038
1039 struct drm_amdgpu_info_vce_clock_table_entry {
1040         /** System clock */
1041         __u32 sclk;
1042         /** Memory clock */
1043         __u32 mclk;
1044         /** VCE clock */
1045         __u32 eclk;
1046         __u32 pad;
1047 };
1048
1049 struct drm_amdgpu_info_vce_clock_table {
1050         struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
1051         __u32 num_valid_entries;
1052         __u32 pad;
1053 };
1054
1055 /*
1056  * Supported GPU families
1057  */
1058 #define AMDGPU_FAMILY_UNKNOWN                   0
1059 #define AMDGPU_FAMILY_SI                        110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
1060 #define AMDGPU_FAMILY_CI                        120 /* Bonaire, Hawaii */
1061 #define AMDGPU_FAMILY_KV                        125 /* Kaveri, Kabini, Mullins */
1062 #define AMDGPU_FAMILY_VI                        130 /* Iceland, Tonga */
1063 #define AMDGPU_FAMILY_CZ                        135 /* Carrizo, Stoney */
1064 #define AMDGPU_FAMILY_AI                        141 /* Vega10 */
1065 #define AMDGPU_FAMILY_RV                        142 /* Raven */
1066 #define AMDGPU_FAMILY_NV                        143 /* Navi10 */
1067
1068 #if defined(__cplusplus)
1069 }
1070 #endif
1071
1072 #endif