sound/soc/atmel/atmel-i2s.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Atmel I2S controller
   4  *
   5  * Copyright (C) 2015 Atmel Corporation
   6  *
   7  * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/device.h>
  13 #include <linux/slab.h>
  14 #include <linux/delay.h>
  15 #include <linux/io.h>
  16 #include <linux/clk.h>
  17 #include <linux/mfd/syscon.h>
  18
  19 #include <sound/core.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/initval.h>
  23 #include <sound/soc.h>
  24 #include <sound/dmaengine_pcm.h>
  25
  26 #define ATMEL_I2SC_MAX_TDM_CHANNELS     8
  27
  28 /*
  29  * ---- I2S Controller Register map ----
  30  */
  31 #define ATMEL_I2SC_CR           0x0000  /* Control Register */
  32 #define ATMEL_I2SC_MR           0x0004  /* Mode Register */
  33 #define ATMEL_I2SC_SR           0x0008  /* Status Register */
  34 #define ATMEL_I2SC_SCR          0x000c  /* Status Clear Register */
  35 #define ATMEL_I2SC_SSR          0x0010  /* Status Set Register */
  36 #define ATMEL_I2SC_IER          0x0014  /* Interrupt Enable Register */
  37 #define ATMEL_I2SC_IDR          0x0018  /* Interrupt Disable Register */
  38 #define ATMEL_I2SC_IMR          0x001c  /* Interrupt Mask Register */
  39 #define ATMEL_I2SC_RHR          0x0020  /* Receiver Holding Register */
  40 #define ATMEL_I2SC_THR          0x0024  /* Transmitter Holding Register */
  41 #define ATMEL_I2SC_VERSION      0x0028  /* Version Register */
  42
  43 /*
  44  * ---- Control Register (Write-only) ----
  45  */
  46 #define ATMEL_I2SC_CR_RXEN      BIT(0)  /* Receiver Enable */
  47 #define ATMEL_I2SC_CR_RXDIS     BIT(1)  /* Receiver Disable */
  48 #define ATMEL_I2SC_CR_CKEN      BIT(2)  /* Clock Enable */
  49 #define ATMEL_I2SC_CR_CKDIS     BIT(3)  /* Clock Disable */
  50 #define ATMEL_I2SC_CR_TXEN      BIT(4)  /* Transmitter Enable */
  51 #define ATMEL_I2SC_CR_TXDIS     BIT(5)  /* Transmitter Disable */
  52 #define ATMEL_I2SC_CR_SWRST     BIT(7)  /* Software Reset */
  53
  54 /*
  55  * ---- Mode Register (Read/Write) ----
  56  */
  57 #define ATMEL_I2SC_MR_MODE_MASK         GENMASK(0, 0)
  58 #define ATMEL_I2SC_MR_MODE_SLAVE        (0 << 0)
  59 #define ATMEL_I2SC_MR_MODE_MASTER       (1 << 0)
  60
  61 #define ATMEL_I2SC_MR_DATALENGTH_MASK           GENMASK(4, 2)
  62 #define ATMEL_I2SC_MR_DATALENGTH_32_BITS        (0 << 2)
  63 #define ATMEL_I2SC_MR_DATALENGTH_24_BITS        (1 << 2)
  64 #define ATMEL_I2SC_MR_DATALENGTH_20_BITS        (2 << 2)
  65 #define ATMEL_I2SC_MR_DATALENGTH_18_BITS        (3 << 2)
  66 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS        (4 << 2)
  67 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT        (5 << 2)
  68 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS         (6 << 2)
  69 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2)
  70
  71 #define ATMEL_I2SC_MR_FORMAT_MASK       GENMASK(7, 6)
  72 #define ATMEL_I2SC_MR_FORMAT_I2S        (0 << 6)
  73 #define ATMEL_I2SC_MR_FORMAT_LJ         (1 << 6)  /* Left Justified */
  74 #define ATMEL_I2SC_MR_FORMAT_TDM        (2 << 6)
  75 #define ATMEL_I2SC_MR_FORMAT_TDMLJ      (3 << 6)
  76
  77 /* Left audio samples duplicated to right audio channel */
  78 #define ATMEL_I2SC_MR_RXMONO            BIT(8)
  79
  80 /* Receiver uses one DMA channel ... */
  81 #define ATMEL_I2SC_MR_RXDMA_MASK        GENMASK(9, 9)
  82 #define ATMEL_I2SC_MR_RXDMA_SINGLE      (0 << 9)  /* for all audio channels */
  83 #define ATMEL_I2SC_MR_RXDMA_MULTIPLE    (1 << 9)  /* per audio channel */
  84
  85 /* I2SDO output of I2SC is internally connected to I2SDI input */
  86 #define ATMEL_I2SC_MR_RXLOOP            BIT(10)
  87
  88 /* Left audio samples duplicated to right audio channel */
  89 #define ATMEL_I2SC_MR_TXMONO            BIT(12)
  90
  91 /* Transmitter uses one DMA channel ... */
  92 #define ATMEL_I2SC_MR_TXDMA_MASK        GENMASK(13, 13)
  93 #define ATMEL_I2SC_MR_TXDMA_SINGLE      (0 << 13)  /* for all audio channels */
  94 #define ATMEL_I2SC_MR_TXDME_MULTIPLE    (1 << 13)  /* per audio channel */
  95
  96 /* x sample transmitted when underrun */
  97 #define ATMEL_I2SC_MR_TXSAME_MASK       GENMASK(14, 14)
  98 #define ATMEL_I2SC_MR_TXSAME_ZERO       (0 << 14)  /* Zero sample */
  99 #define ATMEL_I2SC_MR_TXSAME_PREVIOUS   (1 << 14)  /* Previous sample */
 100
 101 /* Audio Clock to I2SC Master Clock ratio */
 102 #define ATMEL_I2SC_MR_IMCKDIV_MASK      GENMASK(21, 16)
 103 #define ATMEL_I2SC_MR_IMCKDIV(div) \
 104         (((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK)
 105
 106 /* Master Clock to fs ratio */
 107 #define ATMEL_I2SC_MR_IMCKFS_MASK       GENMASK(29, 24)
 108 #define ATMEL_I2SC_MR_IMCKFS(fs) \
 109         (((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK)
 110
 111 /* Master Clock mode */
 112 #define ATMEL_I2SC_MR_IMCKMODE_MASK     GENMASK(30, 30)
 113 /* 0: No master clock generated (selected clock drives I2SCK pin) */
 114 #define ATMEL_I2SC_MR_IMCKMODE_I2SCK    (0 << 30)
 115 /* 1: master clock generated (internally generated clock drives I2SMCK pin) */
 116 #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK   (1 << 30)
 117
 118 /* Slot Width */
 119 /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
 120 /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
 121 #define ATMEL_I2SC_MR_IWS               BIT(31)
 122
 123 /*
 124  * ---- Status Registers ----
 125  */
 126 #define ATMEL_I2SC_SR_RXEN      BIT(0)  /* Receiver Enabled */
 127 #define ATMEL_I2SC_SR_RXRDY     BIT(1)  /* Receive Ready */
 128 #define ATMEL_I2SC_SR_RXOR      BIT(2)  /* Receive Overrun */
 129
 130 #define ATMEL_I2SC_SR_TXEN      BIT(4)  /* Transmitter Enabled */
 131 #define ATMEL_I2SC_SR_TXRDY     BIT(5)  /* Transmit Ready */
 132 #define ATMEL_I2SC_SR_TXUR      BIT(6)  /* Transmit Underrun */
 133
 134 /* Receive Overrun Channel */
 135 #define ATMEL_I2SC_SR_RXORCH_MASK       GENMASK(15, 8)
 136 #define ATMEL_I2SC_SR_RXORCH(ch)        (1 << (((ch) & 0x7) + 8))
 137
 138 /* Transmit Underrun Channel */
 139 #define ATMEL_I2SC_SR_TXURCH_MASK       GENMASK(27, 20)
 140 #define ATMEL_I2SC_SR_TXURCH(ch)        (1 << (((ch) & 0x7) + 20))
 141
 142 /*
 143  * ---- Interrupt Enable/Disable/Mask Registers ----
 144  */
 145 #define ATMEL_I2SC_INT_RXRDY    ATMEL_I2SC_SR_RXRDY
 146 #define ATMEL_I2SC_INT_RXOR     ATMEL_I2SC_SR_RXOR
 147 #define ATMEL_I2SC_INT_TXRDY    ATMEL_I2SC_SR_TXRDY
 148 #define ATMEL_I2SC_INT_TXUR     ATMEL_I2SC_SR_TXUR
 149
 150 static const struct regmap_config atmel_i2s_regmap_config = {
 151         .reg_bits = 32,
 152         .reg_stride = 4,
 153         .val_bits = 32,
 154         .max_register = ATMEL_I2SC_VERSION,
 155 };
 156
 157 struct atmel_i2s_gck_param {
 158         int             fs;
 159         unsigned long   mck;
 160         int             imckdiv;
 161         int             imckfs;
 162 };
 163
 164 #define I2S_MCK_12M288          12288000UL
 165 #define I2S_MCK_11M2896         11289600UL
 166
 167 /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */
 168 static const struct atmel_i2s_gck_param gck_params[] = {
 169         /* mck = 12.288MHz */
 170         {  8000, I2S_MCK_12M288, 0, 47},        /* mck = 1536 fs */
 171         { 16000, I2S_MCK_12M288, 1, 47},        /* mck =  768 fs */
 172         { 24000, I2S_MCK_12M288, 3, 63},        /* mck =  512 fs */
 173         { 32000, I2S_MCK_12M288, 3, 47},        /* mck =  384 fs */
 174         { 48000, I2S_MCK_12M288, 7, 63},        /* mck =  256 fs */
 175         { 64000, I2S_MCK_12M288, 7, 47},        /* mck =  192 fs */
 176         { 96000, I2S_MCK_12M288, 7, 31},        /* mck =  128 fs */
 177         {192000, I2S_MCK_12M288, 7, 15},        /* mck =   64 fs */
 178
 179         /* mck = 11.2896MHz */
 180         { 11025, I2S_MCK_11M2896, 1, 63},       /* mck = 1024 fs */
 181         { 22050, I2S_MCK_11M2896, 3, 63},       /* mck =  512 fs */
 182         { 44100, I2S_MCK_11M2896, 7, 63},       /* mck =  256 fs */
 183         { 88200, I2S_MCK_11M2896, 7, 31},       /* mck =  128 fs */
 184         {176400, I2S_MCK_11M2896, 7, 15},       /* mck =   64 fs */
 185 };
 186
 187 struct atmel_i2s_dev;
 188
 189 struct atmel_i2s_caps {
 190         int     (*mck_init)(struct atmel_i2s_dev *, struct device_node *np);
 191 };
 192
 193 struct atmel_i2s_dev {
 194         struct device                           *dev;
 195         struct regmap                           *regmap;
 196         struct clk                              *pclk;
 197         struct clk                              *gclk;
 198         struct snd_dmaengine_dai_dma_data       playback;
 199         struct snd_dmaengine_dai_dma_data       capture;
 200         unsigned int                            fmt;
 201         const struct atmel_i2s_gck_param        *gck_param;
 202         const struct atmel_i2s_caps             *caps;
 203 };
 204
 205 static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id)
 206 {
 207         struct atmel_i2s_dev *dev = dev_id;
 208         unsigned int sr, imr, pending, ch, mask;
 209         irqreturn_t ret = IRQ_NONE;
 210
 211         regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
 212         regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr);
 213         pending = sr & imr;
 214
 215         if (!pending)
 216                 return IRQ_NONE;
 217
 218         if (pending & ATMEL_I2SC_INT_RXOR) {
 219                 mask = ATMEL_I2SC_SR_RXOR;
 220
 221                 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
 222                         if (sr & ATMEL_I2SC_SR_RXORCH(ch)) {
 223                                 mask |= ATMEL_I2SC_SR_RXORCH(ch);
 224                                 dev_err(dev->dev,
 225                                         "RX overrun on channel %d\n", ch);
 226                         }
 227                 }
 228                 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
 229                 ret = IRQ_HANDLED;
 230         }
 231
 232         if (pending & ATMEL_I2SC_INT_TXUR) {
 233                 mask = ATMEL_I2SC_SR_TXUR;
 234
 235                 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
 236                         if (sr & ATMEL_I2SC_SR_TXURCH(ch)) {
 237                                 mask |= ATMEL_I2SC_SR_TXURCH(ch);
 238                                 dev_err(dev->dev,
 239                                         "TX underrun on channel %d\n", ch);
 240                         }
 241                 }
 242                 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
 243                 ret = IRQ_HANDLED;
 244         }
 245
 246         return ret;
 247 }
 248
 249 #define ATMEL_I2S_RATES         SNDRV_PCM_RATE_8000_192000
 250
 251 #define ATMEL_I2S_FORMATS       (SNDRV_PCM_FMTBIT_S8 |          \
 252                                  SNDRV_PCM_FMTBIT_S16_LE |      \
 253                                  SNDRV_PCM_FMTBIT_S18_3LE |     \
 254                                  SNDRV_PCM_FMTBIT_S20_3LE |     \
 255                                  SNDRV_PCM_FMTBIT_S24_3LE |     \
 256                                  SNDRV_PCM_FMTBIT_S24_LE |      \
 257                                  SNDRV_PCM_FMTBIT_S32_LE)
 258
 259 static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 260 {
 261         struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 262
 263         dev->fmt = fmt;
 264         return 0;
 265 }
 266
 267 static int atmel_i2s_prepare(struct snd_pcm_substream *substream,
 268                              struct snd_soc_dai *dai)
 269 {
 270         struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 271         bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 272         unsigned int rhr, sr = 0;
 273
 274         if (is_playback) {
 275                 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
 276                 if (sr & ATMEL_I2SC_SR_RXRDY) {
 277                         /*
 278                          * The RX Ready flag should not be set. However if here,
 279                          * we flush (read) the Receive Holding Register to start
 280                          * from a clean state.
 281                          */
 282                         dev_dbg(dev->dev, "RXRDY is set\n");
 283                         regmap_read(dev->regmap, ATMEL_I2SC_RHR, &rhr);
 284                 }
 285         }
 286
 287         return 0;
 288 }
 289
 290 static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs)
 291 {
 292         int i, best;
 293
 294         if (!dev->gclk) {
 295                 dev_err(dev->dev, "cannot generate the I2S Master Clock\n");
 296                 return -EINVAL;
 297         }
 298
 299         /*
 300          * Find the best possible settings to generate the I2S Master Clock
 301          * from the PLL Audio.
 302          */
 303         dev->gck_param = NULL;
 304         best = INT_MAX;
 305         for (i = 0; i < ARRAY_SIZE(gck_params); ++i) {
 306                 const struct atmel_i2s_gck_param *gck_param = &gck_params[i];
 307                 int val = abs(fs - gck_param->fs);
 308
 309                 if (val < best) {
 310                         best = val;
 311                         dev->gck_param = gck_param;
 312                 }
 313         }
 314
 315         return 0;
 316 }
 317
 318 static int atmel_i2s_hw_params(struct snd_pcm_substream *substream,
 319                                struct snd_pcm_hw_params *params,
 320                                struct snd_soc_dai *dai)
 321 {
 322         struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 323         bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 324         unsigned int mr = 0;
 325         int ret;
 326
 327         switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 328         case SND_SOC_DAIFMT_I2S:
 329                 mr |= ATMEL_I2SC_MR_FORMAT_I2S;
 330                 break;
 331
 332         default:
 333                 dev_err(dev->dev, "unsupported bus format\n");
 334                 return -EINVAL;
 335         }
 336
 337         switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 338         case SND_SOC_DAIFMT_CBS_CFS:
 339                 /* codec is slave, so cpu is master */
 340                 mr |= ATMEL_I2SC_MR_MODE_MASTER;
 341                 ret = atmel_i2s_get_gck_param(dev, params_rate(params));
 342                 if (ret)
 343                         return ret;
 344                 break;
 345
 346         case SND_SOC_DAIFMT_CBM_CFM:
 347                 /* codec is master, so cpu is slave */
 348                 mr |= ATMEL_I2SC_MR_MODE_SLAVE;
 349                 dev->gck_param = NULL;
 350                 break;
 351
 352         default:
 353                 dev_err(dev->dev, "unsupported master/slave mode\n");
 354                 return -EINVAL;
 355         }
 356
 357         switch (params_channels(params)) {
 358         case 1:
 359                 if (is_playback)
 360                         mr |= ATMEL_I2SC_MR_TXMONO;
 361                 else
 362                         mr |= ATMEL_I2SC_MR_RXMONO;
 363                 break;
 364         case 2:
 365                 break;
 366         default:
 367                 dev_err(dev->dev, "unsupported number of audio channels\n");
 368                 return -EINVAL;
 369         }
 370
 371         switch (params_format(params)) {
 372         case SNDRV_PCM_FORMAT_S8:
 373                 mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS;
 374                 break;
 375
 376         case SNDRV_PCM_FORMAT_S16_LE:
 377                 mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS;
 378                 break;
 379
 380         case SNDRV_PCM_FORMAT_S18_3LE:
 381                 mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS;
 382                 break;
 383
 384         case SNDRV_PCM_FORMAT_S20_3LE:
 385                 mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS;
 386                 break;
 387
 388         case SNDRV_PCM_FORMAT_S24_3LE:
 389                 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS;
 390                 break;
 391
 392         case SNDRV_PCM_FORMAT_S24_LE:
 393                 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS;
 394                 break;
 395
 396         case SNDRV_PCM_FORMAT_S32_LE:
 397                 mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS;
 398                 break;
 399
 400         default:
 401                 dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
 402                 return -EINVAL;
 403         }
 404
 405         return regmap_write(dev->regmap, ATMEL_I2SC_MR, mr);
 406 }
 407
 408 static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev,
 409                                           bool enabled)
 410 {
 411         unsigned int mr, mr_mask;
 412         unsigned long gclk_rate;
 413         int ret;
 414
 415         mr = 0;
 416         mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK |
 417                    ATMEL_I2SC_MR_IMCKFS_MASK |
 418                    ATMEL_I2SC_MR_IMCKMODE_MASK);
 419
 420         if (!enabled) {
 421                 /* Disable the I2S Master Clock generator. */
 422                 ret = regmap_write(dev->regmap, ATMEL_I2SC_CR,
 423                                    ATMEL_I2SC_CR_CKDIS);
 424                 if (ret)
 425                         return ret;
 426
 427                 /* Reset the I2S Master Clock generator settings. */
 428                 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR,
 429                                          mr_mask, mr);
 430                 if (ret)
 431                         return ret;
 432
 433                 /* Disable/unprepare the PMC generated clock. */
 434                 clk_disable_unprepare(dev->gclk);
 435
 436                 return 0;
 437         }
 438
 439         if (!dev->gck_param)
 440                 return -EINVAL;
 441
 442         gclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1);
 443
 444         ret = clk_set_rate(dev->gclk, gclk_rate);
 445         if (ret)
 446                 return ret;
 447
 448         ret = clk_prepare_enable(dev->gclk);
 449         if (ret)
 450                 return ret;
 451
 452         /* Update the Mode Register to generate the I2S Master Clock. */
 453         mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv);
 454         mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs);
 455         mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK;
 456         ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
 457         if (ret)
 458                 return ret;
 459
 460         /* Finally enable the I2S Master Clock generator. */
 461         return regmap_write(dev->regmap, ATMEL_I2SC_CR,
 462                             ATMEL_I2SC_CR_CKEN);
 463 }
 464
 465 static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 466                              struct snd_soc_dai *dai)
 467 {
 468         struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 469         bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 470         bool is_master, mck_enabled;
 471         unsigned int cr, mr;
 472         int err;
 473
 474         switch (cmd) {
 475         case SNDRV_PCM_TRIGGER_START:
 476         case SNDRV_PCM_TRIGGER_RESUME:
 477         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 478                 cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN;
 479                 mck_enabled = true;
 480                 break;
 481         case SNDRV_PCM_TRIGGER_STOP:
 482         case SNDRV_PCM_TRIGGER_SUSPEND:
 483         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 484                 cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS;
 485                 mck_enabled = false;
 486                 break;
 487         default:
 488                 return -EINVAL;
 489         }
 490
 491         /* Read the Mode Register to retrieve the master/slave state. */
 492         err = regmap_read(dev->regmap, ATMEL_I2SC_MR, &mr);
 493         if (err)
 494                 return err;
 495         is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER;
 496
 497         /* If master starts, enable the audio clock. */
 498         if (is_master && mck_enabled)
 499                 err = atmel_i2s_switch_mck_generator(dev, true);
 500         if (err)
 501                 return err;
 502
 503         err = regmap_write(dev->regmap, ATMEL_I2SC_CR, cr);
 504         if (err)
 505                 return err;
 506
 507         /* If master stops, disable the audio clock. */
 508         if (is_master && !mck_enabled)
 509                 err = atmel_i2s_switch_mck_generator(dev, false);
 510
 511         return err;
 512 }
 513
 514 static const struct snd_soc_dai_ops atmel_i2s_dai_ops = {
 515         .prepare        = atmel_i2s_prepare,
 516         .trigger        = atmel_i2s_trigger,
 517         .hw_params      = atmel_i2s_hw_params,
 518         .set_fmt        = atmel_i2s_set_dai_fmt,
 519 };
 520
 521 static int atmel_i2s_dai_probe(struct snd_soc_dai *dai)
 522 {
 523         struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 524
 525         snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
 526         return 0;
 527 }
 528
 529 static struct snd_soc_dai_driver atmel_i2s_dai = {
 530         .probe  = atmel_i2s_dai_probe,
 531         .playback = {
 532                 .channels_min = 1,
 533                 .channels_max = 2,
 534                 .rates = ATMEL_I2S_RATES,
 535                 .formats = ATMEL_I2S_FORMATS,
 536         },
 537         .capture = {
 538                 .channels_min = 1,
 539                 .channels_max = 2,
 540                 .rates = ATMEL_I2S_RATES,
 541                 .formats = ATMEL_I2S_FORMATS,
 542         },
 543         .ops = &atmel_i2s_dai_ops,
 544         .symmetric_rates = 1,
 545 };
 546
 547 static const struct snd_soc_component_driver atmel_i2s_component = {
 548         .name   = "atmel-i2s",
 549 };
 550
 551 static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev,
 552                                       struct device_node *np)
 553 {
 554         struct clk *muxclk;
 555         int err;
 556
 557         if (!dev->gclk)
 558                 return 0;
 559
 560         /* muxclk is optional, so we return error for probe defer only */
 561         muxclk = devm_clk_get(dev->dev, "muxclk");
 562         if (IS_ERR(muxclk)) {
 563                 err = PTR_ERR(muxclk);
 564                 if (err == -EPROBE_DEFER)
 565                         return -EPROBE_DEFER;
 566                 dev_warn(dev->dev,
 567                          "failed to get the I2S clock control: %d\n", err);
 568                 return 0;
 569         }
 570
 571         return clk_set_parent(muxclk, dev->gclk);
 572 }
 573
 574 static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = {
 575         .mck_init = atmel_i2s_sama5d2_mck_init,
 576 };
 577
 578 static const struct of_device_id atmel_i2s_dt_ids[] = {
 579         {
 580                 .compatible = "atmel,sama5d2-i2s",
 581                 .data = (void *)&atmel_i2s_sama5d2_caps,
 582         },
 583
 584         { /* sentinel */ }
 585 };
 586
 587 MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids);
 588
 589 static int atmel_i2s_probe(struct platform_device *pdev)
 590 {
 591         struct device_node *np = pdev->dev.of_node;
 592         const struct of_device_id *match;
 593         struct atmel_i2s_dev *dev;
 594         struct resource *mem;
 595         struct regmap *regmap;
 596         void __iomem *base;
 597         int irq;
 598         int err = -ENXIO;
 599         unsigned int pcm_flags = 0;
 600         unsigned int version;
 601
 602         /* Get memory for driver data. */
 603         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 604         if (!dev)
 605                 return -ENOMEM;
 606
 607         /* Get hardware capabilities. */
 608         match = of_match_node(atmel_i2s_dt_ids, np);
 609         if (match)
 610                 dev->caps = match->data;
 611
 612         /* Map I/O registers. */
 613         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 614         base = devm_ioremap_resource(&pdev->dev, mem);
 615         if (IS_ERR(base))
 616                 return PTR_ERR(base);
 617
 618         regmap = devm_regmap_init_mmio(&pdev->dev, base,
 619                                        &atmel_i2s_regmap_config);
 620         if (IS_ERR(regmap))
 621                 return PTR_ERR(regmap);
 622
 623         /* Request IRQ. */
 624         irq = platform_get_irq(pdev, 0);
 625         if (irq < 0)
 626                 return irq;
 627
 628         err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,
 629                                dev_name(&pdev->dev), dev);
 630         if (err)
 631                 return err;
 632
 633         /* Get the peripheral clock. */
 634         dev->pclk = devm_clk_get(&pdev->dev, "pclk");
 635         if (IS_ERR(dev->pclk)) {
 636                 err = PTR_ERR(dev->pclk);
 637                 dev_err(&pdev->dev,
 638                         "failed to get the peripheral clock: %d\n", err);
 639                 return err;
 640         }
 641
 642         /* Get audio clock to generate the I2S Master Clock (I2S_MCK) */
 643         dev->gclk = devm_clk_get(&pdev->dev, "gclk");
 644         if (IS_ERR(dev->gclk)) {
 645                 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)
 646                         return -EPROBE_DEFER;
 647                 /* Master Mode not supported */
 648                 dev->gclk = NULL;
 649         }
 650         dev->dev = &pdev->dev;
 651         dev->regmap = regmap;
 652         platform_set_drvdata(pdev, dev);
 653
 654         /* Do hardware specific settings to initialize I2S_MCK generator */
 655         if (dev->caps && dev->caps->mck_init) {
 656                 err = dev->caps->mck_init(dev, np);
 657                 if (err)
 658                         return err;
 659         }
 660
 661         /* Enable the peripheral clock. */
 662         err = clk_prepare_enable(dev->pclk);
 663         if (err)
 664                 return err;
 665
 666         /* Get IP version. */
 667         regmap_read(dev->regmap, ATMEL_I2SC_VERSION, &version);
 668         dev_info(&pdev->dev, "hw version: %#x\n", version);
 669
 670         /* Enable error interrupts. */
 671         regmap_write(dev->regmap, ATMEL_I2SC_IER,
 672                      ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR);
 673
 674         err = devm_snd_soc_register_component(&pdev->dev,
 675                                               &atmel_i2s_component,
 676                                               &atmel_i2s_dai, 1);
 677         if (err) {
 678                 dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
 679                 clk_disable_unprepare(dev->pclk);
 680                 return err;
 681         }
 682
 683         /* Prepare DMA config. */
 684         dev->playback.addr      = (dma_addr_t)mem->start + ATMEL_I2SC_THR;
 685         dev->playback.maxburst  = 1;
 686         dev->capture.addr       = (dma_addr_t)mem->start + ATMEL_I2SC_RHR;
 687         dev->capture.maxburst   = 1;
 688
 689         if (of_property_match_string(np, "dma-names", "rx-tx") == 0)
 690                 pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX;
 691         err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, pcm_flags);
 692         if (err) {
 693                 dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
 694                 clk_disable_unprepare(dev->pclk);
 695                 return err;
 696         }
 697
 698         return 0;
 699 }
 700
 701 static int atmel_i2s_remove(struct platform_device *pdev)
 702 {
 703         struct atmel_i2s_dev *dev = platform_get_drvdata(pdev);
 704
 705         clk_disable_unprepare(dev->pclk);
 706
 707         return 0;
 708 }
 709
 710 static struct platform_driver atmel_i2s_driver = {
 711         .driver         = {
 712                 .name   = "atmel_i2s",
 713                 .of_match_table = of_match_ptr(atmel_i2s_dt_ids),
 714         },
 715         .probe          = atmel_i2s_probe,
 716         .remove         = atmel_i2s_remove,
 717 };
 718 module_platform_driver(atmel_i2s_driver);
 719
 720 MODULE_DESCRIPTION("Atmel I2S Controller driver");
 721 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
 722 MODULE_LICENSE("GPL v2");