sound/soc/cirrus/ep93xx-ac97.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ASoC driver for Cirrus Logic EP93xx AC97 controller.
   4  *
   5  * Copyright (c) 2010 Mika Westerberg
   6  *
   7  * Based on s3c-ac97 ASoC driver by Jaswinder Singh.
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/slab.h>
  17
  18 #include <sound/core.h>
  19 #include <sound/dmaengine_pcm.h>
  20 #include <sound/ac97_codec.h>
  21 #include <sound/soc.h>
  22
  23 #include <linux/platform_data/dma-ep93xx.h>
  24 #include <linux/soc/cirrus/ep93xx.h>
  25
  26 #include "ep93xx-pcm.h"
  27
  28 /*
  29  * Per channel (1-4) registers.
  30  */
  31 #define AC97CH(n)               (((n) - 1) * 0x20)
  32
  33 #define AC97DR(n)               (AC97CH(n) + 0x0000)
  34
  35 #define AC97RXCR(n)             (AC97CH(n) + 0x0004)
  36 #define AC97RXCR_REN            BIT(0)
  37 #define AC97RXCR_RX3            BIT(3)
  38 #define AC97RXCR_RX4            BIT(4)
  39 #define AC97RXCR_CM             BIT(15)
  40
  41 #define AC97TXCR(n)             (AC97CH(n) + 0x0008)
  42 #define AC97TXCR_TEN            BIT(0)
  43 #define AC97TXCR_TX3            BIT(3)
  44 #define AC97TXCR_TX4            BIT(4)
  45 #define AC97TXCR_CM             BIT(15)
  46
  47 #define AC97SR(n)               (AC97CH(n) + 0x000c)
  48 #define AC97SR_TXFE             BIT(1)
  49 #define AC97SR_TXUE             BIT(6)
  50
  51 #define AC97RISR(n)             (AC97CH(n) + 0x0010)
  52 #define AC97ISR(n)              (AC97CH(n) + 0x0014)
  53 #define AC97IE(n)               (AC97CH(n) + 0x0018)
  54
  55 /*
  56  * Global AC97 controller registers.
  57  */
  58 #define AC97S1DATA              0x0080
  59 #define AC97S2DATA              0x0084
  60 #define AC97S12DATA             0x0088
  61
  62 #define AC97RGIS                0x008c
  63 #define AC97GIS                 0x0090
  64 #define AC97IM                  0x0094
  65 /*
  66  * Common bits for RGIS, GIS and IM registers.
  67  */
  68 #define AC97_SLOT2RXVALID       BIT(1)
  69 #define AC97_CODECREADY         BIT(5)
  70 #define AC97_SLOT2TXCOMPLETE    BIT(6)
  71
  72 #define AC97EOI                 0x0098
  73 #define AC97EOI_WINT            BIT(0)
  74 #define AC97EOI_CODECREADY      BIT(1)
  75
  76 #define AC97GCR                 0x009c
  77 #define AC97GCR_AC97IFE         BIT(0)
  78
  79 #define AC97RESET               0x00a0
  80 #define AC97RESET_TIMEDRESET    BIT(0)
  81
  82 #define AC97SYNC                0x00a4
  83 #define AC97SYNC_TIMEDSYNC      BIT(0)
  84
  85 #define AC97_TIMEOUT            msecs_to_jiffies(5)
  86
  87 /**
  88  * struct ep93xx_ac97_info - EP93xx AC97 controller info structure
  89  * @lock: mutex serializing access to the bus (slot 1 & 2 ops)
  90  * @dev: pointer to the platform device dev structure
  91  * @regs: mapped AC97 controller registers
  92  * @done: bus ops wait here for an interrupt
  93  */
  94 struct ep93xx_ac97_info {
  95         struct mutex            lock;
  96         struct device           *dev;
  97         void __iomem            *regs;
  98         struct completion       done;
  99         struct snd_dmaengine_dai_dma_data dma_params_rx;
 100         struct snd_dmaengine_dai_dma_data dma_params_tx;
 101 };
 102
 103 /* currently ALSA only supports a single AC97 device */
 104 static struct ep93xx_ac97_info *ep93xx_ac97_info;
 105
 106 static struct ep93xx_dma_data ep93xx_ac97_pcm_out = {
 107         .name           = "ac97-pcm-out",
 108         .port           = EP93XX_DMA_AAC1,
 109         .direction      = DMA_MEM_TO_DEV,
 110 };
 111
 112 static struct ep93xx_dma_data ep93xx_ac97_pcm_in = {
 113         .name           = "ac97-pcm-in",
 114         .port           = EP93XX_DMA_AAC1,
 115         .direction      = DMA_DEV_TO_MEM,
 116 };
 117
 118 static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
 119                                             unsigned reg)
 120 {
 121         return __raw_readl(info->regs + reg);
 122 }
 123
 124 static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
 125                                          unsigned reg, unsigned val)
 126 {
 127         __raw_writel(val, info->regs + reg);
 128 }
 129
 130 static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
 131                                        unsigned short reg)
 132 {
 133         struct ep93xx_ac97_info *info = ep93xx_ac97_info;
 134         unsigned short val;
 135
 136         mutex_lock(&info->lock);
 137
 138         ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
 139         ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
 140         if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
 141                 dev_warn(info->dev, "timeout reading register %x\n", reg);
 142                 mutex_unlock(&info->lock);
 143                 return -ETIMEDOUT;
 144         }
 145         val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
 146
 147         mutex_unlock(&info->lock);
 148         return val;
 149 }
 150
 151 static void ep93xx_ac97_write(struct snd_ac97 *ac97,
 152                               unsigned short reg,
 153                               unsigned short val)
 154 {
 155         struct ep93xx_ac97_info *info = ep93xx_ac97_info;
 156
 157         mutex_lock(&info->lock);
 158
 159         /*
 160          * Writes to the codec need to be done so that slot 2 is filled in
 161          * before slot 1.
 162          */
 163         ep93xx_ac97_write_reg(info, AC97S2DATA, val);
 164         ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
 165
 166         ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
 167         if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
 168                 dev_warn(info->dev, "timeout writing register %x\n", reg);
 169
 170         mutex_unlock(&info->lock);
 171 }
 172
 173 static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
 174 {
 175         struct ep93xx_ac97_info *info = ep93xx_ac97_info;
 176
 177         mutex_lock(&info->lock);
 178
 179         /*
 180          * We are assuming that before this functions gets called, the codec
 181          * BIT_CLK is stopped by forcing the codec into powerdown mode. We can
 182          * control the SYNC signal directly via AC97SYNC register. Using
 183          * TIMEDSYNC the controller will keep the SYNC high > 1us.
 184          */
 185         ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
 186         ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
 187         if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
 188                 dev_warn(info->dev, "codec warm reset timeout\n");
 189
 190         mutex_unlock(&info->lock);
 191 }
 192
 193 static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
 194 {
 195         struct ep93xx_ac97_info *info = ep93xx_ac97_info;
 196
 197         mutex_lock(&info->lock);
 198
 199         /*
 200          * For doing cold reset, we disable the AC97 controller interface, clear
 201          * WINT and CODECREADY bits, and finally enable the interface again.
 202          */
 203         ep93xx_ac97_write_reg(info, AC97GCR, 0);
 204         ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
 205         ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
 206
 207         /*
 208          * Now, assert the reset and wait for the codec to become ready.
 209          */
 210         ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
 211         ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
 212         if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
 213                 dev_warn(info->dev, "codec cold reset timeout\n");
 214
 215         /*
 216          * Give the codec some time to come fully out from the reset. This way
 217          * we ensure that the subsequent reads/writes will work.
 218          */
 219         usleep_range(15000, 20000);
 220
 221         mutex_unlock(&info->lock);
 222 }
 223
 224 static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
 225 {
 226         struct ep93xx_ac97_info *info = dev_id;
 227         unsigned status, mask;
 228
 229         /*
 230          * Just mask out the interrupt and wake up the waiting thread.
 231          * Interrupts are cleared via reading/writing to slot 1 & 2 registers by
 232          * the waiting thread.
 233          */
 234         status = ep93xx_ac97_read_reg(info, AC97GIS);
 235         mask = ep93xx_ac97_read_reg(info, AC97IM);
 236         mask &= ~status;
 237         ep93xx_ac97_write_reg(info, AC97IM, mask);
 238
 239         complete(&info->done);
 240         return IRQ_HANDLED;
 241 }
 242
 243 static struct snd_ac97_bus_ops ep93xx_ac97_ops = {
 244         .read           = ep93xx_ac97_read,
 245         .write          = ep93xx_ac97_write,
 246         .reset          = ep93xx_ac97_cold_reset,
 247         .warm_reset     = ep93xx_ac97_warm_reset,
 248 };
 249
 250 static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
 251                                int cmd, struct snd_soc_dai *dai)
 252 {
 253         struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
 254         unsigned v = 0;
 255
 256         switch (cmd) {
 257         case SNDRV_PCM_TRIGGER_START:
 258         case SNDRV_PCM_TRIGGER_RESUME:
 259         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 260                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 261                         /*
 262                          * Enable compact mode, TX slots 3 & 4, and the TX FIFO
 263                          * itself.
 264                          */
 265                         v |= AC97TXCR_CM;
 266                         v |= AC97TXCR_TX3 | AC97TXCR_TX4;
 267                         v |= AC97TXCR_TEN;
 268                         ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
 269                 } else {
 270                         /*
 271                          * Enable compact mode, RX slots 3 & 4, and the RX FIFO
 272                          * itself.
 273                          */
 274                         v |= AC97RXCR_CM;
 275                         v |= AC97RXCR_RX3 | AC97RXCR_RX4;
 276                         v |= AC97RXCR_REN;
 277                         ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
 278                 }
 279                 break;
 280
 281         case SNDRV_PCM_TRIGGER_STOP:
 282         case SNDRV_PCM_TRIGGER_SUSPEND:
 283         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 284                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 285                         /*
 286                          * As per Cirrus EP93xx errata described below:
 287                          *
 288                          * http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
 289                          *
 290                          * we will wait for the TX FIFO to be empty before
 291                          * clearing the TEN bit.
 292                          */
 293                         unsigned long timeout = jiffies + AC97_TIMEOUT;
 294
 295                         do {
 296                                 v = ep93xx_ac97_read_reg(info, AC97SR(1));
 297                                 if (time_after(jiffies, timeout)) {
 298                                         dev_warn(info->dev, "TX timeout\n");
 299                                         break;
 300                                 }
 301                         } while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));
 302
 303                         /* disable the TX FIFO */
 304                         ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
 305                 } else {
 306                         /* disable the RX FIFO */
 307                         ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
 308                 }
 309                 break;
 310
 311         default:
 312                 dev_warn(info->dev, "unknown command %d\n", cmd);
 313                 return -EINVAL;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int ep93xx_ac97_dai_probe(struct snd_soc_dai *dai)
 320 {
 321         struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
 322
 323         info->dma_params_tx.filter_data = &ep93xx_ac97_pcm_out;
 324         info->dma_params_rx.filter_data = &ep93xx_ac97_pcm_in;
 325
 326         dai->playback_dma_data = &info->dma_params_tx;
 327         dai->capture_dma_data = &info->dma_params_rx;
 328
 329         return 0;
 330 }
 331
 332 static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
 333         .trigger        = ep93xx_ac97_trigger,
 334 };
 335
 336 static struct snd_soc_dai_driver ep93xx_ac97_dai = {
 337         .name           = "ep93xx-ac97",
 338         .id             = 0,
 339         .probe          = ep93xx_ac97_dai_probe,
 340         .playback       = {
 341                 .stream_name    = "AC97 Playback",
 342                 .channels_min   = 2,
 343                 .channels_max   = 2,
 344                 .rates          = SNDRV_PCM_RATE_8000_48000,
 345                 .formats        = SNDRV_PCM_FMTBIT_S16_LE,
 346         },
 347         .capture        = {
 348                 .stream_name    = "AC97 Capture",
 349                 .channels_min   = 2,
 350                 .channels_max   = 2,
 351                 .rates          = SNDRV_PCM_RATE_8000_48000,
 352                 .formats        = SNDRV_PCM_FMTBIT_S16_LE,
 353         },
 354         .ops                    = &ep93xx_ac97_dai_ops,
 355 };
 356
 357 static const struct snd_soc_component_driver ep93xx_ac97_component = {
 358         .name           = "ep93xx-ac97",
 359 };
 360
 361 static int ep93xx_ac97_probe(struct platform_device *pdev)
 362 {
 363         struct ep93xx_ac97_info *info;
 364         int irq;
 365         int ret;
 366
 367         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
 368         if (!info)
 369                 return -ENOMEM;
 370
 371         info->regs = devm_platform_ioremap_resource(pdev, 0);
 372         if (IS_ERR(info->regs))
 373                 return PTR_ERR(info->regs);
 374
 375         irq = platform_get_irq(pdev, 0);
 376         if (irq <= 0)
 377                 return irq < 0 ? irq : -ENODEV;
 378
 379         ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
 380                                IRQF_TRIGGER_HIGH, pdev->name, info);
 381         if (ret)
 382                 goto fail;
 383
 384         dev_set_drvdata(&pdev->dev, info);
 385
 386         mutex_init(&info->lock);
 387         init_completion(&info->done);
 388         info->dev = &pdev->dev;
 389
 390         ep93xx_ac97_info = info;
 391         platform_set_drvdata(pdev, info);
 392
 393         ret = snd_soc_set_ac97_ops(&ep93xx_ac97_ops);
 394         if (ret)
 395                 goto fail;
 396
 397         ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component,
 398                                          &ep93xx_ac97_dai, 1);
 399         if (ret)
 400                 goto fail;
 401
 402         ret = devm_ep93xx_pcm_platform_register(&pdev->dev);
 403         if (ret)
 404                 goto fail_unregister;
 405
 406         return 0;
 407
 408 fail_unregister:
 409         snd_soc_unregister_component(&pdev->dev);
 410 fail:
 411         ep93xx_ac97_info = NULL;
 412         snd_soc_set_ac97_ops(NULL);
 413         return ret;
 414 }
 415
 416 static int ep93xx_ac97_remove(struct platform_device *pdev)
 417 {
 418         struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
 419
 420         snd_soc_unregister_component(&pdev->dev);
 421
 422         /* disable the AC97 controller */
 423         ep93xx_ac97_write_reg(info, AC97GCR, 0);
 424
 425         ep93xx_ac97_info = NULL;
 426
 427         snd_soc_set_ac97_ops(NULL);
 428
 429         return 0;
 430 }
 431
 432 static struct platform_driver ep93xx_ac97_driver = {
 433         .probe  = ep93xx_ac97_probe,
 434         .remove = ep93xx_ac97_remove,
 435         .driver = {
 436                 .name = "ep93xx-ac97",
 437         },
 438 };
 439
 440 module_platform_driver(ep93xx_ac97_driver);
 441
 442 MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
 443 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
 444 MODULE_LICENSE("GPL");
 445 MODULE_ALIAS("platform:ep93xx-ac97");