sound/soc/codecs/cs4271.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * CS4271 ASoC codec driver
   4  *
   5  * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
   6  *
   7  * This driver support CS4271 codec being master or slave, working
   8  * in control port mode, connected either via SPI or I2C.
   9  * The data format accepted is I2S or left-justified.
  10  * DAPM support not implemented.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/slab.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <sound/pcm.h>
  22 #include <sound/soc.h>
  23 #include <sound/tlv.h>
  24 #include <sound/cs4271.h>
  25 #include "cs4271.h"
  26
  27 #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  28                             SNDRV_PCM_FMTBIT_S24_LE | \
  29                             SNDRV_PCM_FMTBIT_S32_LE)
  30 #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
  31
  32 /*
  33  * CS4271 registers
  34  */
  35 #define CS4271_MODE1    0x01    /* Mode Control 1 */
  36 #define CS4271_DACCTL   0x02    /* DAC Control */
  37 #define CS4271_DACVOL   0x03    /* DAC Volume & Mixing Control */
  38 #define CS4271_VOLA     0x04    /* DAC Channel A Volume Control */
  39 #define CS4271_VOLB     0x05    /* DAC Channel B Volume Control */
  40 #define CS4271_ADCCTL   0x06    /* ADC Control */
  41 #define CS4271_MODE2    0x07    /* Mode Control 2 */
  42 #define CS4271_CHIPID   0x08    /* Chip ID */
  43
  44 #define CS4271_FIRSTREG CS4271_MODE1
  45 #define CS4271_LASTREG  CS4271_MODE2
  46 #define CS4271_NR_REGS  ((CS4271_LASTREG & 0xFF) + 1)
  47
  48 /* Bit masks for the CS4271 registers */
  49 #define CS4271_MODE1_MODE_MASK  0xC0
  50 #define CS4271_MODE1_MODE_1X    0x00
  51 #define CS4271_MODE1_MODE_2X    0x80
  52 #define CS4271_MODE1_MODE_4X    0xC0
  53
  54 #define CS4271_MODE1_DIV_MASK   0x30
  55 #define CS4271_MODE1_DIV_1      0x00
  56 #define CS4271_MODE1_DIV_15     0x10
  57 #define CS4271_MODE1_DIV_2      0x20
  58 #define CS4271_MODE1_DIV_3      0x30
  59
  60 #define CS4271_MODE1_MASTER     0x08
  61
  62 #define CS4271_MODE1_DAC_DIF_MASK       0x07
  63 #define CS4271_MODE1_DAC_DIF_LJ         0x00
  64 #define CS4271_MODE1_DAC_DIF_I2S        0x01
  65 #define CS4271_MODE1_DAC_DIF_RJ16       0x02
  66 #define CS4271_MODE1_DAC_DIF_RJ24       0x03
  67 #define CS4271_MODE1_DAC_DIF_RJ20       0x04
  68 #define CS4271_MODE1_DAC_DIF_RJ18       0x05
  69
  70 #define CS4271_DACCTL_AMUTE     0x80
  71 #define CS4271_DACCTL_IF_SLOW   0x40
  72
  73 #define CS4271_DACCTL_DEM_MASK  0x30
  74 #define CS4271_DACCTL_DEM_DIS   0x00
  75 #define CS4271_DACCTL_DEM_441   0x10
  76 #define CS4271_DACCTL_DEM_48    0x20
  77 #define CS4271_DACCTL_DEM_32    0x30
  78
  79 #define CS4271_DACCTL_SVRU      0x08
  80 #define CS4271_DACCTL_SRD       0x04
  81 #define CS4271_DACCTL_INVA      0x02
  82 #define CS4271_DACCTL_INVB      0x01
  83
  84 #define CS4271_DACVOL_BEQUA     0x40
  85 #define CS4271_DACVOL_SOFT      0x20
  86 #define CS4271_DACVOL_ZEROC     0x10
  87
  88 #define CS4271_DACVOL_ATAPI_MASK        0x0F
  89 #define CS4271_DACVOL_ATAPI_M_M         0x00
  90 #define CS4271_DACVOL_ATAPI_M_BR        0x01
  91 #define CS4271_DACVOL_ATAPI_M_BL        0x02
  92 #define CS4271_DACVOL_ATAPI_M_BLR2      0x03
  93 #define CS4271_DACVOL_ATAPI_AR_M        0x04
  94 #define CS4271_DACVOL_ATAPI_AR_BR       0x05
  95 #define CS4271_DACVOL_ATAPI_AR_BL       0x06
  96 #define CS4271_DACVOL_ATAPI_AR_BLR2     0x07
  97 #define CS4271_DACVOL_ATAPI_AL_M        0x08
  98 #define CS4271_DACVOL_ATAPI_AL_BR       0x09
  99 #define CS4271_DACVOL_ATAPI_AL_BL       0x0A
 100 #define CS4271_DACVOL_ATAPI_AL_BLR2     0x0B
 101 #define CS4271_DACVOL_ATAPI_ALR2_M      0x0C
 102 #define CS4271_DACVOL_ATAPI_ALR2_BR     0x0D
 103 #define CS4271_DACVOL_ATAPI_ALR2_BL     0x0E
 104 #define CS4271_DACVOL_ATAPI_ALR2_BLR2   0x0F
 105
 106 #define CS4271_VOLA_MUTE        0x80
 107 #define CS4271_VOLA_VOL_MASK    0x7F
 108 #define CS4271_VOLB_MUTE        0x80
 109 #define CS4271_VOLB_VOL_MASK    0x7F
 110
 111 #define CS4271_ADCCTL_DITHER16  0x20
 112
 113 #define CS4271_ADCCTL_ADC_DIF_MASK      0x10
 114 #define CS4271_ADCCTL_ADC_DIF_LJ        0x00
 115 #define CS4271_ADCCTL_ADC_DIF_I2S       0x10
 116
 117 #define CS4271_ADCCTL_MUTEA     0x08
 118 #define CS4271_ADCCTL_MUTEB     0x04
 119 #define CS4271_ADCCTL_HPFDA     0x02
 120 #define CS4271_ADCCTL_HPFDB     0x01
 121
 122 #define CS4271_MODE2_LOOP       0x10
 123 #define CS4271_MODE2_MUTECAEQUB 0x08
 124 #define CS4271_MODE2_FREEZE     0x04
 125 #define CS4271_MODE2_CPEN       0x02
 126 #define CS4271_MODE2_PDN        0x01
 127
 128 #define CS4271_CHIPID_PART_MASK 0xF0
 129 #define CS4271_CHIPID_REV_MASK  0x0F
 130
 131 /*
 132  * Default CS4271 power-up configuration
 133  * Array contains non-existing in hw register at address 0
 134  * Array do not include Chip ID, as codec driver does not use
 135  * registers read operations at all
 136  */
 137 static const struct reg_default cs4271_reg_defaults[] = {
 138         { CS4271_MODE1,         0, },
 139         { CS4271_DACCTL,        CS4271_DACCTL_AMUTE, },
 140         { CS4271_DACVOL,        CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, },
 141         { CS4271_VOLA,          0, },
 142         { CS4271_VOLB,          0, },
 143         { CS4271_ADCCTL,        0, },
 144         { CS4271_MODE2,         0, },
 145 };
 146
 147 static bool cs4271_volatile_reg(struct device *dev, unsigned int reg)
 148 {
 149         return reg == CS4271_CHIPID;
 150 }
 151
 152 static const char * const supply_names[] = {
 153         "vd", "vl", "va"
 154 };
 155
 156 struct cs4271_private {
 157         unsigned int                    mclk;
 158         bool                            master;
 159         bool                            deemph;
 160         struct regmap                   *regmap;
 161         /* Current sample rate for de-emphasis control */
 162         int                             rate;
 163         /* GPIO driving Reset pin, if any */
 164         int                             gpio_nreset;
 165         /* GPIO that disable serial bus, if any */
 166         int                             gpio_disable;
 167         /* enable soft reset workaround */
 168         bool                            enable_soft_reset;
 169         struct regulator_bulk_data      supplies[ARRAY_SIZE(supply_names)];
 170 };
 171
 172 static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = {
 173 SND_SOC_DAPM_INPUT("AINA"),
 174 SND_SOC_DAPM_INPUT("AINB"),
 175
 176 SND_SOC_DAPM_OUTPUT("AOUTA+"),
 177 SND_SOC_DAPM_OUTPUT("AOUTA-"),
 178 SND_SOC_DAPM_OUTPUT("AOUTB+"),
 179 SND_SOC_DAPM_OUTPUT("AOUTB-"),
 180 };
 181
 182 static const struct snd_soc_dapm_route cs4271_dapm_routes[] = {
 183         { "Capture", NULL, "AINA" },
 184         { "Capture", NULL, "AINB" },
 185
 186         { "AOUTA+", NULL, "Playback" },
 187         { "AOUTA-", NULL, "Playback" },
 188         { "AOUTB+", NULL, "Playback" },
 189         { "AOUTB-", NULL, "Playback" },
 190 };
 191
 192 /*
 193  * @freq is the desired MCLK rate
 194  * MCLK rate should (c) be the sample rate, multiplied by one of the
 195  * ratios listed in cs4271_mclk_fs_ratios table
 196  */
 197 static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 198                                  int clk_id, unsigned int freq, int dir)
 199 {
 200         struct snd_soc_component *component = codec_dai->component;
 201         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 202
 203         cs4271->mclk = freq;
 204         return 0;
 205 }
 206
 207 static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
 208                               unsigned int format)
 209 {
 210         struct snd_soc_component *component = codec_dai->component;
 211         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 212         unsigned int val = 0;
 213         int ret;
 214
 215         switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
 216         case SND_SOC_DAIFMT_CBS_CFS:
 217                 cs4271->master = false;
 218                 break;
 219         case SND_SOC_DAIFMT_CBM_CFM:
 220                 cs4271->master = true;
 221                 val |= CS4271_MODE1_MASTER;
 222                 break;
 223         default:
 224                 dev_err(component->dev, "Invalid DAI format\n");
 225                 return -EINVAL;
 226         }
 227
 228         switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
 229         case SND_SOC_DAIFMT_LEFT_J:
 230                 val |= CS4271_MODE1_DAC_DIF_LJ;
 231                 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
 232                         CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
 233                 if (ret < 0)
 234                         return ret;
 235                 break;
 236         case SND_SOC_DAIFMT_I2S:
 237                 val |= CS4271_MODE1_DAC_DIF_I2S;
 238                 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
 239                         CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
 240                 if (ret < 0)
 241                         return ret;
 242                 break;
 243         default:
 244                 dev_err(component->dev, "Invalid DAI format\n");
 245                 return -EINVAL;
 246         }
 247
 248         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
 249                 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
 250         if (ret < 0)
 251                 return ret;
 252         return 0;
 253 }
 254
 255 static int cs4271_deemph[] = {0, 44100, 48000, 32000};
 256
 257 static int cs4271_set_deemph(struct snd_soc_component *component)
 258 {
 259         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 260         int i, ret;
 261         int val = CS4271_DACCTL_DEM_DIS;
 262
 263         if (cs4271->deemph) {
 264                 /* Find closest de-emphasis freq */
 265                 val = 1;
 266                 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
 267                         if (abs(cs4271_deemph[i] - cs4271->rate) <
 268                             abs(cs4271_deemph[val] - cs4271->rate))
 269                                 val = i;
 270                 val <<= 4;
 271         }
 272
 273         ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL,
 274                 CS4271_DACCTL_DEM_MASK, val);
 275         if (ret < 0)
 276                 return ret;
 277         return 0;
 278 }
 279
 280 static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
 281                              struct snd_ctl_elem_value *ucontrol)
 282 {
 283         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 284         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 285
 286         ucontrol->value.integer.value[0] = cs4271->deemph;
 287         return 0;
 288 }
 289
 290 static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
 291                              struct snd_ctl_elem_value *ucontrol)
 292 {
 293         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 294         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 295
 296         cs4271->deemph = ucontrol->value.integer.value[0];
 297         return cs4271_set_deemph(component);
 298 }
 299
 300 struct cs4271_clk_cfg {
 301         bool            master;         /* codec mode */
 302         u8              speed_mode;     /* codec speed mode: 1x, 2x, 4x */
 303         unsigned short  ratio;          /* MCLK / sample rate */
 304         u8              ratio_mask;     /* ratio bit mask for Master mode */
 305 };
 306
 307 static struct cs4271_clk_cfg cs4271_clk_tab[] = {
 308         {1, CS4271_MODE1_MODE_1X, 256,  CS4271_MODE1_DIV_1},
 309         {1, CS4271_MODE1_MODE_1X, 384,  CS4271_MODE1_DIV_15},
 310         {1, CS4271_MODE1_MODE_1X, 512,  CS4271_MODE1_DIV_2},
 311         {1, CS4271_MODE1_MODE_1X, 768,  CS4271_MODE1_DIV_3},
 312         {1, CS4271_MODE1_MODE_2X, 128,  CS4271_MODE1_DIV_1},
 313         {1, CS4271_MODE1_MODE_2X, 192,  CS4271_MODE1_DIV_15},
 314         {1, CS4271_MODE1_MODE_2X, 256,  CS4271_MODE1_DIV_2},
 315         {1, CS4271_MODE1_MODE_2X, 384,  CS4271_MODE1_DIV_3},
 316         {1, CS4271_MODE1_MODE_4X, 64,   CS4271_MODE1_DIV_1},
 317         {1, CS4271_MODE1_MODE_4X, 96,   CS4271_MODE1_DIV_15},
 318         {1, CS4271_MODE1_MODE_4X, 128,  CS4271_MODE1_DIV_2},
 319         {1, CS4271_MODE1_MODE_4X, 192,  CS4271_MODE1_DIV_3},
 320         {0, CS4271_MODE1_MODE_1X, 256,  CS4271_MODE1_DIV_1},
 321         {0, CS4271_MODE1_MODE_1X, 384,  CS4271_MODE1_DIV_1},
 322         {0, CS4271_MODE1_MODE_1X, 512,  CS4271_MODE1_DIV_1},
 323         {0, CS4271_MODE1_MODE_1X, 768,  CS4271_MODE1_DIV_2},
 324         {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2},
 325         {0, CS4271_MODE1_MODE_2X, 128,  CS4271_MODE1_DIV_1},
 326         {0, CS4271_MODE1_MODE_2X, 192,  CS4271_MODE1_DIV_1},
 327         {0, CS4271_MODE1_MODE_2X, 256,  CS4271_MODE1_DIV_1},
 328         {0, CS4271_MODE1_MODE_2X, 384,  CS4271_MODE1_DIV_2},
 329         {0, CS4271_MODE1_MODE_2X, 512,  CS4271_MODE1_DIV_2},
 330         {0, CS4271_MODE1_MODE_4X, 64,   CS4271_MODE1_DIV_1},
 331         {0, CS4271_MODE1_MODE_4X, 96,   CS4271_MODE1_DIV_1},
 332         {0, CS4271_MODE1_MODE_4X, 128,  CS4271_MODE1_DIV_1},
 333         {0, CS4271_MODE1_MODE_4X, 192,  CS4271_MODE1_DIV_2},
 334         {0, CS4271_MODE1_MODE_4X, 256,  CS4271_MODE1_DIV_2},
 335 };
 336
 337 #define CS4271_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
 338
 339 static int cs4271_hw_params(struct snd_pcm_substream *substream,
 340                             struct snd_pcm_hw_params *params,
 341                             struct snd_soc_dai *dai)
 342 {
 343         struct snd_soc_component *component = dai->component;
 344         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 345         int i, ret;
 346         unsigned int ratio, val;
 347
 348         if (cs4271->enable_soft_reset) {
 349                 /*
 350                  * Put the codec in soft reset and back again in case it's not
 351                  * currently streaming data. This way of bringing the codec in
 352                  * sync to the current clocks is not explicitly documented in
 353                  * the data sheet, but it seems to work fine, and in contrast
 354                  * to a read hardware reset, we don't have to sync back all
 355                  * registers every time.
 356                  */
 357
 358                 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
 359                      !dai->capture_active) ||
 360                     (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
 361                      !dai->playback_active)) {
 362                         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
 363                                                  CS4271_MODE2_PDN,
 364                                                  CS4271_MODE2_PDN);
 365                         if (ret < 0)
 366                                 return ret;
 367
 368                         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
 369                                                  CS4271_MODE2_PDN, 0);
 370                         if (ret < 0)
 371                                 return ret;
 372                 }
 373         }
 374
 375         cs4271->rate = params_rate(params);
 376
 377         /* Configure DAC */
 378         if (cs4271->rate < 50000)
 379                 val = CS4271_MODE1_MODE_1X;
 380         else if (cs4271->rate < 100000)
 381                 val = CS4271_MODE1_MODE_2X;
 382         else
 383                 val = CS4271_MODE1_MODE_4X;
 384
 385         ratio = cs4271->mclk / cs4271->rate;
 386         for (i = 0; i < CS4271_NR_RATIOS; i++)
 387                 if ((cs4271_clk_tab[i].master == cs4271->master) &&
 388                     (cs4271_clk_tab[i].speed_mode == val) &&
 389                     (cs4271_clk_tab[i].ratio == ratio))
 390                         break;
 391
 392         if (i == CS4271_NR_RATIOS) {
 393                 dev_err(component->dev, "Invalid sample rate\n");
 394                 return -EINVAL;
 395         }
 396
 397         val |= cs4271_clk_tab[i].ratio_mask;
 398
 399         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
 400                 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
 401         if (ret < 0)
 402                 return ret;
 403
 404         return cs4271_set_deemph(component);
 405 }
 406
 407 static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 408 {
 409         struct snd_soc_component *component = dai->component;
 410         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 411         int ret;
 412         int val_a = 0;
 413         int val_b = 0;
 414
 415         if (stream != SNDRV_PCM_STREAM_PLAYBACK)
 416                 return 0;
 417
 418         if (mute) {
 419                 val_a = CS4271_VOLA_MUTE;
 420                 val_b = CS4271_VOLB_MUTE;
 421         }
 422
 423         ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA,
 424                                  CS4271_VOLA_MUTE, val_a);
 425         if (ret < 0)
 426                 return ret;
 427
 428         ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB,
 429                                  CS4271_VOLB_MUTE, val_b);
 430         if (ret < 0)
 431                 return ret;
 432
 433         return 0;
 434 }
 435
 436 /* CS4271 controls */
 437 static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
 438
 439 static const struct snd_kcontrol_new cs4271_snd_controls[] = {
 440         SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
 441                 0, 0x7F, 1, cs4271_dac_tlv),
 442         SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
 443         SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
 444         SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
 445         SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
 446                 cs4271_get_deemph, cs4271_put_deemph),
 447         SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
 448         SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
 449         SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
 450         SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
 451         SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
 452         SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
 453         SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
 454         SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
 455         SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
 456         SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
 457                 7, 1, 1),
 458 };
 459
 460 static const struct snd_soc_dai_ops cs4271_dai_ops = {
 461         .hw_params      = cs4271_hw_params,
 462         .set_sysclk     = cs4271_set_dai_sysclk,
 463         .set_fmt        = cs4271_set_dai_fmt,
 464         .mute_stream    = cs4271_mute_stream,
 465 };
 466
 467 static struct snd_soc_dai_driver cs4271_dai = {
 468         .name = "cs4271-hifi",
 469         .playback = {
 470                 .stream_name    = "Playback",
 471                 .channels_min   = 2,
 472                 .channels_max   = 2,
 473                 .rates          = CS4271_PCM_RATES,
 474                 .formats        = CS4271_PCM_FORMATS,
 475         },
 476         .capture = {
 477                 .stream_name    = "Capture",
 478                 .channels_min   = 2,
 479                 .channels_max   = 2,
 480                 .rates          = CS4271_PCM_RATES,
 481                 .formats        = CS4271_PCM_FORMATS,
 482         },
 483         .ops = &cs4271_dai_ops,
 484         .symmetric_rates = 1,
 485 };
 486
 487 static int cs4271_reset(struct snd_soc_component *component)
 488 {
 489         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 490
 491         if (gpio_is_valid(cs4271->gpio_nreset)) {
 492                 gpio_direction_output(cs4271->gpio_nreset, 0);
 493                 mdelay(1);
 494                 gpio_set_value(cs4271->gpio_nreset, 1);
 495                 mdelay(1);
 496         }
 497
 498         return 0;
 499 }
 500
 501 #ifdef CONFIG_PM
 502 static int cs4271_soc_suspend(struct snd_soc_component *component)
 503 {
 504         int ret;
 505         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 506
 507         /* Set power-down bit */
 508         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
 509                                  CS4271_MODE2_PDN, CS4271_MODE2_PDN);
 510         if (ret < 0)
 511                 return ret;
 512
 513         regcache_mark_dirty(cs4271->regmap);
 514         regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies);
 515
 516         return 0;
 517 }
 518
 519 static int cs4271_soc_resume(struct snd_soc_component *component)
 520 {
 521         int ret;
 522         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 523
 524         ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies),
 525                                     cs4271->supplies);
 526         if (ret < 0) {
 527                 dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
 528                 return ret;
 529         }
 530
 531         /* Do a proper reset after power up */
 532         cs4271_reset(component);
 533
 534         /* Restore codec state */
 535         ret = regcache_sync(cs4271->regmap);
 536         if (ret < 0)
 537                 return ret;
 538
 539         /* then disable the power-down bit */
 540         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
 541                                  CS4271_MODE2_PDN, 0);
 542         if (ret < 0)
 543                 return ret;
 544
 545         return 0;
 546 }
 547 #else
 548 #define cs4271_soc_suspend      NULL
 549 #define cs4271_soc_resume       NULL
 550 #endif /* CONFIG_PM */
 551
 552 #ifdef CONFIG_OF
 553 const struct of_device_id cs4271_dt_ids[] = {
 554         { .compatible = "cirrus,cs4271", },
 555         { }
 556 };
 557 MODULE_DEVICE_TABLE(of, cs4271_dt_ids);
 558 EXPORT_SYMBOL_GPL(cs4271_dt_ids);
 559 #endif
 560
 561 static int cs4271_component_probe(struct snd_soc_component *component)
 562 {
 563         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 564         struct cs4271_platform_data *cs4271plat = component->dev->platform_data;
 565         int ret;
 566         bool amutec_eq_bmutec = false;
 567
 568 #ifdef CONFIG_OF
 569         if (of_match_device(cs4271_dt_ids, component->dev)) {
 570                 if (of_get_property(component->dev->of_node,
 571                                      "cirrus,amutec-eq-bmutec", NULL))
 572                         amutec_eq_bmutec = true;
 573
 574                 if (of_get_property(component->dev->of_node,
 575                                      "cirrus,enable-soft-reset", NULL))
 576                         cs4271->enable_soft_reset = true;
 577         }
 578 #endif
 579
 580         ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies),
 581                                     cs4271->supplies);
 582         if (ret < 0) {
 583                 dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
 584                 return ret;
 585         }
 586
 587         if (cs4271plat) {
 588                 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec;
 589                 cs4271->enable_soft_reset = cs4271plat->enable_soft_reset;
 590         }
 591
 592         /* Reset codec */
 593         cs4271_reset(component);
 594
 595         ret = regcache_sync(cs4271->regmap);
 596         if (ret < 0)
 597                 return ret;
 598
 599         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
 600                                  CS4271_MODE2_PDN | CS4271_MODE2_CPEN,
 601                                  CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
 602         if (ret < 0)
 603                 return ret;
 604         ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
 605                                  CS4271_MODE2_PDN, 0);
 606         if (ret < 0)
 607                 return ret;
 608         /* Power-up sequence requires 85 uS */
 609         udelay(85);
 610
 611         if (amutec_eq_bmutec)
 612                 regmap_update_bits(cs4271->regmap, CS4271_MODE2,
 613                                    CS4271_MODE2_MUTECAEQUB,
 614                                    CS4271_MODE2_MUTECAEQUB);
 615
 616         return 0;
 617 }
 618
 619 static void cs4271_component_remove(struct snd_soc_component *component)
 620 {
 621         struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
 622
 623         if (gpio_is_valid(cs4271->gpio_nreset))
 624                 /* Set codec to the reset state */
 625                 gpio_set_value(cs4271->gpio_nreset, 0);
 626
 627         regcache_mark_dirty(cs4271->regmap);
 628         regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies);
 629 };
 630
 631 static const struct snd_soc_component_driver soc_component_dev_cs4271 = {
 632         .probe                  = cs4271_component_probe,
 633         .remove                 = cs4271_component_remove,
 634         .suspend                = cs4271_soc_suspend,
 635         .resume                 = cs4271_soc_resume,
 636         .controls               = cs4271_snd_controls,
 637         .num_controls           = ARRAY_SIZE(cs4271_snd_controls),
 638         .dapm_widgets           = cs4271_dapm_widgets,
 639         .num_dapm_widgets       = ARRAY_SIZE(cs4271_dapm_widgets),
 640         .dapm_routes            = cs4271_dapm_routes,
 641         .num_dapm_routes        = ARRAY_SIZE(cs4271_dapm_routes),
 642         .idle_bias_on           = 1,
 643         .use_pmdown_time        = 1,
 644         .endianness             = 1,
 645         .non_legacy_dai_naming  = 1,
 646 };
 647
 648 static int cs4271_common_probe(struct device *dev,
 649                                struct cs4271_private **c)
 650 {
 651         struct cs4271_platform_data *cs4271plat = dev->platform_data;
 652         struct cs4271_private *cs4271;
 653         int i, ret;
 654
 655         cs4271 = devm_kzalloc(dev, sizeof(*cs4271), GFP_KERNEL);
 656         if (!cs4271)
 657                 return -ENOMEM;
 658
 659         if (of_match_device(cs4271_dt_ids, dev))
 660                 cs4271->gpio_nreset =
 661                         of_get_named_gpio(dev->of_node, "reset-gpio", 0);
 662
 663         if (cs4271plat)
 664                 cs4271->gpio_nreset = cs4271plat->gpio_nreset;
 665
 666         if (gpio_is_valid(cs4271->gpio_nreset)) {
 667                 ret = devm_gpio_request(dev, cs4271->gpio_nreset,
 668                                         "CS4271 Reset");
 669                 if (ret < 0)
 670                         return ret;
 671         }
 672
 673         for (i = 0; i < ARRAY_SIZE(supply_names); i++)
 674                 cs4271->supplies[i].supply = supply_names[i];
 675
 676         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs4271->supplies),
 677                                         cs4271->supplies);
 678
 679         if (ret < 0) {
 680                 dev_err(dev, "Failed to get regulators: %d\n", ret);
 681                 return ret;
 682         }
 683
 684         *c = cs4271;
 685         return 0;
 686 }
 687
 688 const struct regmap_config cs4271_regmap_config = {
 689         .max_register = CS4271_LASTREG,
 690
 691         .reg_defaults = cs4271_reg_defaults,
 692         .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults),
 693         .cache_type = REGCACHE_RBTREE,
 694
 695         .volatile_reg = cs4271_volatile_reg,
 696 };
 697 EXPORT_SYMBOL_GPL(cs4271_regmap_config);
 698
 699 int cs4271_probe(struct device *dev, struct regmap *regmap)
 700 {
 701         struct cs4271_private *cs4271;
 702         int ret;
 703
 704         if (IS_ERR(regmap))
 705                 return PTR_ERR(regmap);
 706
 707         ret = cs4271_common_probe(dev, &cs4271);
 708         if (ret < 0)
 709                 return ret;
 710
 711         dev_set_drvdata(dev, cs4271);
 712         cs4271->regmap = regmap;
 713
 714         return devm_snd_soc_register_component(dev, &soc_component_dev_cs4271,
 715                                                &cs4271_dai, 1);
 716 }
 717 EXPORT_SYMBOL_GPL(cs4271_probe);
 718
 719 MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
 720 MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
 721 MODULE_LICENSE("GPL");