sound/soc/codecs/max98373.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017, Maxim Integrated
   3
   4 #ifndef _MAX98373_H
   5 #define _MAX98373_H
   6
   7 #define MAX98373_R2000_SW_RESET 0x2000
   8 #define MAX98373_R2001_INT_RAW1 0x2001
   9 #define MAX98373_R2002_INT_RAW2 0x2002
  10 #define MAX98373_R2003_INT_RAW3 0x2003
  11 #define MAX98373_R2004_INT_STATE1 0x2004
  12 #define MAX98373_R2005_INT_STATE2 0x2005
  13 #define MAX98373_R2006_INT_STATE3 0x2006
  14 #define MAX98373_R2007_INT_FLAG1 0x2007
  15 #define MAX98373_R2008_INT_FLAG2 0x2008
  16 #define MAX98373_R2009_INT_FLAG3 0x2009
  17 #define MAX98373_R200A_INT_EN1 0x200A
  18 #define MAX98373_R200B_INT_EN2 0x200B
  19 #define MAX98373_R200C_INT_EN3 0x200C
  20 #define MAX98373_R200D_INT_FLAG_CLR1 0x200D
  21 #define MAX98373_R200E_INT_FLAG_CLR2 0x200E
  22 #define MAX98373_R200F_INT_FLAG_CLR3 0x200F
  23 #define MAX98373_R2010_IRQ_CTRL 0x2010
  24 #define MAX98373_R2014_THERM_WARN_THRESH 0x2014
  25 #define MAX98373_R2015_THERM_SHDN_THRESH 0x2015
  26 #define MAX98373_R2016_THERM_HYSTERESIS 0x2016
  27 #define MAX98373_R2017_THERM_FOLDBACK_SET 0x2017
  28 #define MAX98373_R2018_THERM_FOLDBACK_EN 0x2018
  29 #define MAX98373_R201E_PIN_DRIVE_STRENGTH 0x201E
  30 #define MAX98373_R2020_PCM_TX_HIZ_EN_1 0x2020
  31 #define MAX98373_R2021_PCM_TX_HIZ_EN_2 0x2021
  32 #define MAX98373_R2022_PCM_TX_SRC_1 0x2022
  33 #define MAX98373_R2023_PCM_TX_SRC_2 0x2023
  34 #define MAX98373_R2024_PCM_DATA_FMT_CFG 0x2024
  35 #define MAX98373_R2025_AUDIO_IF_MODE 0x2025
  36 #define MAX98373_R2026_PCM_CLOCK_RATIO 0x2026
  37 #define MAX98373_R2027_PCM_SR_SETUP_1 0x2027
  38 #define MAX98373_R2028_PCM_SR_SETUP_2 0x2028
  39 #define MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1 0x2029
  40 #define MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2 0x202A
  41 #define MAX98373_R202B_PCM_RX_EN 0x202B
  42 #define MAX98373_R202C_PCM_TX_EN 0x202C
  43 #define MAX98373_R202E_ICC_RX_CH_EN_1 0x202E
  44 #define MAX98373_R202F_ICC_RX_CH_EN_2 0x202F
  45 #define MAX98373_R2030_ICC_TX_HIZ_EN_1 0x2030
  46 #define MAX98373_R2031_ICC_TX_HIZ_EN_2 0x2031
  47 #define MAX98373_R2032_ICC_LINK_EN_CFG 0x2032
  48 #define MAX98373_R2034_ICC_TX_CNTL 0x2034
  49 #define MAX98373_R2035_ICC_TX_EN 0x2035
  50 #define MAX98373_R2036_SOUNDWIRE_CTRL 0x2036
  51 #define MAX98373_R203D_AMP_DIG_VOL_CTRL 0x203D
  52 #define MAX98373_R203E_AMP_PATH_GAIN 0x203E
  53 #define MAX98373_R203F_AMP_DSP_CFG 0x203F
  54 #define MAX98373_R2040_TONE_GEN_CFG 0x2040
  55 #define MAX98373_R2041_AMP_CFG 0x2041
  56 #define MAX98373_R2042_AMP_EDGE_RATE_CFG 0x2042
  57 #define MAX98373_R2043_AMP_EN 0x2043
  58 #define MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 0x2046
  59 #define MAX98373_R2047_IV_SENSE_ADC_EN 0x2047
  60 #define MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 0x2051
  61 #define MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG 0x2052
  62 #define MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG 0x2053
  63 #define MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK 0x2054
  64 #define MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK 0x2055
  65 #define MAX98373_R2056_MEAS_ADC_PVDD_CH_EN 0x2056
  66 #define MAX98373_R2090_BDE_LVL_HOLD 0x2090
  67 #define MAX98373_R2091_BDE_GAIN_ATK_REL_RATE 0x2091
  68 #define MAX98373_R2092_BDE_CLIPPER_MODE 0x2092
  69 #define MAX98373_R2097_BDE_L1_THRESH 0x2097
  70 #define MAX98373_R2098_BDE_L2_THRESH 0x2098
  71 #define MAX98373_R2099_BDE_L3_THRESH 0x2099
  72 #define MAX98373_R209A_BDE_L4_THRESH 0x209A
  73 #define MAX98373_R209B_BDE_THRESH_HYST 0x209B
  74 #define MAX98373_R20A8_BDE_L1_CFG_1 0x20A8
  75 #define MAX98373_R20A9_BDE_L1_CFG_2 0x20A9
  76 #define MAX98373_R20AA_BDE_L1_CFG_3 0x20AA
  77 #define MAX98373_R20AB_BDE_L2_CFG_1 0x20AB
  78 #define MAX98373_R20AC_BDE_L2_CFG_2 0x20AC
  79 #define MAX98373_R20AD_BDE_L2_CFG_3 0x20AD
  80 #define MAX98373_R20AE_BDE_L3_CFG_1 0x20AE
  81 #define MAX98373_R20AF_BDE_L3_CFG_2 0x20AF
  82 #define MAX98373_R20B0_BDE_L3_CFG_3 0x20B0
  83 #define MAX98373_R20B1_BDE_L4_CFG_1 0x20B1
  84 #define MAX98373_R20B2_BDE_L4_CFG_2 0x20B2
  85 #define MAX98373_R20B3_BDE_L4_CFG_3 0x20B3
  86 #define MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE 0x20B4
  87 #define MAX98373_R20B5_BDE_EN 0x20B5
  88 #define MAX98373_R20B6_BDE_CUR_STATE_READBACK 0x20B6
  89 #define MAX98373_R20D1_DHT_CFG 0x20D1
  90 #define MAX98373_R20D2_DHT_ATTACK_CFG 0x20D2
  91 #define MAX98373_R20D3_DHT_RELEASE_CFG 0x20D3
  92 #define MAX98373_R20D4_DHT_EN 0x20D4
  93 #define MAX98373_R20E0_LIMITER_THRESH_CFG 0x20E0
  94 #define MAX98373_R20E1_LIMITER_ATK_REL_RATES 0x20E1
  95 #define MAX98373_R20E2_LIMITER_EN 0x20E2
  96 #define MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 0x20FE
  97 #define MAX98373_R20FF_GLOBAL_SHDN 0x20FF
  98 #define MAX98373_R21FF_REV_ID 0x21FF
  99
 100 /* MAX98373_R2022_PCM_TX_SRC_1 */
 101 #define MAX98373_PCM_TX_CH_SRC_A_V_SHIFT (0)
 102 #define MAX98373_PCM_TX_CH_SRC_A_I_SHIFT (4)
 103
 104 /* MAX98373_R2024_PCM_DATA_FMT_CFG */
 105 #define MAX98373_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
 106 #define MAX98373_PCM_MODE_CFG_FORMAT_SHIFT (3)
 107 #define MAX98373_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2)
 108 #define MAX98373_PCM_FORMAT_I2S (0x0 << 0)
 109 #define MAX98373_PCM_FORMAT_LJ (0x1 << 0)
 110 #define MAX98373_PCM_FORMAT_TDM_MODE0 (0x3 << 0)
 111 #define MAX98373_PCM_FORMAT_TDM_MODE1 (0x4 << 0)
 112 #define MAX98373_PCM_FORMAT_TDM_MODE2 (0x5 << 0)
 113 #define MAX98373_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
 114 #define MAX98373_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
 115 #define MAX98373_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
 116 #define MAX98373_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
 117
 118 /* MAX98373_R2026_PCM_CLOCK_RATIO */
 119 #define MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 4)
 120 #define MAX98373_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
 121
 122 /* MAX98373_R2027_PCM_SR_SETUP_1 */
 123 #define MAX98373_PCM_SR_SET1_SR_MASK (0xF << 0)
 124 #define MAX98373_PCM_SR_SET1_SR_8000 (0x0 << 0)
 125 #define MAX98373_PCM_SR_SET1_SR_11025 (0x1 << 0)
 126 #define MAX98373_PCM_SR_SET1_SR_12000 (0x2 << 0)
 127 #define MAX98373_PCM_SR_SET1_SR_16000 (0x3 << 0)
 128 #define MAX98373_PCM_SR_SET1_SR_22050 (0x4 << 0)
 129 #define MAX98373_PCM_SR_SET1_SR_24000 (0x5 << 0)
 130 #define MAX98373_PCM_SR_SET1_SR_32000 (0x6 << 0)
 131 #define MAX98373_PCM_SR_SET1_SR_44100 (0x7 << 0)
 132 #define MAX98373_PCM_SR_SET1_SR_48000 (0x8 << 0)
 133 #define MAX98373_PCM_SR_SET1_SR_88200 (0x9 << 0)
 134 #define MAX98373_PCM_SR_SET1_SR_96000 (0xA << 0)
 135
 136 /* MAX98373_R2028_PCM_SR_SETUP_2 */
 137 #define MAX98373_PCM_SR_SET2_SR_MASK (0xF << 4)
 138 #define MAX98373_PCM_SR_SET2_SR_SHIFT (4)
 139 #define MAX98373_PCM_SR_SET2_IVADC_SR_MASK (0xF << 0)
 140
 141 /* MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1 */
 142 #define MAX98373_PCM_TO_SPK_MONOMIX_CFG_MASK (0x3 << 6)
 143 #define MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT (6)
 144 #define MAX98373_PCM_TO_SPK_CH0_SRC_MASK (0xF << 0)
 145
 146 /* MAX98373_R203E_AMP_PATH_GAIN */
 147 #define MAX98373_SPK_DIGI_GAIN_MASK (0xF << 4)
 148 #define MAX98373_SPK_DIGI_GAIN_SHIFT (4)
 149 #define MAX98373_FS_GAIN_MAX_MASK (0xF << 0)
 150 #define MAX98373_FS_GAIN_MAX_SHIFT (0)
 151
 152 /* MAX98373_R203F_AMP_DSP_CFG */
 153 #define MAX98373_AMP_DSP_CFG_DCBLK_SHIFT (0)
 154 #define MAX98373_AMP_DSP_CFG_DITH_SHIFT (1)
 155 #define MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT (2)
 156 #define MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT (3)
 157 #define MAX98373_AMP_DSP_CFG_DAC_INV_SHIFT (5)
 158 #define MAX98373_AMP_VOL_SEL_SHIFT (7)
 159
 160 /* MAX98373_R2043_AMP_EN */
 161 #define MAX98373_SPKFB_EN_MASK (0x1 << 1)
 162 #define MAX98373_SPK_EN_MASK (0x1 << 0)
 163 #define MAX98373_SPKFB_EN_SHIFT (1)
 164
 165 /*MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG */
 166 #define MAX98373_FLT_EN_SHIFT (4)
 167
 168 /* MAX98373_R20B2_BDE_L4_CFG_2 */
 169 #define MAX98373_LVL4_MUTE_EN_SHIFT (7)
 170 #define MAX98373_LVL4_HOLD_EN_SHIFT (6)
 171
 172 /* MAX98373_R20B5_BDE_EN */
 173 #define MAX98373_BDE_EN_SHIFT (0)
 174
 175 /* MAX98373_R20D1_DHT_CFG */
 176 #define MAX98373_DHT_SPK_GAIN_MIN_SHIFT (4)
 177 #define MAX98373_DHT_ROT_PNT_SHIFT      (0)
 178
 179 /* MAX98373_R20D2_DHT_ATTACK_CFG */
 180 #define MAX98373_DHT_ATTACK_STEP_SHIFT (3)
 181 #define MAX98373_DHT_ATTACK_RATE_SHIFT (0)
 182
 183 /* MAX98373_R20D3_DHT_RELEASE_CFG */
 184 #define MAX98373_DHT_RELEASE_STEP_SHIFT (3)
 185 #define MAX98373_DHT_RELEASE_RATE_SHIFT (0)
 186
 187 /* MAX98373_R20D4_DHT_EN */
 188 #define MAX98373_DHT_EN_SHIFT (0)
 189
 190 /* MAX98373_R20E0_LIMITER_THRESH_CFG */
 191 #define MAX98373_LIMITER_THRESH_SHIFT (2)
 192 #define MAX98373_LIMITER_THRESH_SRC_SHIFT (0)
 193
 194 /* MAX98373_R20E2_LIMITER_EN */
 195 #define MAX98373_LIMITER_EN_SHIFT (0)
 196
 197 /* MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG */
 198 #define MAX98373_CLOCK_MON_SHIFT (0)
 199
 200 /* MAX98373_R20FF_GLOBAL_SHDN */
 201 #define MAX98373_GLOBAL_EN_MASK (0x1 << 0)
 202
 203 /* MAX98373_R2000_SW_RESET */
 204 #define MAX98373_SOFT_RESET (0x1 << 0)
 205
 206 struct max98373_priv {
 207         struct regmap *regmap;
 208         int reset_gpio;
 209         unsigned int v_slot;
 210         unsigned int i_slot;
 211         unsigned int spkfb_slot;
 212         bool interleave_mode;
 213         unsigned int ch_size;
 214         bool tdm_mode;
 215 };
 216 #endif