sound/soc/codecs/max98925.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * max98925.c -- ALSA SoC Stereo MAX98925 driver
   4  * Copyright 2013-15 Maxim Integrated Products
   5  */
   6 #include <linux/delay.h>
   7 #include <linux/i2c.h>
   8 #include <linux/module.h>
   9 #include <linux/regmap.h>
  10 #include <linux/slab.h>
  11 #include <linux/cdev.h>
  12 #include <sound/pcm.h>
  13 #include <sound/pcm_params.h>
  14 #include <sound/soc.h>
  15 #include <sound/tlv.h>
  16 #include "max98925.h"
  17
  18 static const char *const dai_text[] = {
  19         "Left", "Right", "LeftRight", "LeftRightDiv2",
  20 };
  21
  22 static const char * const max98925_boost_voltage_text[] = {
  23         "8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
  24         "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
  25 };
  26
  27 static SOC_ENUM_SINGLE_DECL(max98925_boost_voltage,
  28         MAX98925_CONFIGURATION, M98925_BST_VOUT_SHIFT,
  29         max98925_boost_voltage_text);
  30
  31 static const char *const hpf_text[] = {
  32         "Disable", "DC Block", "100Hz", "200Hz", "400Hz", "800Hz",
  33 };
  34
  35 static const struct reg_default max98925_reg[] = {
  36         { 0x0B, 0x00 }, /* IRQ Enable0 */
  37         { 0x0C, 0x00 }, /* IRQ Enable1 */
  38         { 0x0D, 0x00 }, /* IRQ Enable2 */
  39         { 0x0E, 0x00 }, /* IRQ Clear0 */
  40         { 0x0F, 0x00 }, /* IRQ Clear1 */
  41         { 0x10, 0x00 }, /* IRQ Clear2 */
  42         { 0x11, 0xC0 }, /* Map0 */
  43         { 0x12, 0x00 }, /* Map1 */
  44         { 0x13, 0x00 }, /* Map2 */
  45         { 0x14, 0xF0 }, /* Map3 */
  46         { 0x15, 0x00 }, /* Map4 */
  47         { 0x16, 0xAB }, /* Map5 */
  48         { 0x17, 0x89 }, /* Map6 */
  49         { 0x18, 0x00 }, /* Map7 */
  50         { 0x19, 0x00 }, /* Map8 */
  51         { 0x1A, 0x06 }, /* DAI Clock Mode 1 */
  52         { 0x1B, 0xC0 }, /* DAI Clock Mode 2 */
  53         { 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
  54         { 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
  55         { 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
  56         { 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
  57         { 0x20, 0x50 }, /* Format */
  58         { 0x21, 0x00 }, /* TDM Slot Select */
  59         { 0x22, 0x00 }, /* DOUT Configuration VMON */
  60         { 0x23, 0x00 }, /* DOUT Configuration IMON */
  61         { 0x24, 0x00 }, /* DOUT Configuration VBAT */
  62         { 0x25, 0x00 }, /* DOUT Configuration VBST */
  63         { 0x26, 0x00 }, /* DOUT Configuration FLAG */
  64         { 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
  65         { 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
  66         { 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
  67         { 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
  68         { 0x2B, 0x02 }, /* DOUT Drive Strength */
  69         { 0x2C, 0x90 }, /* Filters */
  70         { 0x2D, 0x00 }, /* Gain */
  71         { 0x2E, 0x02 }, /* Gain Ramping */
  72         { 0x2F, 0x00 }, /* Speaker Amplifier */
  73         { 0x30, 0x0A }, /* Threshold */
  74         { 0x31, 0x00 }, /* ALC Attack */
  75         { 0x32, 0x80 }, /* ALC Atten and Release */
  76         { 0x33, 0x00 }, /* ALC Infinite Hold Release */
  77         { 0x34, 0x92 }, /* ALC Configuration */
  78         { 0x35, 0x01 }, /* Boost Converter */
  79         { 0x36, 0x00 }, /* Block Enable */
  80         { 0x37, 0x00 }, /* Configuration */
  81         { 0x38, 0x00 }, /* Global Enable */
  82         { 0x3A, 0x00 }, /* Boost Limiter */
  83 };
  84
  85 static const struct soc_enum max98925_dai_enum =
  86         SOC_ENUM_SINGLE(MAX98925_GAIN, 5, ARRAY_SIZE(dai_text), dai_text);
  87
  88 static const struct soc_enum max98925_hpf_enum =
  89         SOC_ENUM_SINGLE(MAX98925_FILTERS, 0, ARRAY_SIZE(hpf_text), hpf_text);
  90
  91 static const struct snd_kcontrol_new max98925_hpf_sel_mux =
  92         SOC_DAPM_ENUM("Rc Filter MUX Mux", max98925_hpf_enum);
  93
  94 static const struct snd_kcontrol_new max98925_dai_sel_mux =
  95         SOC_DAPM_ENUM("DAI IN MUX Mux", max98925_dai_enum);
  96
  97 static int max98925_dac_event(struct snd_soc_dapm_widget *w,
  98                 struct snd_kcontrol *kcontrol, int event)
  99 {
 100         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 101         struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
 102
 103         switch (event) {
 104         case SND_SOC_DAPM_PRE_PMU:
 105                 regmap_update_bits(max98925->regmap,
 106                         MAX98925_BLOCK_ENABLE,
 107                         M98925_BST_EN_MASK |
 108                         M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK,
 109                         M98925_BST_EN_MASK |
 110                         M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK);
 111                 break;
 112         case SND_SOC_DAPM_POST_PMD:
 113                 regmap_update_bits(max98925->regmap,
 114                         MAX98925_BLOCK_ENABLE, M98925_BST_EN_MASK |
 115                         M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK, 0);
 116                 break;
 117         default:
 118                 return 0;
 119         }
 120         return 0;
 121 }
 122
 123 static const struct snd_soc_dapm_widget max98925_dapm_widgets[] = {
 124         SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
 125         SND_SOC_DAPM_MUX("DAI IN MUX", SND_SOC_NOPM, 0, 0,
 126                                 &max98925_dai_sel_mux),
 127         SND_SOC_DAPM_MUX("Rc Filter MUX", SND_SOC_NOPM, 0, 0,
 128                                 &max98925_hpf_sel_mux),
 129         SND_SOC_DAPM_DAC_E("Amp Enable", NULL, MAX98925_BLOCK_ENABLE,
 130                         M98925_SPK_EN_SHIFT, 0, max98925_dac_event,
 131                         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 132         SND_SOC_DAPM_SUPPLY("Global Enable", MAX98925_GLOBAL_ENABLE,
 133                         M98925_EN_SHIFT, 0, NULL, 0),
 134         SND_SOC_DAPM_OUTPUT("BE_OUT"),
 135 };
 136
 137 static const struct snd_soc_dapm_route max98925_audio_map[] = {
 138         {"DAI IN MUX", "Left", "DAI_OUT"},
 139         {"DAI IN MUX", "Right", "DAI_OUT"},
 140         {"DAI IN MUX", "LeftRight", "DAI_OUT"},
 141         {"DAI IN MUX", "LeftRightDiv2", "DAI_OUT"},
 142         {"Rc Filter MUX", "Disable", "DAI IN MUX"},
 143         {"Rc Filter MUX", "DC Block", "DAI IN MUX"},
 144         {"Rc Filter MUX", "100Hz", "DAI IN MUX"},
 145         {"Rc Filter MUX", "200Hz", "DAI IN MUX"},
 146         {"Rc Filter MUX", "400Hz", "DAI IN MUX"},
 147         {"Rc Filter MUX", "800Hz", "DAI IN MUX"},
 148         {"Amp Enable", NULL, "Rc Filter MUX"},
 149         {"BE_OUT", NULL, "Amp Enable"},
 150         {"BE_OUT", NULL, "Global Enable"},
 151 };
 152
 153 static bool max98925_volatile_register(struct device *dev, unsigned int reg)
 154 {
 155         switch (reg) {
 156         case MAX98925_VBAT_DATA:
 157         case MAX98925_VBST_DATA:
 158         case MAX98925_LIVE_STATUS0:
 159         case MAX98925_LIVE_STATUS1:
 160         case MAX98925_LIVE_STATUS2:
 161         case MAX98925_STATE0:
 162         case MAX98925_STATE1:
 163         case MAX98925_STATE2:
 164         case MAX98925_FLAG0:
 165         case MAX98925_FLAG1:
 166         case MAX98925_FLAG2:
 167         case MAX98925_REV_VERSION:
 168                 return true;
 169         default:
 170                 return false;
 171         }
 172 }
 173
 174 static bool max98925_readable_register(struct device *dev, unsigned int reg)
 175 {
 176         switch (reg) {
 177         case MAX98925_IRQ_CLEAR0:
 178         case MAX98925_IRQ_CLEAR1:
 179         case MAX98925_IRQ_CLEAR2:
 180         case MAX98925_ALC_HOLD_RLS:
 181                 return false;
 182         default:
 183                 return true;
 184         }
 185 }
 186
 187 static DECLARE_TLV_DB_SCALE(max98925_spk_tlv, -600, 100, 0);
 188
 189 static const struct snd_kcontrol_new max98925_snd_controls[] = {
 190         SOC_SINGLE_TLV("Speaker Volume", MAX98925_GAIN,
 191                 M98925_SPK_GAIN_SHIFT, (1<<M98925_SPK_GAIN_WIDTH)-1, 0,
 192                 max98925_spk_tlv),
 193         SOC_SINGLE("Ramp Switch", MAX98925_GAIN_RAMPING,
 194                                 M98925_SPK_RMP_EN_SHIFT, 1, 0),
 195         SOC_SINGLE("ZCD Switch", MAX98925_GAIN_RAMPING,
 196                                 M98925_SPK_ZCD_EN_SHIFT, 1, 0),
 197         SOC_SINGLE("ALC Switch", MAX98925_THRESHOLD,
 198                                 M98925_ALC_EN_SHIFT, 1, 0),
 199         SOC_SINGLE("ALC Threshold", MAX98925_THRESHOLD, M98925_ALC_TH_SHIFT,
 200                                 (1<<M98925_ALC_TH_WIDTH)-1, 0),
 201         SOC_ENUM("Boost Output Voltage", max98925_boost_voltage),
 202 };
 203
 204 /* codec sample rate and n/m dividers parameter table */
 205 static const struct {
 206         int rate;
 207         int  sr;
 208         int divisors[3][2];
 209 } rate_table[] = {
 210         {
 211                 .rate = 8000,
 212                 .sr = 0,
 213                 .divisors = { {1, 375}, {5, 1764}, {1, 384} }
 214         },
 215         {
 216                 .rate = 11025,
 217                 .sr = 1,
 218                 .divisors = { {147, 40000}, {1, 256}, {147, 40960} }
 219         },
 220         {
 221                 .rate = 12000,
 222                 .sr = 2,
 223                 .divisors = { {1, 250}, {5, 1176}, {1, 256} }
 224         },
 225         {
 226                 .rate = 16000,
 227                 .sr = 3,
 228                 .divisors = { {2, 375}, {5, 882}, {1, 192} }
 229         },
 230         {
 231                 .rate = 22050,
 232                 .sr = 4,
 233                 .divisors = { {147, 20000}, {1, 128}, {147, 20480} }
 234         },
 235         {
 236                 .rate = 24000,
 237                 .sr = 5,
 238                 .divisors = { {1, 125}, {5, 588}, {1, 128} }
 239         },
 240         {
 241                 .rate = 32000,
 242                 .sr = 6,
 243                 .divisors = { {4, 375}, {5, 441}, {1, 96} }
 244         },
 245         {
 246                 .rate = 44100,
 247                 .sr = 7,
 248                 .divisors = { {147, 10000}, {1, 64}, {147, 10240} }
 249         },
 250         {
 251                 .rate = 48000,
 252                 .sr = 8,
 253                 .divisors = { {2, 125}, {5, 294}, {1, 64} }
 254         },
 255 };
 256
 257 static inline int max98925_rate_value(struct snd_soc_component *component,
 258                 int rate, int clock, int *value, int *n, int *m)
 259 {
 260         int ret = -EINVAL;
 261         int i;
 262
 263         for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
 264                 if (rate_table[i].rate >= rate) {
 265                         *value = rate_table[i].sr;
 266                         *n = rate_table[i].divisors[clock][0];
 267                         *m = rate_table[i].divisors[clock][1];
 268                         ret = 0;
 269                         break;
 270                 }
 271         }
 272         return ret;
 273 }
 274
 275 static void max98925_set_sense_data(struct max98925_priv *max98925)
 276 {
 277         /* set VMON slots */
 278         regmap_update_bits(max98925->regmap,
 279                 MAX98925_DOUT_CFG_VMON,
 280                 M98925_DAI_VMON_EN_MASK, M98925_DAI_VMON_EN_MASK);
 281         regmap_update_bits(max98925->regmap,
 282                 MAX98925_DOUT_CFG_VMON,
 283                 M98925_DAI_VMON_SLOT_MASK,
 284                 max98925->v_slot << M98925_DAI_VMON_SLOT_SHIFT);
 285         /* set IMON slots */
 286         regmap_update_bits(max98925->regmap,
 287                 MAX98925_DOUT_CFG_IMON,
 288                 M98925_DAI_IMON_EN_MASK, M98925_DAI_IMON_EN_MASK);
 289         regmap_update_bits(max98925->regmap,
 290                 MAX98925_DOUT_CFG_IMON,
 291                 M98925_DAI_IMON_SLOT_MASK,
 292                 max98925->i_slot << M98925_DAI_IMON_SLOT_SHIFT);
 293 }
 294
 295 static int max98925_dai_set_fmt(struct snd_soc_dai *codec_dai,
 296                                  unsigned int fmt)
 297 {
 298         struct snd_soc_component *component = codec_dai->component;
 299         struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
 300         unsigned int invert = 0;
 301
 302         dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
 303         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 304         case SND_SOC_DAIFMT_CBS_CFS:
 305                 /* set DAI to slave mode */
 306                 regmap_update_bits(max98925->regmap,
 307                         MAX98925_DAI_CLK_MODE2,
 308                         M98925_DAI_MAS_MASK, 0);
 309                 max98925_set_sense_data(max98925);
 310                 break;
 311         case SND_SOC_DAIFMT_CBM_CFM:
 312                 /*
 313                  * set left channel DAI to master mode,
 314                  * right channel always slave
 315                  */
 316                 regmap_update_bits(max98925->regmap,
 317                         MAX98925_DAI_CLK_MODE2,
 318                         M98925_DAI_MAS_MASK, M98925_DAI_MAS_MASK);
 319                 break;
 320         case SND_SOC_DAIFMT_CBS_CFM:
 321         case SND_SOC_DAIFMT_CBM_CFS:
 322         default:
 323                 dev_err(component->dev, "DAI clock mode unsupported");
 324                 return -EINVAL;
 325         }
 326
 327         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 328         case SND_SOC_DAIFMT_NB_NF:
 329                 break;
 330         case SND_SOC_DAIFMT_NB_IF:
 331                 invert = M98925_DAI_WCI_MASK;
 332                 break;
 333         case SND_SOC_DAIFMT_IB_NF:
 334                 invert = M98925_DAI_BCI_MASK;
 335                 break;
 336         case SND_SOC_DAIFMT_IB_IF:
 337                 invert = M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK;
 338                 break;
 339         default:
 340                 dev_err(component->dev, "DAI invert mode unsupported");
 341                 return -EINVAL;
 342         }
 343
 344         regmap_update_bits(max98925->regmap, MAX98925_FORMAT,
 345                         M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK, invert);
 346         return 0;
 347 }
 348
 349 static int max98925_set_clock(struct max98925_priv *max98925,
 350                 struct snd_pcm_hw_params *params)
 351 {
 352         unsigned int dai_sr = 0, clock, mdll, n, m;
 353         struct snd_soc_component *component = max98925->component;
 354         int rate = params_rate(params);
 355         /* BCLK/LRCLK ratio calculation */
 356         int blr_clk_ratio = params_channels(params) * max98925->ch_size;
 357
 358         switch (blr_clk_ratio) {
 359         case 32:
 360                 regmap_update_bits(max98925->regmap,
 361                         MAX98925_DAI_CLK_MODE2,
 362                         M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_32);
 363                 break;
 364         case 48:
 365                 regmap_update_bits(max98925->regmap,
 366                         MAX98925_DAI_CLK_MODE2,
 367                         M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_48);
 368                 break;
 369         case 64:
 370                 regmap_update_bits(max98925->regmap,
 371                         MAX98925_DAI_CLK_MODE2,
 372                         M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_64);
 373                 break;
 374         default:
 375                 return -EINVAL;
 376         }
 377
 378         switch (max98925->sysclk) {
 379         case 6000000:
 380                 clock = 0;
 381                 mdll  = M98925_MDLL_MULT_MCLKx16;
 382                 break;
 383         case 11289600:
 384                 clock = 1;
 385                 mdll  = M98925_MDLL_MULT_MCLKx8;
 386                 break;
 387         case 12000000:
 388                 clock = 0;
 389                 mdll  = M98925_MDLL_MULT_MCLKx8;
 390                 break;
 391         case 12288000:
 392                 clock = 2;
 393                 mdll  = M98925_MDLL_MULT_MCLKx8;
 394                 break;
 395         default:
 396                 dev_info(max98925->component->dev, "unsupported sysclk %d\n",
 397                                         max98925->sysclk);
 398                 return -EINVAL;
 399         }
 400
 401         if (max98925_rate_value(component, rate, clock, &dai_sr, &n, &m))
 402                 return -EINVAL;
 403
 404         /* set DAI_SR to correct LRCLK frequency */
 405         regmap_update_bits(max98925->regmap,
 406                         MAX98925_DAI_CLK_MODE2,
 407                         M98925_DAI_SR_MASK, dai_sr << M98925_DAI_SR_SHIFT);
 408         /* set DAI m divider */
 409         regmap_write(max98925->regmap,
 410                 MAX98925_DAI_CLK_DIV_M_MSBS, m >> 8);
 411         regmap_write(max98925->regmap,
 412                 MAX98925_DAI_CLK_DIV_M_LSBS, m & 0xFF);
 413         /* set DAI n divider */
 414         regmap_write(max98925->regmap,
 415                 MAX98925_DAI_CLK_DIV_N_MSBS, n >> 8);
 416         regmap_write(max98925->regmap,
 417                 MAX98925_DAI_CLK_DIV_N_LSBS, n & 0xFF);
 418         /* set MDLL */
 419         regmap_update_bits(max98925->regmap, MAX98925_DAI_CLK_MODE1,
 420                         M98925_MDLL_MULT_MASK, mdll << M98925_MDLL_MULT_SHIFT);
 421         return 0;
 422 }
 423
 424 static int max98925_dai_hw_params(struct snd_pcm_substream *substream,
 425                                    struct snd_pcm_hw_params *params,
 426                                    struct snd_soc_dai *dai)
 427 {
 428         struct snd_soc_component *component = dai->component;
 429         struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
 430
 431         switch (params_width(params)) {
 432         case 16:
 433                 regmap_update_bits(max98925->regmap,
 434                                 MAX98925_FORMAT,
 435                                 M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_16);
 436                 max98925->ch_size = 16;
 437                 break;
 438         case 24:
 439                 regmap_update_bits(max98925->regmap,
 440                                 MAX98925_FORMAT,
 441                                 M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_24);
 442                 max98925->ch_size = 24;
 443                 break;
 444         case 32:
 445                 regmap_update_bits(max98925->regmap,
 446                                 MAX98925_FORMAT,
 447                                 M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_32);
 448                 max98925->ch_size = 32;
 449                 break;
 450         default:
 451                 pr_err("%s: format unsupported %d",
 452                                 __func__, params_format(params));
 453                 return -EINVAL;
 454         }
 455         dev_dbg(component->dev, "%s: format supported %d",
 456                                 __func__, params_format(params));
 457         return max98925_set_clock(max98925, params);
 458 }
 459
 460 static int max98925_dai_set_sysclk(struct snd_soc_dai *dai,
 461                                    int clk_id, unsigned int freq, int dir)
 462 {
 463         struct snd_soc_component *component = dai->component;
 464         struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
 465
 466         switch (clk_id) {
 467         case 0:
 468                 /* use MCLK for Left channel, right channel always BCLK */
 469                 regmap_update_bits(max98925->regmap,
 470                                 MAX98925_DAI_CLK_MODE1,
 471                                 M98925_DAI_CLK_SOURCE_MASK, 0);
 472                 break;
 473         case 1:
 474                 /* configure dai clock source to BCLK instead of MCLK */
 475                 regmap_update_bits(max98925->regmap,
 476                                 MAX98925_DAI_CLK_MODE1,
 477                                 M98925_DAI_CLK_SOURCE_MASK,
 478                                 M98925_DAI_CLK_SOURCE_MASK);
 479                 break;
 480         default:
 481                 return -EINVAL;
 482         }
 483         max98925->sysclk = freq;
 484         return 0;
 485 }
 486
 487 #define MAX98925_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
 488                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 489
 490 static const struct snd_soc_dai_ops max98925_dai_ops = {
 491         .set_sysclk = max98925_dai_set_sysclk,
 492         .set_fmt = max98925_dai_set_fmt,
 493         .hw_params = max98925_dai_hw_params,
 494 };
 495
 496 static struct snd_soc_dai_driver max98925_dai[] = {
 497         {
 498                 .name = "max98925-aif1",
 499                 .playback = {
 500                         .stream_name = "HiFi Playback",
 501                         .channels_min = 1,
 502                         .channels_max = 2,
 503                         .rates = SNDRV_PCM_RATE_8000_48000,
 504                         .formats = MAX98925_FORMATS,
 505                 },
 506                 .capture = {
 507                         .stream_name = "HiFi Capture",
 508                         .channels_min = 1,
 509                         .channels_max = 2,
 510                         .rates = SNDRV_PCM_RATE_8000_48000,
 511                         .formats = MAX98925_FORMATS,
 512                 },
 513                 .ops = &max98925_dai_ops,
 514         }
 515 };
 516
 517 static int max98925_probe(struct snd_soc_component *component)
 518 {
 519         struct max98925_priv *max98925 = snd_soc_component_get_drvdata(component);
 520
 521         max98925->component = component;
 522         regmap_write(max98925->regmap, MAX98925_GLOBAL_ENABLE, 0x00);
 523         /* It's not the default but we need to set DAI_DLY */
 524         regmap_write(max98925->regmap,
 525                         MAX98925_FORMAT, M98925_DAI_DLY_MASK);
 526         regmap_write(max98925->regmap, MAX98925_TDM_SLOT_SELECT, 0xC8);
 527         regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG1, 0xFF);
 528         regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG2, 0xFF);
 529         regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG3, 0xFF);
 530         regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG4, 0xF0);
 531         regmap_write(max98925->regmap, MAX98925_FILTERS, 0xD8);
 532         regmap_write(max98925->regmap, MAX98925_ALC_CONFIGURATION, 0xF8);
 533         regmap_write(max98925->regmap, MAX98925_CONFIGURATION, 0xF0);
 534         /* Disable ALC muting */
 535         regmap_write(max98925->regmap, MAX98925_BOOST_LIMITER, 0xF8);
 536         return 0;
 537 }
 538
 539 static const struct snd_soc_component_driver soc_component_dev_max98925 = {
 540         .probe                  = max98925_probe,
 541         .controls               = max98925_snd_controls,
 542         .num_controls           = ARRAY_SIZE(max98925_snd_controls),
 543         .dapm_routes            = max98925_audio_map,
 544         .num_dapm_routes        = ARRAY_SIZE(max98925_audio_map),
 545         .dapm_widgets           = max98925_dapm_widgets,
 546         .num_dapm_widgets       = ARRAY_SIZE(max98925_dapm_widgets),
 547         .idle_bias_on           = 1,
 548         .use_pmdown_time        = 1,
 549         .endianness             = 1,
 550         .non_legacy_dai_naming  = 1,
 551 };
 552
 553 static const struct regmap_config max98925_regmap = {
 554         .reg_bits         = 8,
 555         .val_bits         = 8,
 556         .max_register     = MAX98925_REV_VERSION,
 557         .reg_defaults     = max98925_reg,
 558         .num_reg_defaults = ARRAY_SIZE(max98925_reg),
 559         .volatile_reg     = max98925_volatile_register,
 560         .readable_reg     = max98925_readable_register,
 561         .cache_type       = REGCACHE_RBTREE,
 562 };
 563
 564 static int max98925_i2c_probe(struct i2c_client *i2c,
 565                              const struct i2c_device_id *id)
 566 {
 567         int ret, reg;
 568         u32 value;
 569         struct max98925_priv *max98925;
 570
 571         max98925 = devm_kzalloc(&i2c->dev,
 572                         sizeof(*max98925), GFP_KERNEL);
 573         if (!max98925)
 574                 return -ENOMEM;
 575
 576         i2c_set_clientdata(i2c, max98925);
 577         max98925->regmap = devm_regmap_init_i2c(i2c, &max98925_regmap);
 578         if (IS_ERR(max98925->regmap)) {
 579                 ret = PTR_ERR(max98925->regmap);
 580                 dev_err(&i2c->dev,
 581                                 "Failed to allocate regmap: %d\n", ret);
 582                 return ret;
 583         }
 584
 585         if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
 586                 if (value > M98925_DAI_VMON_SLOT_1E_1F) {
 587                         dev_err(&i2c->dev, "vmon slot number is wrong:\n");
 588                         return -EINVAL;
 589                 }
 590                 max98925->v_slot = value;
 591         }
 592         if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
 593                 if (value > M98925_DAI_IMON_SLOT_1E_1F) {
 594                         dev_err(&i2c->dev, "imon slot number is wrong:\n");
 595                         return -EINVAL;
 596                 }
 597                 max98925->i_slot = value;
 598         }
 599
 600         ret = regmap_read(max98925->regmap, MAX98925_REV_VERSION, &reg);
 601         if (ret < 0) {
 602                 dev_err(&i2c->dev, "Read revision failed\n");
 603                 return ret;
 604         }
 605
 606         if ((reg != MAX98925_VERSION) && (reg != MAX98925_VERSION1)) {
 607                 ret = -ENODEV;
 608                 dev_err(&i2c->dev, "Invalid revision (%d 0x%02X)\n",
 609                         ret, reg);
 610                 return ret;
 611         }
 612
 613         dev_info(&i2c->dev, "device version 0x%02X\n", reg);
 614
 615         ret = devm_snd_soc_register_component(&i2c->dev,
 616                         &soc_component_dev_max98925,
 617                         max98925_dai, ARRAY_SIZE(max98925_dai));
 618         if (ret < 0)
 619                 dev_err(&i2c->dev,
 620                                 "Failed to register component: %d\n", ret);
 621         return ret;
 622 }
 623
 624 static const struct i2c_device_id max98925_i2c_id[] = {
 625         { "max98925", 0 },
 626         { }
 627 };
 628 MODULE_DEVICE_TABLE(i2c, max98925_i2c_id);
 629
 630 static const struct of_device_id max98925_of_match[] = {
 631         { .compatible = "maxim,max98925", },
 632         { }
 633 };
 634 MODULE_DEVICE_TABLE(of, max98925_of_match);
 635
 636 static struct i2c_driver max98925_i2c_driver = {
 637         .driver = {
 638                 .name = "max98925",
 639                 .of_match_table = of_match_ptr(max98925_of_match),
 640                 .pm = NULL,
 641         },
 642         .probe  = max98925_i2c_probe,
 643         .id_table = max98925_i2c_id,
 644 };
 645
 646 module_i2c_driver(max98925_i2c_driver)
 647
 648 MODULE_DESCRIPTION("ALSA SoC MAX98925 driver");
 649 MODULE_AUTHOR("Ralph Birt <rdbirt@gmail.com>, Anish kumar <anish.kumar@maximintegrated.com>");
 650 MODULE_LICENSE("GPL");