sound/soc/codecs/rt1308.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // rt1308.c  --  RT1308 ALSA SoC amplifier component driver
   4 //
   5 // Copyright 2019 Realtek Semiconductor Corp.
   6 // Author: Derek Fang <derek.fang@realtek.com>
   7 //
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/gpio.h>
  15 #include <linux/i2c.h>
  16 #include <linux/regmap.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/acpi.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/firmware.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/soc.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/initval.h>
  27 #include <sound/tlv.h>
  28
  29 #include "rl6231.h"
  30 #include "rt1308.h"
  31
  32 static const struct reg_sequence init_list[] = {
  33
  34         { RT1308_I2C_I2S_SDW_SET,       0x01014005 },
  35         { RT1308_CLASS_D_SET_2,         0x227f5501 },
  36         { RT1308_PADS_1,                0x50150505 },
  37         { RT1308_VREF,                  0x18100000 },
  38         { RT1308_IV_SENSE,              0x87010000 },
  39         { RT1308_DUMMY_REG,             0x00000200 },
  40         { RT1308_SIL_DET,               0xe1c30000 },
  41         { RT1308_DC_CAL_2,              0x00ffff00 },
  42         { RT1308_CLK_DET,               0x01000000 },
  43         { RT1308_POWER_STATUS,          0x08800000 },
  44         { RT1308_DAC_SET,               0xafaf0700 },
  45
  46 };
  47 #define RT1308_INIT_REG_LEN ARRAY_SIZE(init_list)
  48
  49 struct rt1308_priv {
  50         struct snd_soc_component *component;
  51         struct regmap *regmap;
  52
  53         int sysclk;
  54         int sysclk_src;
  55         int lrck;
  56         int bclk;
  57         int master;
  58
  59         int pll_src;
  60         int pll_in;
  61         int pll_out;
  62 };
  63
  64 static const struct reg_default rt1308_reg[] = {
  65
  66         { 0x01, 0x1f3f5f00 },
  67         { 0x02, 0x07000000 },
  68         { 0x03, 0x80003e00 },
  69         { 0x04, 0x80800600 },
  70         { 0x05, 0x0aaa1a0a },
  71         { 0x06, 0x52000000 },
  72         { 0x07, 0x00000000 },
  73         { 0x08, 0x00600000 },
  74         { 0x09, 0xe1030000 },
  75         { 0x0a, 0x00000000 },
  76         { 0x0b, 0x30000000 },
  77         { 0x0c, 0x7fff7000 },
  78         { 0x10, 0xffff0700 },
  79         { 0x11, 0x0a000000 },
  80         { 0x12, 0x60040000 },
  81         { 0x13, 0x00000000 },
  82         { 0x14, 0x0f300000 },
  83         { 0x15, 0x00000022 },
  84         { 0x16, 0x02000000 },
  85         { 0x17, 0x01004045 },
  86         { 0x18, 0x00000000 },
  87         { 0x19, 0x00000000 },
  88         { 0x1a, 0x80000000 },
  89         { 0x1b, 0x10325476 },
  90         { 0x1c, 0x1d1d0000 },
  91         { 0x20, 0xd2101300 },
  92         { 0x21, 0xf3ffff00 },
  93         { 0x22, 0x00000000 },
  94         { 0x23, 0x00000000 },
  95         { 0x24, 0x00000000 },
  96         { 0x25, 0x00000000 },
  97         { 0x26, 0x00000000 },
  98         { 0x27, 0x00000000 },
  99         { 0x28, 0x00000000 },
 100         { 0x29, 0x00000000 },
 101         { 0x2a, 0x00000000 },
 102         { 0x2b, 0x00000000 },
 103         { 0x2c, 0x00000000 },
 104         { 0x2d, 0x00000000 },
 105         { 0x2e, 0x00000000 },
 106         { 0x2f, 0x00000000 },
 107         { 0x30, 0x01000000 },
 108         { 0x31, 0x20025501 },
 109         { 0x32, 0x00000000 },
 110         { 0x33, 0x105a0000 },
 111         { 0x34, 0x10100000 },
 112         { 0x35, 0x2aaa52aa },
 113         { 0x36, 0x00c00000 },
 114         { 0x37, 0x20046100 },
 115         { 0x50, 0x10022f00 },
 116         { 0x51, 0x003c0000 },
 117         { 0x54, 0x04000000 },
 118         { 0x55, 0x01000000 },
 119         { 0x56, 0x02000000 },
 120         { 0x57, 0x02000000 },
 121         { 0x58, 0x02000000 },
 122         { 0x59, 0x02000000 },
 123         { 0x5b, 0x02000000 },
 124         { 0x5c, 0x00000000 },
 125         { 0x5d, 0x00000000 },
 126         { 0x5e, 0x00000000 },
 127         { 0x5f, 0x00000000 },
 128         { 0x60, 0x02000000 },
 129         { 0x61, 0x00000000 },
 130         { 0x62, 0x00000000 },
 131         { 0x63, 0x00000000 },
 132         { 0x64, 0x00000000 },
 133         { 0x65, 0x02000000 },
 134         { 0x66, 0x00000000 },
 135         { 0x67, 0x00000000 },
 136         { 0x68, 0x00000000 },
 137         { 0x69, 0x00000000 },
 138         { 0x6a, 0x02000000 },
 139         { 0x6c, 0x00000000 },
 140         { 0x6d, 0x00000000 },
 141         { 0x6e, 0x00000000 },
 142         { 0x70, 0x10EC1308 },
 143         { 0x71, 0x00000000 },
 144         { 0x72, 0x00000000 },
 145         { 0x73, 0x00000000 },
 146         { 0x74, 0x00000000 },
 147         { 0x75, 0x00000000 },
 148         { 0x76, 0x00000000 },
 149         { 0x77, 0x00000000 },
 150         { 0x78, 0x00000000 },
 151         { 0x79, 0x00000000 },
 152         { 0x7a, 0x00000000 },
 153         { 0x7b, 0x00000000 },
 154         { 0x7c, 0x00000000 },
 155         { 0x7d, 0x00000000 },
 156         { 0x7e, 0x00000000 },
 157         { 0x7f, 0x00020f00 },
 158         { 0x80, 0x00000000 },
 159         { 0x81, 0x00000000 },
 160         { 0x82, 0x00000000 },
 161         { 0x83, 0x00000000 },
 162         { 0x84, 0x00000000 },
 163         { 0x85, 0x00000000 },
 164         { 0x86, 0x00000000 },
 165         { 0x87, 0x00000000 },
 166         { 0x88, 0x00000000 },
 167         { 0x89, 0x00000000 },
 168         { 0x8a, 0x00000000 },
 169         { 0x8b, 0x00000000 },
 170         { 0x8c, 0x00000000 },
 171         { 0x8d, 0x00000000 },
 172         { 0x8e, 0x00000000 },
 173         { 0x90, 0x50250905 },
 174         { 0x91, 0x15050000 },
 175         { 0xa0, 0x00000000 },
 176         { 0xa1, 0x00000000 },
 177         { 0xa2, 0x00000000 },
 178         { 0xa3, 0x00000000 },
 179         { 0xa4, 0x00000000 },
 180         { 0xb0, 0x00000000 },
 181         { 0xb1, 0x00000000 },
 182         { 0xb2, 0x00000000 },
 183         { 0xb3, 0x00000000 },
 184         { 0xb4, 0x00000000 },
 185         { 0xb5, 0x00000000 },
 186         { 0xb6, 0x00000000 },
 187         { 0xb7, 0x00000000 },
 188         { 0xb8, 0x00000000 },
 189         { 0xb9, 0x00000000 },
 190         { 0xba, 0x00000000 },
 191         { 0xbb, 0x00000000 },
 192         { 0xc0, 0x01000000 },
 193         { 0xc1, 0x00000000 },
 194         { 0xf0, 0x00000000 },
 195 };
 196
 197 static int rt1308_reg_init(struct snd_soc_component *component)
 198 {
 199         struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
 200
 201         return regmap_multi_reg_write(rt1308->regmap, init_list,
 202                                 RT1308_INIT_REG_LEN);
 203 }
 204
 205 static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
 206 {
 207         switch (reg) {
 208         case RT1308_RESET:
 209         case RT1308_RESET_N:
 210         case RT1308_CLK_2:
 211         case RT1308_SIL_DET:
 212         case RT1308_CLK_DET:
 213         case RT1308_DC_DET:
 214         case RT1308_DAC_SET:
 215         case RT1308_DAC_BUF:
 216         case RT1308_SDW_REG_RDATA:
 217         case RT1308_DC_CAL_1:
 218         case RT1308_PVDD_OFFSET_CTL:
 219         case RT1308_CAL_OFFSET_DAC_PBTL:
 220         case RT1308_CAL_OFFSET_DAC_L:
 221         case RT1308_CAL_OFFSET_DAC_R:
 222         case RT1308_CAL_OFFSET_PWM_L:
 223         case RT1308_CAL_OFFSET_PWM_R:
 224         case RT1308_CAL_PWM_VOS_ADC_L:
 225         case RT1308_CAL_PWM_VOS_ADC_R:
 226         case RT1308_MBIAS:
 227         case RT1308_POWER_STATUS:
 228         case RT1308_POWER_INT:
 229         case RT1308_SINE_TONE_GEN_2:
 230         case RT1308_BQ_SET:
 231         case RT1308_BQ_PARA_UPDATE:
 232         case RT1308_VEN_DEV_ID:
 233         case RT1308_VERSION_ID:
 234         case RT1308_EFUSE_1:
 235         case RT1308_EFUSE_READ_PVDD_L:
 236         case RT1308_EFUSE_READ_PVDD_R:
 237         case RT1308_EFUSE_READ_PVDD_PTBL:
 238         case RT1308_EFUSE_READ_DEV:
 239         case RT1308_EFUSE_READ_R0:
 240         case RT1308_EFUSE_READ_ADC_L:
 241         case RT1308_EFUSE_READ_ADC_R:
 242         case RT1308_EFUSE_READ_ADC_PBTL:
 243         case RT1308_EFUSE_RESERVE:
 244         case RT1308_EFUSE_DATA_0_MSB:
 245         case RT1308_EFUSE_DATA_0_LSB:
 246         case RT1308_EFUSE_DATA_1_MSB:
 247         case RT1308_EFUSE_DATA_1_LSB:
 248         case RT1308_EFUSE_DATA_2_MSB:
 249         case RT1308_EFUSE_DATA_2_LSB:
 250         case RT1308_EFUSE_DATA_3_MSB:
 251         case RT1308_EFUSE_DATA_3_LSB:
 252         case RT1308_EFUSE_STATUS_1:
 253         case RT1308_EFUSE_STATUS_2:
 254         case RT1308_DUMMY_REG:
 255                 return true;
 256         default:
 257                 return false;
 258         }
 259 }
 260
 261 static bool rt1308_readable_register(struct device *dev, unsigned int reg)
 262 {
 263         switch (reg) {
 264         case RT1308_RESET:
 265         case RT1308_RESET_N:
 266         case RT1308_CLK_GATING ... RT1308_DC_DET_THRES:
 267         case RT1308_DAC_SET ... RT1308_AD_FILTER_SET:
 268         case RT1308_DC_CAL_1 ... RT1308_POWER_INT:
 269         case RT1308_SINE_TONE_GEN_1:
 270         case RT1308_SINE_TONE_GEN_2:
 271         case RT1308_BQ_SET:
 272         case RT1308_BQ_PARA_UPDATE:
 273         case RT1308_BQ_PRE_VOL_L ... RT1308_BQ_POST_VOL_R:
 274         case RT1308_BQ1_L_H0 ... RT1308_BQ2_R_A2:
 275         case RT1308_VEN_DEV_ID:
 276         case RT1308_VERSION_ID:
 277         case RT1308_SPK_BOUND:
 278         case RT1308_BQ1_EQ_L_1 ... RT1308_BQ2_EQ_R_3:
 279         case RT1308_EFUSE_1 ... RT1308_EFUSE_RESERVE:
 280         case RT1308_PADS_1:
 281         case RT1308_PADS_2:
 282         case RT1308_TEST_MODE:
 283         case RT1308_TEST_1:
 284         case RT1308_TEST_2:
 285         case RT1308_TEST_3:
 286         case RT1308_TEST_4:
 287         case RT1308_EFUSE_DATA_0_MSB ... RT1308_EFUSE_STATUS_2:
 288         case RT1308_TCON_1:
 289         case RT1308_TCON_2:
 290         case RT1308_DUMMY_REG:
 291         case RT1308_MAX_REG:
 292                 return true;
 293         default:
 294                 return false;
 295         }
 296 }
 297
 298 static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
 299         struct snd_kcontrol *kcontrol, int event)
 300 {
 301         struct snd_soc_component *component =
 302                 snd_soc_dapm_to_component(w->dapm);
 303
 304         switch (event) {
 305         case SND_SOC_DAPM_POST_PMU:
 306                 msleep(30);
 307                 snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
 308                         RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT,
 309                         RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT);
 310                 msleep(40);
 311                 break;
 312         case SND_SOC_DAPM_PRE_PMD:
 313                 snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
 314                         RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT, 0);
 315                 usleep_range(150000, 200000);
 316                 break;
 317
 318         default:
 319                 break;
 320         }
 321
 322         return 0;
 323 }
 324
 325 static const char * const rt1308_rx_data_ch_select[] = {
 326         "LR",
 327         "LL",
 328         "RL",
 329         "RR",
 330 };
 331
 332 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, RT1308_DATA_PATH, 24,
 333         rt1308_rx_data_ch_select);
 334
 335 static const struct snd_kcontrol_new rt1308_snd_controls[] = {
 336
 337         /* I2S Data Channel Selection */
 338         SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
 339 };
 340
 341 static const struct snd_kcontrol_new rt1308_sto_dac_l =
 342         SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
 343                 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
 344
 345 static const struct snd_kcontrol_new rt1308_sto_dac_r =
 346         SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
 347                 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
 348
 349 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
 350         /* Audio Interface */
 351         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
 352
 353         /* Supply Widgets */
 354         SND_SOC_DAPM_SUPPLY("MBIAS20U", RT1308_POWER,
 355                 RT1308_POW_MBIAS20U_BIT, 0, NULL, 0),
 356         SND_SOC_DAPM_SUPPLY("ALDO", RT1308_POWER,
 357                 RT1308_POW_ALDO_BIT, 0, NULL, 0),
 358         SND_SOC_DAPM_SUPPLY("DBG", RT1308_POWER,
 359                 RT1308_POW_DBG_BIT, 0, NULL, 0),
 360         SND_SOC_DAPM_SUPPLY("DACL", RT1308_POWER,
 361                 RT1308_POW_DACL_BIT, 0, NULL, 0),
 362         SND_SOC_DAPM_SUPPLY("CLK25M", RT1308_POWER,
 363                 RT1308_POW_CLK25M_BIT, 0, NULL, 0),
 364         SND_SOC_DAPM_SUPPLY("ADC_R", RT1308_POWER,
 365                 RT1308_POW_ADC_R_BIT, 0, NULL, 0),
 366         SND_SOC_DAPM_SUPPLY("ADC_L", RT1308_POWER,
 367                 RT1308_POW_ADC_L_BIT, 0, NULL, 0),
 368         SND_SOC_DAPM_SUPPLY("DLDO", RT1308_POWER,
 369                 RT1308_POW_DLDO_BIT, 0, NULL, 0),
 370         SND_SOC_DAPM_SUPPLY("VREF", RT1308_POWER,
 371                 RT1308_POW_VREF_BIT, 0, NULL, 0),
 372         SND_SOC_DAPM_SUPPLY("MIXER_R", RT1308_POWER,
 373                 RT1308_POW_MIXER_R_BIT, 0, NULL, 0),
 374         SND_SOC_DAPM_SUPPLY("MIXER_L", RT1308_POWER,
 375                 RT1308_POW_MIXER_L_BIT, 0, NULL, 0),
 376         SND_SOC_DAPM_SUPPLY("MBIAS4U", RT1308_POWER,
 377                 RT1308_POW_MBIAS4U_BIT, 0, NULL, 0),
 378         SND_SOC_DAPM_SUPPLY("PLL2_LDO", RT1308_POWER,
 379                 RT1308_POW_PLL2_LDO_EN_BIT, 0, NULL, 0),
 380         SND_SOC_DAPM_SUPPLY("PLL2B", RT1308_POWER,
 381                 RT1308_POW_PLL2B_EN_BIT, 0, NULL, 0),
 382         SND_SOC_DAPM_SUPPLY("PLL2F", RT1308_POWER,
 383                 RT1308_POW_PLL2F_EN_BIT, 0, NULL, 0),
 384         SND_SOC_DAPM_SUPPLY("PLL2F2", RT1308_POWER,
 385                 RT1308_POW_PLL2F2_EN_BIT, 0, NULL, 0),
 386         SND_SOC_DAPM_SUPPLY("PLL2B2", RT1308_POWER,
 387                 RT1308_POW_PLL2B2_EN_BIT, 0, NULL, 0),
 388
 389         /* Digital Interface */
 390         SND_SOC_DAPM_SUPPLY("DAC Power", RT1308_POWER,
 391                 RT1308_POW_DAC1_BIT, 0, NULL, 0),
 392         SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
 393         SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
 394         SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
 395
 396         /* Output Lines */
 397         SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
 398                 rt1308_classd_event,
 399                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 400         SND_SOC_DAPM_OUTPUT("SPOL"),
 401         SND_SOC_DAPM_OUTPUT("SPOR"),
 402 };
 403
 404 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
 405
 406         { "DAC", NULL, "AIF1RX" },
 407
 408         { "DAC", NULL, "MBIAS20U" },
 409         { "DAC", NULL, "ALDO" },
 410         { "DAC", NULL, "DBG" },
 411         { "DAC", NULL, "DACL" },
 412         { "DAC", NULL, "CLK25M" },
 413         { "DAC", NULL, "ADC_R" },
 414         { "DAC", NULL, "ADC_L" },
 415         { "DAC", NULL, "DLDO" },
 416         { "DAC", NULL, "VREF" },
 417         { "DAC", NULL, "MIXER_R" },
 418         { "DAC", NULL, "MIXER_L" },
 419         { "DAC", NULL, "MBIAS4U" },
 420         { "DAC", NULL, "PLL2_LDO" },
 421         { "DAC", NULL, "PLL2B" },
 422         { "DAC", NULL, "PLL2F" },
 423         { "DAC", NULL, "PLL2F2" },
 424         { "DAC", NULL, "PLL2B2" },
 425
 426         { "DAC L", "Switch", "DAC" },
 427         { "DAC R", "Switch", "DAC" },
 428         { "DAC L", NULL, "DAC Power" },
 429         { "DAC R", NULL, "DAC Power" },
 430
 431         { "CLASS D", NULL, "DAC L" },
 432         { "CLASS D", NULL, "DAC R" },
 433         { "SPOL", NULL, "CLASS D" },
 434         { "SPOR", NULL, "CLASS D" },
 435 };
 436
 437 static int rt1308_get_clk_info(int sclk, int rate)
 438 {
 439         int i;
 440         static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
 441
 442         if (sclk <= 0 || rate <= 0)
 443                 return -EINVAL;
 444
 445         rate = rate << 8;
 446         for (i = 0; i < ARRAY_SIZE(pd); i++)
 447                 if (sclk == rate * pd[i])
 448                         return i;
 449
 450         return -EINVAL;
 451 }
 452
 453 static int rt1308_hw_params(struct snd_pcm_substream *substream,
 454         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 455 {
 456         struct snd_soc_component *component = dai->component;
 457         struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
 458         unsigned int val_len = 0, val_clk, mask_clk;
 459         int pre_div, bclk_ms, frame_size;
 460
 461         rt1308->lrck = params_rate(params);
 462         pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck);
 463         if (pre_div < 0) {
 464                 dev_err(component->dev,
 465                         "Unsupported clock setting %d\n", rt1308->lrck);
 466                 return -EINVAL;
 467         }
 468
 469         frame_size = snd_soc_params_to_frame_size(params);
 470         if (frame_size < 0) {
 471                 dev_err(component->dev, "Unsupported frame size: %d\n",
 472                         frame_size);
 473                 return -EINVAL;
 474         }
 475
 476         bclk_ms = frame_size > 32;
 477         rt1308->bclk = rt1308->lrck * (32 << bclk_ms);
 478
 479         dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
 480                                 bclk_ms, pre_div, dai->id);
 481
 482         dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
 483                                 rt1308->lrck, pre_div, dai->id);
 484
 485         switch (params_width(params)) {
 486         case 16:
 487                 val_len |= RT1308_I2S_DL_SEL_16B;
 488                 break;
 489         case 20:
 490                 val_len |= RT1308_I2S_DL_SEL_20B;
 491                 break;
 492         case 24:
 493                 val_len |= RT1308_I2S_DL_SEL_24B;
 494                 break;
 495         case 8:
 496                 val_len |= RT1308_I2S_DL_SEL_8B;
 497                 break;
 498         default:
 499                 return -EINVAL;
 500         }
 501
 502         switch (dai->id) {
 503         case RT1308_AIF1:
 504                 mask_clk = RT1308_DIV_FS_SYS_MASK;
 505                 val_clk = pre_div << RT1308_DIV_FS_SYS_SFT;
 506                 snd_soc_component_update_bits(component,
 507                         RT1308_I2S_SET_2, RT1308_I2S_DL_SEL_MASK,
 508                         val_len);
 509                 break;
 510         default:
 511                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
 512                 return -EINVAL;
 513         }
 514
 515         snd_soc_component_update_bits(component, RT1308_CLK_1,
 516                 mask_clk, val_clk);
 517
 518         return 0;
 519 }
 520
 521 static int rt1308_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 522 {
 523         struct snd_soc_component *component = dai->component;
 524         struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
 525         unsigned int reg_val = 0, reg1_val = 0;
 526
 527         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 528         case SND_SOC_DAIFMT_CBS_CFS:
 529                 rt1308->master = 0;
 530                 break;
 531         default:
 532                 return -EINVAL;
 533         }
 534
 535         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 536         case SND_SOC_DAIFMT_I2S:
 537                 break;
 538         case SND_SOC_DAIFMT_LEFT_J:
 539                 reg_val |= RT1308_I2S_DF_SEL_LEFT;
 540                 break;
 541         case SND_SOC_DAIFMT_DSP_A:
 542                 reg_val |= RT1308_I2S_DF_SEL_PCM_A;
 543                 break;
 544         case SND_SOC_DAIFMT_DSP_B:
 545                 reg_val |= RT1308_I2S_DF_SEL_PCM_B;
 546                 break;
 547         default:
 548                 return -EINVAL;
 549         }
 550
 551         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 552         case SND_SOC_DAIFMT_NB_NF:
 553                 break;
 554         case SND_SOC_DAIFMT_IB_NF:
 555                 reg1_val |= RT1308_I2S_BCLK_INV;
 556                 break;
 557         default:
 558                 return -EINVAL;
 559         }
 560
 561         switch (dai->id) {
 562         case RT1308_AIF1:
 563                 snd_soc_component_update_bits(component,
 564                         RT1308_I2S_SET_1, RT1308_I2S_DF_SEL_MASK,
 565                         reg_val);
 566                 snd_soc_component_update_bits(component,
 567                         RT1308_I2S_SET_2, RT1308_I2S_BCLK_MASK,
 568                         reg1_val);
 569                 break;
 570         default:
 571                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
 572                 return -EINVAL;
 573         }
 574         return 0;
 575 }
 576
 577 static int rt1308_set_component_sysclk(struct snd_soc_component *component,
 578                 int clk_id, int source, unsigned int freq, int dir)
 579 {
 580         struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
 581         unsigned int reg_val = 0;
 582
 583         if (freq == rt1308->sysclk && clk_id == rt1308->sysclk_src)
 584                 return 0;
 585
 586         switch (clk_id) {
 587         case RT1308_FS_SYS_S_MCLK:
 588                 reg_val |= RT1308_SEL_FS_SYS_SRC_MCLK;
 589                 snd_soc_component_update_bits(component,
 590                         RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
 591                         RT1308_MCLK_DET_EN);
 592                 break;
 593         case RT1308_FS_SYS_S_BCLK:
 594                 reg_val |= RT1308_SEL_FS_SYS_SRC_BCLK;
 595                 break;
 596         case RT1308_FS_SYS_S_PLL:
 597                 reg_val |= RT1308_SEL_FS_SYS_SRC_PLL;
 598                 break;
 599         case RT1308_FS_SYS_S_RCCLK:
 600                 reg_val |= RT1308_SEL_FS_SYS_SRC_RCCLK;
 601                 break;
 602         default:
 603                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
 604                 return -EINVAL;
 605         }
 606         snd_soc_component_update_bits(component, RT1308_CLK_1,
 607                 RT1308_SEL_FS_SYS_MASK, reg_val);
 608         rt1308->sysclk = freq;
 609         rt1308->sysclk_src = clk_id;
 610
 611         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
 612                 freq, clk_id);
 613
 614         return 0;
 615 }
 616
 617 static int rt1308_set_component_pll(struct snd_soc_component *component,
 618                 int pll_id, int source, unsigned int freq_in,
 619                 unsigned int freq_out)
 620 {
 621         struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
 622         struct rl6231_pll_code pll_code;
 623         int ret;
 624
 625         if (source == rt1308->pll_src && freq_in == rt1308->pll_in &&
 626             freq_out == rt1308->pll_out)
 627                 return 0;
 628
 629         if (!freq_in || !freq_out) {
 630                 dev_dbg(component->dev, "PLL disabled\n");
 631
 632                 rt1308->pll_in = 0;
 633                 rt1308->pll_out = 0;
 634                 snd_soc_component_update_bits(component,
 635                         RT1308_CLK_1, RT1308_SEL_FS_SYS_MASK,
 636                         RT1308_SEL_FS_SYS_SRC_MCLK);
 637                 return 0;
 638         }
 639
 640         switch (source) {
 641         case RT1308_PLL_S_MCLK:
 642                 snd_soc_component_update_bits(component,
 643                         RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
 644                         RT1308_SEL_PLL_SRC_MCLK);
 645                 snd_soc_component_update_bits(component,
 646                         RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
 647                         RT1308_MCLK_DET_EN);
 648                 break;
 649         case RT1308_PLL_S_BCLK:
 650                 snd_soc_component_update_bits(component,
 651                         RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
 652                         RT1308_SEL_PLL_SRC_BCLK);
 653                 break;
 654         case RT1308_PLL_S_RCCLK:
 655                 snd_soc_component_update_bits(component,
 656                         RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
 657                         RT1308_SEL_PLL_SRC_RCCLK);
 658                 freq_in = 25000000;
 659                 break;
 660         default:
 661                 dev_err(component->dev, "Unknown PLL Source %d\n", source);
 662                 return -EINVAL;
 663         }
 664
 665         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
 666         if (ret < 0) {
 667                 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
 668                 return ret;
 669         }
 670
 671         dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
 672                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
 673                 pll_code.n_code, pll_code.k_code);
 674
 675         snd_soc_component_write(component, RT1308_PLL_1,
 676                 pll_code.k_code << RT1308_PLL1_K_SFT |
 677                 pll_code.m_bp << RT1308_PLL1_M_BYPASS_SFT |
 678                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1308_PLL1_M_SFT |
 679                 pll_code.n_code << RT1308_PLL1_N_SFT);
 680
 681         rt1308->pll_in = freq_in;
 682         rt1308->pll_out = freq_out;
 683         rt1308->pll_src = source;
 684
 685         return 0;
 686 }
 687
 688 static int rt1308_probe(struct snd_soc_component *component)
 689 {
 690         struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
 691
 692         rt1308->component = component;
 693
 694         return rt1308_reg_init(component);
 695 }
 696
 697 static void rt1308_remove(struct snd_soc_component *component)
 698 {
 699         struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
 700
 701         regmap_write(rt1308->regmap, RT1308_RESET, 0);
 702 }
 703
 704 #ifdef CONFIG_PM
 705 static int rt1308_suspend(struct snd_soc_component *component)
 706 {
 707         struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
 708
 709         regcache_cache_only(rt1308->regmap, true);
 710         regcache_mark_dirty(rt1308->regmap);
 711
 712         return 0;
 713 }
 714
 715 static int rt1308_resume(struct snd_soc_component *component)
 716 {
 717         struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
 718
 719         regcache_cache_only(rt1308->regmap, false);
 720         regcache_sync(rt1308->regmap);
 721
 722         return 0;
 723 }
 724 #else
 725 #define rt1308_suspend NULL
 726 #define rt1308_resume NULL
 727 #endif
 728
 729 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
 730 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
 731                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
 732                         SNDRV_PCM_FMTBIT_S24_LE)
 733
 734 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
 735         .hw_params = rt1308_hw_params,
 736         .set_fmt = rt1308_set_dai_fmt,
 737 };
 738
 739 static struct snd_soc_dai_driver rt1308_dai[] = {
 740         {
 741                 .name = "rt1308-aif",
 742                 .playback = {
 743                         .stream_name = "AIF1 Playback",
 744                         .channels_min = 1,
 745                         .channels_max = 2,
 746                         .rates = RT1308_STEREO_RATES,
 747                         .formats = RT1308_FORMATS,
 748                 },
 749                 .ops = &rt1308_aif_dai_ops,
 750         },
 751 };
 752
 753 static const struct snd_soc_component_driver soc_component_dev_rt1308 = {
 754         .probe = rt1308_probe,
 755         .remove = rt1308_remove,
 756         .suspend = rt1308_suspend,
 757         .resume = rt1308_resume,
 758         .controls = rt1308_snd_controls,
 759         .num_controls = ARRAY_SIZE(rt1308_snd_controls),
 760         .dapm_widgets = rt1308_dapm_widgets,
 761         .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
 762         .dapm_routes = rt1308_dapm_routes,
 763         .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
 764         .set_sysclk = rt1308_set_component_sysclk,
 765         .set_pll = rt1308_set_component_pll,
 766         .use_pmdown_time        = 1,
 767         .endianness             = 1,
 768         .non_legacy_dai_naming  = 1,
 769 };
 770
 771 static const struct regmap_config rt1308_regmap = {
 772         .reg_bits = 8,
 773         .val_bits = 32,
 774         .max_register = RT1308_MAX_REG,
 775         .volatile_reg = rt1308_volatile_register,
 776         .readable_reg = rt1308_readable_register,
 777         .cache_type = REGCACHE_RBTREE,
 778         .reg_defaults = rt1308_reg,
 779         .num_reg_defaults = ARRAY_SIZE(rt1308_reg),
 780         .use_single_read = true,
 781         .use_single_write = true,
 782 };
 783
 784 #ifdef CONFIG_OF
 785 static const struct of_device_id rt1308_of_match[] = {
 786         { .compatible = "realtek,rt1308", },
 787         { },
 788 };
 789 MODULE_DEVICE_TABLE(of, rt1308_of_match);
 790 #endif
 791
 792 #ifdef CONFIG_ACPI
 793 static struct acpi_device_id rt1308_acpi_match[] = {
 794         { "10EC1308", 0, },
 795         { },
 796 };
 797 MODULE_DEVICE_TABLE(acpi, rt1308_acpi_match);
 798 #endif
 799
 800 static const struct i2c_device_id rt1308_i2c_id[] = {
 801         { "rt1308", 0 },
 802         { }
 803 };
 804 MODULE_DEVICE_TABLE(i2c, rt1308_i2c_id);
 805
 806 static void rt1308_efuse(struct rt1308_priv *rt1308)
 807 {
 808         regmap_write(rt1308->regmap, RT1308_RESET, 0);
 809
 810         regmap_write(rt1308->regmap, RT1308_POWER_STATUS, 0x01800000);
 811         msleep(100);
 812         regmap_write(rt1308->regmap, RT1308_EFUSE_1, 0x44fe0f00);
 813         msleep(20);
 814         regmap_write(rt1308->regmap, RT1308_PVDD_OFFSET_CTL, 0x10000000);
 815 }
 816
 817 static int rt1308_i2c_probe(struct i2c_client *i2c,
 818                     const struct i2c_device_id *id)
 819 {
 820         struct rt1308_priv *rt1308;
 821         int ret;
 822         unsigned int val;
 823
 824         rt1308 = devm_kzalloc(&i2c->dev, sizeof(struct rt1308_priv),
 825                                 GFP_KERNEL);
 826         if (rt1308 == NULL)
 827                 return -ENOMEM;
 828
 829         i2c_set_clientdata(i2c, rt1308);
 830
 831         rt1308->regmap = devm_regmap_init_i2c(i2c, &rt1308_regmap);
 832         if (IS_ERR(rt1308->regmap)) {
 833                 ret = PTR_ERR(rt1308->regmap);
 834                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
 835                         ret);
 836                 return ret;
 837         }
 838
 839         regmap_read(rt1308->regmap, RT1308_VEN_DEV_ID, &val);
 840         /* ignore last byte difference */
 841         if ((val & 0xFFFFFF00) != RT1308_DEVICE_ID_NUM) {
 842                 dev_err(&i2c->dev,
 843                         "Device with ID register %x is not rt1308\n", val);
 844                 return -ENODEV;
 845         }
 846
 847         rt1308_efuse(rt1308);
 848
 849         return devm_snd_soc_register_component(&i2c->dev,
 850                         &soc_component_dev_rt1308,
 851                         rt1308_dai, ARRAY_SIZE(rt1308_dai));
 852 }
 853
 854 static void rt1308_i2c_shutdown(struct i2c_client *client)
 855 {
 856         struct rt1308_priv *rt1308 = i2c_get_clientdata(client);
 857
 858         regmap_write(rt1308->regmap, RT1308_RESET, 0);
 859 }
 860
 861 static struct i2c_driver rt1308_i2c_driver = {
 862         .driver = {
 863                 .name = "rt1308",
 864                 .of_match_table = of_match_ptr(rt1308_of_match),
 865                 .acpi_match_table = ACPI_PTR(rt1308_acpi_match),
 866         },
 867         .probe = rt1308_i2c_probe,
 868         .shutdown = rt1308_i2c_shutdown,
 869         .id_table = rt1308_i2c_id,
 870 };
 871 module_i2c_driver(rt1308_i2c_driver);
 872
 873 MODULE_DESCRIPTION("ASoC RT1308 amplifier driver");
 874 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
 875 MODULE_LICENSE("GPL v2");