sound/soc/codecs/tlv320dac33.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   4  *
   5  * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   6  *
   7  * Copyright:   (C) 2009 Nokia Corporation
   8  */
   9
  10 #ifndef __TLV320DAC33_H
  11 #define __TLV320DAC33_H
  12
  13 #define DAC33_PAGE_SELECT               0x00
  14 #define DAC33_PWR_CTRL                  0x01
  15 #define DAC33_PLL_CTRL_A                0x02
  16 #define DAC33_PLL_CTRL_B                0x03
  17 #define DAC33_PLL_CTRL_C                0x04
  18 #define DAC33_PLL_CTRL_D                0x05
  19 #define DAC33_PLL_CTRL_E                0x06
  20 #define DAC33_INT_OSC_CTRL              0x07
  21 #define DAC33_INT_OSC_FREQ_RAT_A        0x08
  22 #define DAC33_INT_OSC_FREQ_RAT_B        0x09
  23 #define DAC33_INT_OSC_DAC_RATIO_SET     0x0A
  24 #define DAC33_CALIB_TIME                0x0B
  25 #define DAC33_INT_OSC_CTRL_B            0x0C
  26 #define DAC33_INT_OSC_CTRL_C            0x0D
  27 #define DAC33_INT_OSC_STATUS            0x0E
  28 #define DAC33_INT_OSC_DAC_RATIO_READ    0x0F
  29 #define DAC33_INT_OSC_FREQ_RAT_READ_A   0x10
  30 #define DAC33_INT_OSC_FREQ_RAT_READ_B   0x11
  31 #define DAC33_SER_AUDIOIF_CTRL_A        0x12
  32 #define DAC33_SER_AUDIOIF_CTRL_B        0x13
  33 #define DAC33_SER_AUDIOIF_CTRL_C        0x14
  34 #define DAC33_FIFO_CTRL_A               0x15
  35 #define DAC33_UTHR_MSB                  0x16
  36 #define DAC33_UTHR_LSB                  0x17
  37 #define DAC33_ATHR_MSB                  0x18
  38 #define DAC33_ATHR_LSB                  0x19
  39 #define DAC33_LTHR_MSB                  0x1A
  40 #define DAC33_LTHR_LSB                  0x1B
  41 #define DAC33_PREFILL_MSB               0x1C
  42 #define DAC33_PREFILL_LSB               0x1D
  43 #define DAC33_NSAMPLE_MSB               0x1E
  44 #define DAC33_NSAMPLE_LSB               0x1F
  45 #define DAC33_FIFO_WPTR_MSB             0x20
  46 #define DAC33_FIFO_WPTR_LSB             0x21
  47 #define DAC33_FIFO_RPTR_MSB             0x22
  48 #define DAC33_FIFO_RPTR_LSB             0x23
  49 #define DAC33_FIFO_DEPTH_MSB            0x24
  50 #define DAC33_FIFO_DEPTH_LSB            0x25
  51 #define DAC33_SAMPLES_REMAINING_MSB     0x26
  52 #define DAC33_SAMPLES_REMAINING_LSB     0x27
  53 #define DAC33_FIFO_IRQ_FLAG             0x28
  54 #define DAC33_FIFO_IRQ_MASK             0x29
  55 #define DAC33_FIFO_IRQ_MODE_A           0x2A
  56 #define DAC33_FIFO_IRQ_MODE_B           0x2B
  57 #define DAC33_DAC_CTRL_A                0x2C
  58 #define DAC33_DAC_CTRL_B                0x2D
  59 #define DAC33_DAC_CTRL_C                0x2E
  60 #define DAC33_LDAC_DIG_VOL_CTRL         0x2F
  61 #define DAC33_RDAC_DIG_VOL_CTRL         0x30
  62 #define DAC33_DAC_STATUS_FLAGS          0x31
  63 #define DAC33_ASRC_CTRL_A               0x32
  64 #define DAC33_ASRC_CTRL_B               0x33
  65 #define DAC33_SRC_REF_CLK_RATIO_A       0x34
  66 #define DAC33_SRC_REF_CLK_RATIO_B       0x35
  67 #define DAC33_SRC_EST_REF_CLK_RATIO_A   0x36
  68 #define DAC33_SRC_EST_REF_CLK_RATIO_B   0x37
  69 #define DAC33_INTP_CTRL_A               0x38
  70 #define DAC33_INTP_CTRL_B               0x39
  71 /* Registers 0x3A - 0x3F Reserved */
  72 #define DAC33_LDAC_PWR_CTRL             0x40
  73 #define DAC33_RDAC_PWR_CTRL             0x41
  74 #define DAC33_OUT_AMP_CM_CTRL           0x42
  75 #define DAC33_OUT_AMP_PWR_CTRL          0x43
  76 #define DAC33_OUT_AMP_CTRL              0x44
  77 #define DAC33_LINEL_TO_LLO_VOL          0x45
  78 /* Registers 0x45 - 0x47 Reserved */
  79 #define DAC33_LINER_TO_RLO_VOL          0x48
  80 #define DAC33_ANA_VOL_SOFT_STEP_CTRL    0x49
  81 #define DAC33_OSC_TRIM                  0x4A
  82 /* Registers 0x4B - 0x7C Reserved */
  83 #define DAC33_DEVICE_ID_MSB             0x7D
  84 #define DAC33_DEVICE_ID_LSB             0x7E
  85 #define DAC33_DEVICE_REV_ID             0x7F
  86
  87 #define DAC33_CACHEREGNUM               128
  88
  89 /* Bit definitions */
  90
  91 /* DAC33_PWR_CTRL (0x01) */
  92 #define DAC33_DACRPDNB                  (0x01 << 0)
  93 #define DAC33_DACLPDNB                  (0x01 << 1)
  94 #define DAC33_OSCPDNB                   (0x01 << 2)
  95 #define DAC33_PLLPDNB                   (0x01 << 3)
  96 #define DAC33_PDNALLB                   (0x01 << 4)
  97 #define DAC33_SOFT_RESET                (0x01 << 7)
  98
  99 /* DAC33_INT_OSC_CTRL (0x07) */
 100 #define DAC33_REFSEL                    (0x01 << 1)
 101
 102 /* DAC33_INT_OSC_CTRL_B (0x0C) */
 103 #define DAC33_ADJSTEP(x)                (x << 0)
 104 #define DAC33_ADJTHRSHLD(x)             (x << 4)
 105
 106 /* DAC33_INT_OSC_CTRL_C (0x0D) */
 107 #define DAC33_REFDIV(x)                 (x << 4)
 108
 109 /* DAC33_INT_OSC_STATUS (0x0E) */
 110 #define DAC33_OSCSTATUS_IDLE_CALIB      (0x00)
 111 #define DAC33_OSCSTATUS_NORMAL          (0x01)
 112 #define DAC33_OSCSTATUS_ADJUSTMENT      (0x03)
 113 #define DAC33_OSCSTATUS_NOT_USED        (0x02)
 114
 115 /* DAC33_SER_AUDIOIF_CTRL_A (0x12) */
 116 #define DAC33_MSWCLK                    (0x01 << 0)
 117 #define DAC33_MSBCLK                    (0x01 << 1)
 118 #define DAC33_AFMT_MASK                 (0x03 << 2)
 119 #define DAC33_AFMT_I2S                  (0x00 << 2)
 120 #define DAC33_AFMT_DSP                  (0x01 << 2)
 121 #define DAC33_AFMT_RIGHT_J              (0x02 << 2)
 122 #define DAC33_AFMT_LEFT_J               (0x03 << 2)
 123 #define DAC33_WLEN_MASK                 (0x03 << 4)
 124 #define DAC33_WLEN_16                   (0x00 << 4)
 125 #define DAC33_WLEN_20                   (0x01 << 4)
 126 #define DAC33_WLEN_24                   (0x02 << 4)
 127 #define DAC33_WLEN_32                   (0x03 << 4)
 128 #define DAC33_NCYCL_MASK                (0x03 << 6)
 129 #define DAC33_NCYCL_16                  (0x00 << 6)
 130 #define DAC33_NCYCL_20                  (0x01 << 6)
 131 #define DAC33_NCYCL_24                  (0x02 << 6)
 132 #define DAC33_NCYCL_32                  (0x03 << 6)
 133
 134 /* DAC33_SER_AUDIOIF_CTRL_B (0x13) */
 135 #define DAC33_DATA_DELAY_MASK           (0x03 << 2)
 136 #define DAC33_DATA_DELAY(x)             (x << 2)
 137 #define DAC33_BCLKON                    (0x01 << 5)
 138
 139 /* DAC33_FIFO_CTRL_A (0x15) */
 140 #define DAC33_WIDTH                             (0x01 << 0)
 141 #define DAC33_FBYPAS                            (0x01 << 1)
 142 #define DAC33_FAUTO                             (0x01 << 2)
 143 #define DAC33_FIFOFLUSH                 (0x01 << 3)
 144
 145 /*
 146  * UTHR, ATHR, LTHR, PREFILL, NSAMPLE (0x16 - 0x1F)
 147  * 13-bit values
 148 */
 149 #define DAC33_THRREG(x)                 (((x) & 0x1FFF) << 3)
 150
 151 /* DAC33_FIFO_IRQ_MASK (0x29) */
 152 #define DAC33_MNS                       (0x01 << 0)
 153 #define DAC33_MPS                       (0x01 << 1)
 154 #define DAC33_MAT                       (0x01 << 2)
 155 #define DAC33_MLT                       (0x01 << 3)
 156 #define DAC33_MUT                       (0x01 << 4)
 157 #define DAC33_MUF                       (0x01 << 5)
 158 #define DAC33_MOF                       (0x01 << 6)
 159
 160 #define DAC33_FIFO_IRQ_MODE_MASK        (0x03)
 161 #define DAC33_FIFO_IRQ_MODE_RISING      (0x00)
 162 #define DAC33_FIFO_IRQ_MODE_FALLING     (0x01)
 163 #define DAC33_FIFO_IRQ_MODE_LEVEL       (0x02)
 164 #define DAC33_FIFO_IRQ_MODE_EDGE        (0x03)
 165
 166 /* DAC33_FIFO_IRQ_MODE_A (0x2A) */
 167 #define DAC33_UTM(x)                    (x << 0)
 168 #define DAC33_UFM(x)                    (x << 2)
 169 #define DAC33_OFM(x)                    (x << 4)
 170
 171 /* DAC33_FIFO_IRQ_MODE_B (0x2B) */
 172 #define DAC33_NSM(x)                    (x << 0)
 173 #define DAC33_PSM(x)                    (x << 2)
 174 #define DAC33_ATM(x)                    (x << 4)
 175 #define DAC33_LTM(x)                    (x << 6)
 176
 177 /* DAC33_DAC_CTRL_A (0x2C) */
 178 #define DAC33_DACRATE(x)                (x << 0)
 179 #define DAC33_DACDUAL                   (0x01 << 4)
 180 #define DAC33_DACLKSEL_MASK             (0x03 << 5)
 181 #define DAC33_DACLKSEL_INTSOC           (0x00 << 5)
 182 #define DAC33_DACLKSEL_PLL              (0x01 << 5)
 183 #define DAC33_DACLKSEL_MCLK             (0x02 << 5)
 184 #define DAC33_DACLKSEL_BCLK             (0x03 << 5)
 185
 186 /* DAC33_DAC_CTRL_B (0x2D) */
 187 #define DAC33_DACSRCR_MASK              (0x03 << 0)
 188 #define DAC33_DACSRCR_MUTE              (0x00 << 0)
 189 #define DAC33_DACSRCR_RIGHT             (0x01 << 0)
 190 #define DAC33_DACSRCR_LEFT              (0x02 << 0)
 191 #define DAC33_DACSRCR_MONOMIX           (0x03 << 0)
 192 #define DAC33_DACSRCL_MASK              (0x03 << 2)
 193 #define DAC33_DACSRCL_MUTE              (0x00 << 2)
 194 #define DAC33_DACSRCL_LEFT              (0x01 << 2)
 195 #define DAC33_DACSRCL_RIGHT             (0x02 << 2)
 196 #define DAC33_DACSRCL_MONOMIX           (0x03 << 2)
 197 #define DAC33_DVOLSTEP_MASK             (0x03 << 4)
 198 #define DAC33_DVOLSTEP_SS_PERFS         (0x00 << 4)
 199 #define DAC33_DVOLSTEP_SS_PER2FS        (0x01 << 4)
 200 #define DAC33_DVOLSTEP_SS_DISABLED      (0x02 << 4)
 201 #define DAC33_DVOLCTRL_MASK             (0x03 << 6)
 202 #define DAC33_DVOLCTRL_LR_INDEPENDENT1  (0x00 << 6)
 203 #define DAC33_DVOLCTRL_LR_RIGHT_CONTROL (0x01 << 6)
 204 #define DAC33_DVOLCTRL_LR_LEFT_CONTROL  (0x02 << 6)
 205 #define DAC33_DVOLCTRL_LR_INDEPENDENT2  (0x03 << 6)
 206
 207 /* DAC33_DAC_CTRL_C (0x2E) */
 208 #define DAC33_DEEMENR                   (0x01 << 0)
 209 #define DAC33_EFFENR                    (0x01 << 1)
 210 #define DAC33_DEEMENL                   (0x01 << 2)
 211 #define DAC33_EFFENL                    (0x01 << 3)
 212 #define DAC33_EN3D                      (0x01 << 4)
 213 #define DAC33_RESYNMUTE                 (0x01 << 5)
 214 #define DAC33_RESYNEN                   (0x01 << 6)
 215
 216 /* DAC33_ASRC_CTRL_A (0x32) */
 217 #define DAC33_SRCBYP                    (0x01 << 0)
 218 #define DAC33_SRCLKSEL_MASK             (0x03 << 1)
 219 #define DAC33_SRCLKSEL_INTSOC           (0x00 << 1)
 220 #define DAC33_SRCLKSEL_PLL              (0x01 << 1)
 221 #define DAC33_SRCLKSEL_MCLK             (0x02 << 1)
 222 #define DAC33_SRCLKSEL_BCLK             (0x03 << 1)
 223 #define DAC33_SRCLKDIV(x)               (x << 3)
 224
 225 /* DAC33_ASRC_CTRL_B (0x33) */
 226 #define DAC33_SRCSETUP(x)               (x << 0)
 227 #define DAC33_SRCREFSEL                 (0x01 << 4)
 228 #define DAC33_SRCREFDIV(x)              (x << 5)
 229
 230 /* DAC33_INTP_CTRL_A (0x38) */
 231 #define DAC33_INTPSEL                   (0x01 << 0)
 232 #define DAC33_INTPM_MASK                (0x03 << 1)
 233 #define DAC33_INTPM_ALOW_OPENDRAIN      (0x00 << 1)
 234 #define DAC33_INTPM_ALOW                (0x01 << 1)
 235 #define DAC33_INTPM_AHIGH               (0x02 << 1)
 236
 237 /* DAC33_LDAC_PWR_CTRL (0x40) */
 238 /* DAC33_RDAC_PWR_CTRL (0x41) */
 239 #define DAC33_DACLRNUM                  (0x01 << 2)
 240 #define DAC33_LROUT_GAIN(x)             (x << 0)
 241
 242 /* DAC33_ANA_VOL_SOFT_STEP_CTRL (0x49) */
 243 #define DAC33_VOLCLKSEL                 (0x01 << 0)
 244 #define DAC33_VOLCLKEN                  (0x01 << 1)
 245 #define DAC33_VOLBYPASS                 (0x01 << 2)
 246
 247 #define TLV320DAC33_MCLK                0
 248 #define TLV320DAC33_SLEEPCLK            1
 249
 250 #endif /* __TLV320DAC33_H */