?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / sound / soc / codecs / wcd934x.c
blob158e878abd6c7df52f8a5dfa9cb079d9be4222b9
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
3
4 #include <linux/clk.h>
5 #include <linux/clk-provider.h>
6 #include <linux/gpio.h>
7 #include <linux/interrupt.h>
8 #include <linux/kernel.h>
9 #include <linux/mfd/wcd934x/registers.h>
10 #include <linux/mfd/wcd934x/wcd934x.h>
11 #include <linux/module.h>
12 #include <linux/mutex.h>
13 #include <linux/of_clk.h>
14 #include <linux/of_device.h>
15 #include <linux/of_gpio.h>
16 #include <linux/of.h>
17 #include <linux/of_irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <linux/slimbus.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/tlv.h>
27 #include "wcd-clsh-v2.h"
28
29 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
30 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
31 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
32 /* Fractional Rates */
33 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
34 SNDRV_PCM_RATE_176400)
35 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
36 SNDRV_PCM_FMTBIT_S24_LE)
37
38 /* slave port water mark level
39 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
40 */
41 #define SLAVE_PORT_WATER_MARK_6BYTES 0
42 #define SLAVE_PORT_WATER_MARK_9BYTES 1
43 #define SLAVE_PORT_WATER_MARK_12BYTES 2
44 #define SLAVE_PORT_WATER_MARK_15BYTES 3
45 #define SLAVE_PORT_WATER_MARK_SHIFT 1
46 #define SLAVE_PORT_ENABLE 1
47 #define SLAVE_PORT_DISABLE 0
48 #define WCD934X_SLIM_WATER_MARK_VAL \
49 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
50 (SLAVE_PORT_ENABLE))
51
52 #define WCD934X_SLIM_NUM_PORT_REG 3
53 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
54 #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0)
55 #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1)
56 #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2)
57
58 #define WCD934X_MCLK_CLK_12P288MHZ 12288000
59 #define WCD934X_MCLK_CLK_9P6MHZ 9600000
60
61 /* Only valid for 9.6 MHz mclk */
62 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
63 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
64
65 /* Only valid for 12.288 MHz mclk */
66 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
67
68 #define WCD934X_DMIC_CLK_DIV_2 0x0
69 #define WCD934X_DMIC_CLK_DIV_3 0x1
70 #define WCD934X_DMIC_CLK_DIV_4 0x2
71 #define WCD934X_DMIC_CLK_DIV_6 0x3
72 #define WCD934X_DMIC_CLK_DIV_8 0x4
73 #define WCD934X_DMIC_CLK_DIV_16 0x5
74 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
75
76 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
77 #define CF_MIN_3DB_4HZ 0x0
78 #define CF_MIN_3DB_75HZ 0x1
79 #define CF_MIN_3DB_150HZ 0x2
80
81 #define WCD934X_RX_START 16
82 #define WCD934X_NUM_INTERPOLATORS 9
83 #define WCD934X_RX_PATH_CTL_OFFSET 20
84 #define WCD934X_MAX_VALID_ADC_MUX 13
85 #define WCD934X_INVALID_ADC_MUX 9
86
87 #define WCD934X_SLIM_RX_CH(p) \
88 {.port = p + WCD934X_RX_START, .shift = p,}
89
90 #define WCD934X_SLIM_TX_CH(p) \
91 {.port = p, .shift = p,}
92
93 /* Feature masks to distinguish codec version */
94 #define DSD_DISABLED_MASK 0
95 #define SLNQ_DISABLED_MASK 1
96
97 #define DSD_DISABLED BIT(DSD_DISABLED_MASK)
98 #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK)
99
100 /* As fine version info cannot be retrieved before wcd probe.
101 * Define three coarse versions for possible future use before wcd probe.
102 */
103 #define WCD_VERSION_WCD9340_1_0 0x400
104 #define WCD_VERSION_WCD9341_1_0 0x410
105 #define WCD_VERSION_WCD9340_1_1 0x401
106 #define WCD_VERSION_WCD9341_1_1 0x411
107 #define WCD934X_AMIC_PWR_LEVEL_LP 0
108 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1
109 #define WCD934X_AMIC_PWR_LEVEL_HP 2
110 #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3
111 #define WCD934X_AMIC_PWR_LVL_MASK 0x60
112 #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5
113
114 #define WCD934X_DEC_PWR_LVL_MASK 0x06
115 #define WCD934X_DEC_PWR_LVL_LP 0x02
116 #define WCD934X_DEC_PWR_LVL_HP 0x04
117 #define WCD934X_DEC_PWR_LVL_DF 0x00
118 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
119
120 #define WCD934X_DEF_MICBIAS_MV 1800
121 #define WCD934X_MAX_MICBIAS_MV 2850
122
123 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
124
125 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
126 { \
127 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
128 .info = wcd934x_iir_filter_info, \
129 .get = wcd934x_get_iir_band_audio_mixer, \
130 .put = wcd934x_put_iir_band_audio_mixer, \
131 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
132 .iir_idx = iidx, \
133 .band_idx = bidx, \
134 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
135 } \
136 }
137
138 #define WCD934X_INTERPOLATOR_PATH(id) \
139 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
140 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
141 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
142 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
143 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
144 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
145 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
146 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
147 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \
148 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
149 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
150 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
151 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
152 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
153 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
154 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
155 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
156 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
157 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \
158 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
159 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
160 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
161 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
162 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
163 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
164 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
165 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
166 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
167 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \
168 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
169 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
170 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
171 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
172 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
173 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
174 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
175 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
176 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
177 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
178 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
179 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
180 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
181 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
182 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \
183 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \
184 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \
185 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
186 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \
187 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
188
189 #define WCD934X_INTERPOLATOR_MIX2(id) \
190 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
191 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
192
193 #define WCD934X_SLIM_RX_AIF_PATH(id) \
194 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
195 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
196 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
197 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \
198 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
199
200 #define WCD934X_ADC_MUX(id) \
201 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \
202 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \
203 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
204 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
205 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
206 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
207 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
208 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
209 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
210 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
211 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
212 {"AMIC MUX" #id, "ADC4", "ADC4"}
213
214 #define WCD934X_IIR_INP_MUX(id) \
215 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \
216 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \
217 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \
218 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \
219 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \
220 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \
221 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \
222 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \
223 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \
224 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \
225 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
226 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
227 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
228 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
229 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
230 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
231 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
232 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
233 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \
234 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \
235 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \
236 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \
237 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \
238 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \
239 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \
240 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \
241 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \
242 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \
243 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
244 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
245 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
246 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
247 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
248 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
249 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
250 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
251 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \
252 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \
253 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \
254 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \
255 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \
256 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \
257 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \
258 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \
259 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \
260 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \
261 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
262 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
263 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
264 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
265 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
266 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
267 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
268 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
269 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \
270 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \
271 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \
272 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \
273 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \
274 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \
275 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \
276 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \
277 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \
278 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \
279 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
280 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
281 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
282 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
283 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
284 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
285 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
286 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
287
288 #define WCD934X_SLIM_TX_AIF_PATH(id) \
289 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
290 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
291 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
292 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
293
294 enum {
295 MIC_BIAS_1 = 1,
296 MIC_BIAS_2,
297 MIC_BIAS_3,
298 MIC_BIAS_4
299 };
300
301 enum {
302 SIDO_SOURCE_INTERNAL,
303 SIDO_SOURCE_RCO_BG,
304 };
305
306 enum {
307 INTERP_EAR = 0,
308 INTERP_HPHL,
309 INTERP_HPHR,
310 INTERP_LO1,
311 INTERP_LO2,
312 INTERP_LO3_NA, /* LO3 not avalible in Tavil */
313 INTERP_LO4_NA,
314 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
315 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
316 INTERP_MAX,
317 };
318
319 enum {
320 WCD934X_RX0 = 0,
321 WCD934X_RX1,
322 WCD934X_RX2,
323 WCD934X_RX3,
324 WCD934X_RX4,
325 WCD934X_RX5,
326 WCD934X_RX6,
327 WCD934X_RX7,
328 WCD934X_RX8,
329 WCD934X_RX9,
330 WCD934X_RX10,
331 WCD934X_RX11,
332 WCD934X_RX12,
333 WCD934X_RX_MAX,
334 };
335
336 enum {
337 WCD934X_TX0 = 0,
338 WCD934X_TX1,
339 WCD934X_TX2,
340 WCD934X_TX3,
341 WCD934X_TX4,
342 WCD934X_TX5,
343 WCD934X_TX6,
344 WCD934X_TX7,
345 WCD934X_TX8,
346 WCD934X_TX9,
347 WCD934X_TX10,
348 WCD934X_TX11,
349 WCD934X_TX12,
350 WCD934X_TX13,
351 WCD934X_TX14,
352 WCD934X_TX15,
353 WCD934X_TX_MAX,
354 };
355
356 struct wcd934x_slim_ch {
357 u32 ch_num;
358 u16 port;
359 u16 shift;
360 struct list_head list;
361 };
362
363 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
364 WCD934X_SLIM_TX_CH(0),
365 WCD934X_SLIM_TX_CH(1),
366 WCD934X_SLIM_TX_CH(2),
367 WCD934X_SLIM_TX_CH(3),
368 WCD934X_SLIM_TX_CH(4),
369 WCD934X_SLIM_TX_CH(5),
370 WCD934X_SLIM_TX_CH(6),
371 WCD934X_SLIM_TX_CH(7),
372 WCD934X_SLIM_TX_CH(8),
373 WCD934X_SLIM_TX_CH(9),
374 WCD934X_SLIM_TX_CH(10),
375 WCD934X_SLIM_TX_CH(11),
376 WCD934X_SLIM_TX_CH(12),
377 WCD934X_SLIM_TX_CH(13),
378 WCD934X_SLIM_TX_CH(14),
379 WCD934X_SLIM_TX_CH(15),
380 };
381
382 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
383 WCD934X_SLIM_RX_CH(0), /* 16 */
384 WCD934X_SLIM_RX_CH(1), /* 17 */
385 WCD934X_SLIM_RX_CH(2),
386 WCD934X_SLIM_RX_CH(3),
387 WCD934X_SLIM_RX_CH(4),
388 WCD934X_SLIM_RX_CH(5),
389 WCD934X_SLIM_RX_CH(6),
390 WCD934X_SLIM_RX_CH(7),
391 WCD934X_SLIM_RX_CH(8),
392 WCD934X_SLIM_RX_CH(9),
393 WCD934X_SLIM_RX_CH(10),
394 WCD934X_SLIM_RX_CH(11),
395 WCD934X_SLIM_RX_CH(12),
396 };
397
398 /* Codec supports 2 IIR filters */
399 enum {
400 IIR0 = 0,
401 IIR1,
402 IIR_MAX,
403 };
404
405 /* Each IIR has 5 Filter Stages */
406 enum {
407 BAND1 = 0,
408 BAND2,
409 BAND3,
410 BAND4,
411 BAND5,
412 BAND_MAX,
413 };
414
415 enum {
416 COMPANDER_1, /* HPH_L */
417 COMPANDER_2, /* HPH_R */
418 COMPANDER_3, /* LO1_DIFF */
419 COMPANDER_4, /* LO2_DIFF */
420 COMPANDER_5, /* LO3_SE - not used in Tavil */
421 COMPANDER_6, /* LO4_SE - not used in Tavil */
422 COMPANDER_7, /* SWR SPK CH1 */
423 COMPANDER_8, /* SWR SPK CH2 */
424 COMPANDER_MAX,
425 };
426
427 enum {
428 AIF1_PB = 0,
429 AIF1_CAP,
430 AIF2_PB,
431 AIF2_CAP,
432 AIF3_PB,
433 AIF3_CAP,
434 AIF4_PB,
435 AIF4_VIFEED,
436 AIF4_MAD_TX,
437 NUM_CODEC_DAIS,
438 };
439
440 enum {
441 INTn_1_INP_SEL_ZERO = 0,
442 INTn_1_INP_SEL_DEC0,
443 INTn_1_INP_SEL_DEC1,
444 INTn_1_INP_SEL_IIR0,
445 INTn_1_INP_SEL_IIR1,
446 INTn_1_INP_SEL_RX0,
447 INTn_1_INP_SEL_RX1,
448 INTn_1_INP_SEL_RX2,
449 INTn_1_INP_SEL_RX3,
450 INTn_1_INP_SEL_RX4,
451 INTn_1_INP_SEL_RX5,
452 INTn_1_INP_SEL_RX6,
453 INTn_1_INP_SEL_RX7,
454 };
455
456 enum {
457 INTn_2_INP_SEL_ZERO = 0,
458 INTn_2_INP_SEL_RX0,
459 INTn_2_INP_SEL_RX1,
460 INTn_2_INP_SEL_RX2,
461 INTn_2_INP_SEL_RX3,
462 INTn_2_INP_SEL_RX4,
463 INTn_2_INP_SEL_RX5,
464 INTn_2_INP_SEL_RX6,
465 INTn_2_INP_SEL_RX7,
466 INTn_2_INP_SEL_PROXIMITY,
467 };
468
469 enum {
470 INTERP_MAIN_PATH,
471 INTERP_MIX_PATH,
472 };
473
474 struct interp_sample_rate {
475 int sample_rate;
476 int rate_val;
477 };
478
479 static struct interp_sample_rate sr_val_tbl[] = {
480 {8000, 0x0},
481 {16000, 0x1},
482 {32000, 0x3},
483 {48000, 0x4},
484 {96000, 0x5},
485 {192000, 0x6},
486 {384000, 0x7},
487 {44100, 0x9},
488 {88200, 0xA},
489 {176400, 0xB},
490 {352800, 0xC},
491 };
492
493 struct wcd_slim_codec_dai_data {
494 struct list_head slim_ch_list;
495 struct slim_stream_config sconfig;
496 struct slim_stream_runtime *sruntime;
497 };
498
499 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
500 {
501 .name = "WCD9335-IFC-DEV",
502 .range_min = 0x0,
503 .range_max = 0xffff,
504 .selector_reg = 0x800,
505 .selector_mask = 0xfff,
506 .selector_shift = 0,
507 .window_start = 0x800,
508 .window_len = 0x400,
509 },
510 };
511
512 static struct regmap_config wcd934x_ifc_regmap_config = {
513 .reg_bits = 16,
514 .val_bits = 8,
515 .max_register = 0xffff,
516 .ranges = wcd934x_ifc_ranges,
517 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
518 };
519
520 struct wcd934x_codec {
521 struct device *dev;
522 struct clk_hw hw;
523 struct clk *extclk;
524 struct regmap *regmap;
525 struct regmap *if_regmap;
526 struct slim_device *sdev;
527 struct slim_device *sidev;
528 struct wcd_clsh_ctrl *clsh_ctrl;
529 struct snd_soc_component *component;
530 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
531 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
532 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
533 int rate;
534 u32 version;
535 u32 hph_mode;
536 int num_rx_port;
537 int num_tx_port;
538 u32 tx_port_value[WCD934X_TX_MAX];
539 u32 rx_port_value[WCD934X_RX_MAX];
540 int sido_input_src;
541 int dmic_0_1_clk_cnt;
542 int dmic_2_3_clk_cnt;
543 int dmic_4_5_clk_cnt;
544 int dmic_sample_rate;
545 int comp_enabled[COMPANDER_MAX];
546 int sysclk_users;
547 struct mutex sysclk_mutex;
548 };
549
550 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
551
552 struct wcd_iir_filter_ctl {
553 unsigned int iir_idx;
554 unsigned int band_idx;
555 struct soc_bytes_ext bytes_ext;
556 };
557
558 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
559 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
560 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
561 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
562
563 /* Cutoff frequency for high pass filter */
564 static const char * const cf_text[] = {
565 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
566 };
567
568 static const char * const rx_cf_text[] = {
569 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
570 "CF_NEG_3DB_0P48HZ"
571 };
572
573 static const char * const rx_hph_mode_mux_text[] = {
574 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
575 "Class-H Hi-Fi Low Power"
576 };
577
578 static const char *const slim_rx_mux_text[] = {
579 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
580 };
581
582 static const char * const rx_int0_7_mix_mux_text[] = {
583 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
584 "RX6", "RX7", "PROXIMITY"
585 };
586
587 static const char * const rx_int_mix_mux_text[] = {
588 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
589 "RX6", "RX7"
590 };
591
592 static const char * const rx_prim_mix_text[] = {
593 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
594 "RX3", "RX4", "RX5", "RX6", "RX7"
595 };
596
597 static const char * const rx_sidetone_mix_text[] = {
598 "ZERO", "SRC0", "SRC1", "SRC_SUM"
599 };
600
601 static const char * const iir_inp_mux_text[] = {
602 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
603 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
604 };
605
606 static const char * const rx_int_dem_inp_mux_text[] = {
607 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
608 };
609
610 static const char * const rx_int0_1_interp_mux_text[] = {
611 "ZERO", "RX INT0_1 MIX1",
612 };
613
614 static const char * const rx_int1_1_interp_mux_text[] = {
615 "ZERO", "RX INT1_1 MIX1",
616 };
617
618 static const char * const rx_int2_1_interp_mux_text[] = {
619 "ZERO", "RX INT2_1 MIX1",
620 };
621
622 static const char * const rx_int3_1_interp_mux_text[] = {
623 "ZERO", "RX INT3_1 MIX1",
624 };
625
626 static const char * const rx_int4_1_interp_mux_text[] = {
627 "ZERO", "RX INT4_1 MIX1",
628 };
629
630 static const char * const rx_int7_1_interp_mux_text[] = {
631 "ZERO", "RX INT7_1 MIX1",
632 };
633
634 static const char * const rx_int8_1_interp_mux_text[] = {
635 "ZERO", "RX INT8_1 MIX1",
636 };
637
638 static const char * const rx_int0_2_interp_mux_text[] = {
639 "ZERO", "RX INT0_2 MUX",
640 };
641
642 static const char * const rx_int1_2_interp_mux_text[] = {
643 "ZERO", "RX INT1_2 MUX",
644 };
645
646 static const char * const rx_int2_2_interp_mux_text[] = {
647 "ZERO", "RX INT2_2 MUX",
648 };
649
650 static const char * const rx_int3_2_interp_mux_text[] = {
651 "ZERO", "RX INT3_2 MUX",
652 };
653
654 static const char * const rx_int4_2_interp_mux_text[] = {
655 "ZERO", "RX INT4_2 MUX",
656 };
657
658 static const char * const rx_int7_2_interp_mux_text[] = {
659 "ZERO", "RX INT7_2 MUX",
660 };
661
662 static const char * const rx_int8_2_interp_mux_text[] = {
663 "ZERO", "RX INT8_2 MUX",
664 };
665
666 static const char * const dmic_mux_text[] = {
667 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
668 };
669
670 static const char * const amic_mux_text[] = {
671 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
672 };
673
674 static const char * const amic4_5_sel_text[] = {
675 "AMIC4", "AMIC5"
676 };
677
678 static const char * const adc_mux_text[] = {
679 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
680 };
681
682 static const char * const cdc_if_tx0_mux_text[] = {
683 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
684 };
685
686 static const char * const cdc_if_tx1_mux_text[] = {
687 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
688 };
689
690 static const char * const cdc_if_tx2_mux_text[] = {
691 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
692 };
693
694 static const char * const cdc_if_tx3_mux_text[] = {
695 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
696 };
697
698 static const char * const cdc_if_tx4_mux_text[] = {
699 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
700 };
701
702 static const char * const cdc_if_tx5_mux_text[] = {
703 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
704 };
705
706 static const char * const cdc_if_tx6_mux_text[] = {
707 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
708 };
709
710 static const char * const cdc_if_tx7_mux_text[] = {
711 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
712 };
713
714 static const char * const cdc_if_tx8_mux_text[] = {
715 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
716 };
717
718 static const char * const cdc_if_tx9_mux_text[] = {
719 "ZERO", "DEC7", "DEC7_192"
720 };
721
722 static const char * const cdc_if_tx10_mux_text[] = {
723 "ZERO", "DEC6", "DEC6_192"
724 };
725
726 static const char * const cdc_if_tx11_mux_text[] = {
727 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
728 };
729
730 static const char * const cdc_if_tx11_inp1_mux_text[] = {
731 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
732 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
733 };
734
735 static const char * const cdc_if_tx13_mux_text[] = {
736 "CDC_DEC_5", "MAD_BRDCST"
737 };
738
739 static const char * const cdc_if_tx13_inp1_mux_text[] = {
740 "ZERO", "DEC5", "DEC5_192"
741 };
742
743 static const struct soc_enum cf_dec0_enum =
744 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
745
746 static const struct soc_enum cf_dec1_enum =
747 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
748
749 static const struct soc_enum cf_dec2_enum =
750 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
751
752 static const struct soc_enum cf_dec3_enum =
753 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
754
755 static const struct soc_enum cf_dec4_enum =
756 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
757
758 static const struct soc_enum cf_dec5_enum =
759 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
760
761 static const struct soc_enum cf_dec6_enum =
762 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
763
764 static const struct soc_enum cf_dec7_enum =
765 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
766
767 static const struct soc_enum cf_dec8_enum =
768 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
769
770 static const struct soc_enum cf_int0_1_enum =
771 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
772
773 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
774 rx_cf_text);
775
776 static const struct soc_enum cf_int1_1_enum =
777 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
778
779 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
780 rx_cf_text);
781
782 static const struct soc_enum cf_int2_1_enum =
783 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
784
785 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
786 rx_cf_text);
787
788 static const struct soc_enum cf_int3_1_enum =
789 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
790
791 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
792 rx_cf_text);
793
794 static const struct soc_enum cf_int4_1_enum =
795 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
796
797 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
798 rx_cf_text);
799
800 static const struct soc_enum cf_int7_1_enum =
801 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
802
803 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
804 rx_cf_text);
805
806 static const struct soc_enum cf_int8_1_enum =
807 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
808
809 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
810 rx_cf_text);
811
812 static const struct soc_enum rx_hph_mode_mux_enum =
813 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
814 rx_hph_mode_mux_text);
815
816 static const struct soc_enum slim_rx_mux_enum =
817 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
818
819 static const struct soc_enum rx_int0_2_mux_chain_enum =
820 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
821 rx_int0_7_mix_mux_text);
822
823 static const struct soc_enum rx_int1_2_mux_chain_enum =
824 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
825 rx_int_mix_mux_text);
826
827 static const struct soc_enum rx_int2_2_mux_chain_enum =
828 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
829 rx_int_mix_mux_text);
830
831 static const struct soc_enum rx_int3_2_mux_chain_enum =
832 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
833 rx_int_mix_mux_text);
834
835 static const struct soc_enum rx_int4_2_mux_chain_enum =
836 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
837 rx_int_mix_mux_text);
838
839 static const struct soc_enum rx_int7_2_mux_chain_enum =
840 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
841 rx_int0_7_mix_mux_text);
842
843 static const struct soc_enum rx_int8_2_mux_chain_enum =
844 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
845 rx_int_mix_mux_text);
846
847 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
848 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
849 rx_prim_mix_text);
850
851 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
852 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
853 rx_prim_mix_text);
854
855 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
856 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
857 rx_prim_mix_text);
858
859 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
860 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
861 rx_prim_mix_text);
862
863 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
864 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
865 rx_prim_mix_text);
866
867 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
868 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
869 rx_prim_mix_text);
870
871 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
872 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
873 rx_prim_mix_text);
874
875 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
876 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
877 rx_prim_mix_text);
878
879 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
880 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
881 rx_prim_mix_text);
882
883 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
884 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
885 rx_prim_mix_text);
886
887 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
888 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
889 rx_prim_mix_text);
890
891 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
892 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
893 rx_prim_mix_text);
894
895 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
896 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
897 rx_prim_mix_text);
898
899 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
900 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
901 rx_prim_mix_text);
902
903 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
904 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
905 rx_prim_mix_text);
906
907 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
908 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
909 rx_prim_mix_text);
910
911 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
912 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
913 rx_prim_mix_text);
914
915 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
916 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
917 rx_prim_mix_text);
918
919 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
920 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
921 rx_prim_mix_text);
922
923 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
924 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
925 rx_prim_mix_text);
926
927 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
928 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
929 rx_prim_mix_text);
930
931 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
932 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
933 rx_sidetone_mix_text);
934
935 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
936 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
937 rx_sidetone_mix_text);
938
939 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
940 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
941 rx_sidetone_mix_text);
942
943 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
944 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
945 rx_sidetone_mix_text);
946
947 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
948 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
949 rx_sidetone_mix_text);
950
951 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
952 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
953 rx_sidetone_mix_text);
954
955 static const struct soc_enum iir0_inp0_mux_enum =
956 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
957 0, 18, iir_inp_mux_text);
958
959 static const struct soc_enum iir0_inp1_mux_enum =
960 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
961 0, 18, iir_inp_mux_text);
962
963 static const struct soc_enum iir0_inp2_mux_enum =
964 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
965 0, 18, iir_inp_mux_text);
966
967 static const struct soc_enum iir0_inp3_mux_enum =
968 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
969 0, 18, iir_inp_mux_text);
970
971 static const struct soc_enum iir1_inp0_mux_enum =
972 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
973 0, 18, iir_inp_mux_text);
974
975 static const struct soc_enum iir1_inp1_mux_enum =
976 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
977 0, 18, iir_inp_mux_text);
978
979 static const struct soc_enum iir1_inp2_mux_enum =
980 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
981 0, 18, iir_inp_mux_text);
982
983 static const struct soc_enum iir1_inp3_mux_enum =
984 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
985 0, 18, iir_inp_mux_text);
986
987 static const struct soc_enum rx_int0_dem_inp_mux_enum =
988 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
989 ARRAY_SIZE(rx_int_dem_inp_mux_text),
990 rx_int_dem_inp_mux_text);
991
992 static const struct soc_enum rx_int1_dem_inp_mux_enum =
993 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
994 ARRAY_SIZE(rx_int_dem_inp_mux_text),
995 rx_int_dem_inp_mux_text);
996
997 static const struct soc_enum rx_int2_dem_inp_mux_enum =
998 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
999 ARRAY_SIZE(rx_int_dem_inp_mux_text),
1000 rx_int_dem_inp_mux_text);
1001
1002 static const struct soc_enum tx_adc_mux0_enum =
1003 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1004 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1005 static const struct soc_enum tx_adc_mux1_enum =
1006 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1007 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1008 static const struct soc_enum tx_adc_mux2_enum =
1009 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1010 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1011 static const struct soc_enum tx_adc_mux3_enum =
1012 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1013 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1014 static const struct soc_enum tx_adc_mux4_enum =
1015 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1016 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1017 static const struct soc_enum tx_adc_mux5_enum =
1018 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1019 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1020 static const struct soc_enum tx_adc_mux6_enum =
1021 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1022 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1023 static const struct soc_enum tx_adc_mux7_enum =
1024 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1025 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1026 static const struct soc_enum tx_adc_mux8_enum =
1027 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1028 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1029
1030 static const struct soc_enum rx_int0_1_interp_mux_enum =
1031 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1032 rx_int0_1_interp_mux_text);
1033
1034 static const struct soc_enum rx_int1_1_interp_mux_enum =
1035 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1036 rx_int1_1_interp_mux_text);
1037
1038 static const struct soc_enum rx_int2_1_interp_mux_enum =
1039 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1040 rx_int2_1_interp_mux_text);
1041
1042 static const struct soc_enum rx_int3_1_interp_mux_enum =
1043 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text);
1044
1045 static const struct soc_enum rx_int4_1_interp_mux_enum =
1046 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text);
1047
1048 static const struct soc_enum rx_int7_1_interp_mux_enum =
1049 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text);
1050
1051 static const struct soc_enum rx_int8_1_interp_mux_enum =
1052 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text);
1053
1054 static const struct soc_enum rx_int0_2_interp_mux_enum =
1055 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text);
1056
1057 static const struct soc_enum rx_int1_2_interp_mux_enum =
1058 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text);
1059
1060 static const struct soc_enum rx_int2_2_interp_mux_enum =
1061 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text);
1062
1063 static const struct soc_enum rx_int3_2_interp_mux_enum =
1064 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text);
1065
1066 static const struct soc_enum rx_int4_2_interp_mux_enum =
1067 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text);
1068
1069 static const struct soc_enum rx_int7_2_interp_mux_enum =
1070 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text);
1071
1072 static const struct soc_enum rx_int8_2_interp_mux_enum =
1073 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text);
1074
1075 static const struct soc_enum tx_dmic_mux0_enum =
1076 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1077 dmic_mux_text);
1078
1079 static const struct soc_enum tx_dmic_mux1_enum =
1080 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1081 dmic_mux_text);
1082
1083 static const struct soc_enum tx_dmic_mux2_enum =
1084 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1085 dmic_mux_text);
1086
1087 static const struct soc_enum tx_dmic_mux3_enum =
1088 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1089 dmic_mux_text);
1090
1091 static const struct soc_enum tx_dmic_mux4_enum =
1092 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1093 dmic_mux_text);
1094
1095 static const struct soc_enum tx_dmic_mux5_enum =
1096 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1097 dmic_mux_text);
1098
1099 static const struct soc_enum tx_dmic_mux6_enum =
1100 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1101 dmic_mux_text);
1102
1103 static const struct soc_enum tx_dmic_mux7_enum =
1104 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1105 dmic_mux_text);
1106
1107 static const struct soc_enum tx_dmic_mux8_enum =
1108 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1109 dmic_mux_text);
1110
1111 static const struct soc_enum tx_amic_mux0_enum =
1112 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1113 amic_mux_text);
1114 static const struct soc_enum tx_amic_mux1_enum =
1115 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1116 amic_mux_text);
1117 static const struct soc_enum tx_amic_mux2_enum =
1118 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1119 amic_mux_text);
1120 static const struct soc_enum tx_amic_mux3_enum =
1121 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1122 amic_mux_text);
1123 static const struct soc_enum tx_amic_mux4_enum =
1124 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1125 amic_mux_text);
1126 static const struct soc_enum tx_amic_mux5_enum =
1127 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1128 amic_mux_text);
1129 static const struct soc_enum tx_amic_mux6_enum =
1130 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1131 amic_mux_text);
1132 static const struct soc_enum tx_amic_mux7_enum =
1133 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1134 amic_mux_text);
1135 static const struct soc_enum tx_amic_mux8_enum =
1136 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1137 amic_mux_text);
1138
1139 static const struct soc_enum tx_amic4_5_enum =
1140 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1141
1142 static const struct soc_enum cdc_if_tx0_mux_enum =
1143 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1144 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1145 static const struct soc_enum cdc_if_tx1_mux_enum =
1146 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1147 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1148 static const struct soc_enum cdc_if_tx2_mux_enum =
1149 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1150 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1151 static const struct soc_enum cdc_if_tx3_mux_enum =
1152 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1153 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1154 static const struct soc_enum cdc_if_tx4_mux_enum =
1155 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1156 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1157 static const struct soc_enum cdc_if_tx5_mux_enum =
1158 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1159 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1160 static const struct soc_enum cdc_if_tx6_mux_enum =
1161 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1162 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1163 static const struct soc_enum cdc_if_tx7_mux_enum =
1164 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1165 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1166 static const struct soc_enum cdc_if_tx8_mux_enum =
1167 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1168 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1169 static const struct soc_enum cdc_if_tx9_mux_enum =
1170 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1171 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1172 static const struct soc_enum cdc_if_tx10_mux_enum =
1173 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1174 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1175 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1176 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1177 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1178 cdc_if_tx11_inp1_mux_text);
1179 static const struct soc_enum cdc_if_tx11_mux_enum =
1180 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1181 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1182 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1183 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1184 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1185 cdc_if_tx13_inp1_mux_text);
1186 static const struct soc_enum cdc_if_tx13_mux_enum =
1187 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1188 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1189
1190 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1191 {
1192 if (sido_src == wcd->sido_input_src)
1193 return 0;
1194
1195 if (sido_src == SIDO_SOURCE_INTERNAL) {
1196 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1197 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 0);
1198 usleep_range(100, 110);
1199 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1200 WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK, 0x0);
1201 usleep_range(100, 110);
1202 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1203 WCD934X_ANA_RCO_BG_EN_MASK, 0);
1204 usleep_range(100, 110);
1205 } else if (sido_src == SIDO_SOURCE_RCO_BG) {
1206 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1207 WCD934X_ANA_RCO_BG_EN_MASK,
1208 WCD934X_ANA_RCO_BG_ENABLE);
1209 usleep_range(100, 110);
1210 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1211 WCD934X_ANA_BUCK_PRE_EN1_MASK,
1212 WCD934X_ANA_BUCK_PRE_EN1_ENABLE);
1213 usleep_range(100, 110);
1214 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1215 WCD934X_ANA_BUCK_PRE_EN2_MASK,
1216 WCD934X_ANA_BUCK_PRE_EN2_ENABLE);
1217 usleep_range(100, 110);
1218 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1219 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK,
1220 WCD934X_ANA_BUCK_HI_ACCU_ENABLE);
1221 usleep_range(100, 110);
1222 }
1223 wcd->sido_input_src = sido_src;
1224
1225 return 0;
1226 }
1227
1228 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1229 {
1230 mutex_lock(&wcd->sysclk_mutex);
1231
1232 if (++wcd->sysclk_users != 1) {
1233 mutex_unlock(&wcd->sysclk_mutex);
1234 return 0;
1235 }
1236 mutex_unlock(&wcd->sysclk_mutex);
1237
1238 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1239 WCD934X_ANA_BIAS_EN_MASK,
1240 WCD934X_ANA_BIAS_EN);
1241 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1242 WCD934X_ANA_PRECHRG_EN_MASK,
1243 WCD934X_ANA_PRECHRG_EN);
1244 /*
1245 * 1ms delay is required after pre-charge is enabled
1246 * as per HW requirement
1247 */
1248 usleep_range(1000, 1100);
1249 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1250 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1251 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1252 WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1253
1254 /*
1255 * In data clock contrl register is changed
1256 * to CLK_SYS_MCLK_PRG
1257 */
1258
1259 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1260 WCD934X_EXT_CLK_BUF_EN_MASK,
1261 WCD934X_EXT_CLK_BUF_EN);
1262 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1263 WCD934X_EXT_CLK_DIV_RATIO_MASK,
1264 WCD934X_EXT_CLK_DIV_BY_2);
1265 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1266 WCD934X_MCLK_SRC_MASK,
1267 WCD934X_MCLK_SRC_EXT_CLK);
1268 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1269 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1270 regmap_update_bits(wcd->regmap,
1271 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1272 WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1273 WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1274 regmap_update_bits(wcd->regmap,
1275 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1276 WCD934X_MCLK_EN_MASK,
1277 WCD934X_MCLK_EN);
1278 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1279 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1280 /*
1281 * 10us sleep is required after clock is enabled
1282 * as per HW requirement
1283 */
1284 usleep_range(10, 15);
1285
1286 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1287
1288 return 0;
1289 }
1290
1291 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1292 {
1293 mutex_lock(&wcd->sysclk_mutex);
1294 if (--wcd->sysclk_users != 0) {
1295 mutex_unlock(&wcd->sysclk_mutex);
1296 return 0;
1297 }
1298 mutex_unlock(&wcd->sysclk_mutex);
1299
1300 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1301 WCD934X_EXT_CLK_BUF_EN_MASK |
1302 WCD934X_MCLK_EN_MASK, 0x0);
1303 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_INTERNAL);
1304
1305 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1306 WCD934X_ANA_BIAS_EN_MASK, 0);
1307 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1308 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1309
1310 return 0;
1311 }
1312
1313 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1314 {
1315 int ret = 0;
1316
1317 if (enable) {
1318 ret = clk_prepare_enable(wcd->extclk);
1319
1320 if (ret) {
1321 dev_err(wcd->dev, "%s: ext clk enable failed\n",
1322 __func__);
1323 return ret;
1324 }
1325 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1326 } else {
1327 int val;
1328
1329 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1330 &val);
1331
1332 /* Don't disable clock if soundwire using it.*/
1333 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1334 return 0;
1335
1336 wcd934x_disable_ana_bias_and_syclk(wcd);
1337 clk_disable_unprepare(wcd->extclk);
1338 }
1339
1340 return ret;
1341 }
1342
1343 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1344 struct snd_kcontrol *kc, int event)
1345 {
1346 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1347 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1348
1349 switch (event) {
1350 case SND_SOC_DAPM_PRE_PMU:
1351 return __wcd934x_cdc_mclk_enable(wcd, true);
1352 case SND_SOC_DAPM_POST_PMD:
1353 return __wcd934x_cdc_mclk_enable(wcd, false);
1354 }
1355
1356 return 0;
1357 }
1358
1359 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1360 {
1361 int val1, val2, ver, ret;
1362 struct regmap *regmap;
1363 u16 id_minor;
1364 u32 version_mask = 0;
1365
1366 regmap = wcd->regmap;
1367 ver = 0;
1368
1369 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1370 (u8 *)&id_minor, sizeof(u16));
1371
1372 if (ret)
1373 return ret;
1374
1375 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1376 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1377
1378 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1379 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1380
1381 switch (version_mask) {
1382 case DSD_DISABLED | SLNQ_DISABLED:
1383 if (id_minor == 0)
1384 ver = WCD_VERSION_WCD9340_1_0;
1385 else if (id_minor == 0x01)
1386 ver = WCD_VERSION_WCD9340_1_1;
1387 break;
1388 case SLNQ_DISABLED:
1389 if (id_minor == 0)
1390 ver = WCD_VERSION_WCD9341_1_0;
1391 else if (id_minor == 0x01)
1392 ver = WCD_VERSION_WCD9341_1_1;
1393 break;
1394 }
1395
1396 wcd->version = ver;
1397 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1398
1399 return 0;
1400 }
1401
1402 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1403 {
1404 int rc, val;
1405
1406 __wcd934x_cdc_mclk_enable(wcd, true);
1407
1408 regmap_update_bits(wcd->regmap,
1409 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1410 WCD934X_EFUSE_SENSE_STATE_MASK,
1411 WCD934X_EFUSE_SENSE_STATE_DEF);
1412 regmap_update_bits(wcd->regmap,
1413 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1414 WCD934X_EFUSE_SENSE_EN_MASK,
1415 WCD934X_EFUSE_SENSE_ENABLE);
1416 /*
1417 * 5ms sleep required after enabling efuse control
1418 * before checking the status.
1419 */
1420 usleep_range(5000, 5500);
1421 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1422
1423 rc = regmap_read(wcd->regmap,
1424 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1425 if (rc || (!(val & 0x01)))
1426 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1427 __func__, val, rc);
1428
1429 __wcd934x_cdc_mclk_enable(wcd, false);
1430 }
1431
1432 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1433 {
1434 if (enable) {
1435 __wcd934x_cdc_mclk_enable(wcd, true);
1436 regmap_update_bits(wcd->regmap,
1437 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1438 WCD934X_CDC_SWR_CLK_EN_MASK,
1439 WCD934X_CDC_SWR_CLK_ENABLE);
1440 } else {
1441 regmap_update_bits(wcd->regmap,
1442 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1443 WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1444 __wcd934x_cdc_mclk_enable(wcd, false);
1445 }
1446
1447 return 0;
1448 }
1449
1450 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1451 u8 rate_val, u32 rate)
1452 {
1453 struct snd_soc_component *comp = dai->component;
1454 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1455 struct wcd934x_slim_ch *ch;
1456 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1457 int inp, j;
1458
1459 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1460 inp = ch->shift + INTn_1_INP_SEL_RX0;
1461 /*
1462 * Loop through all interpolator MUX inputs and find out
1463 * to which interpolator input, the slim rx port
1464 * is connected
1465 */
1466 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1467 /* Interpolators 5 and 6 are not aviliable in Tavil */
1468 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1469 continue;
1470
1471 cfg0 = snd_soc_component_read32(comp,
1472 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1473 cfg1 = snd_soc_component_read32(comp,
1474 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1475
1476 inp0_sel = cfg0 &
1477 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1478 inp1_sel = (cfg0 >> 4) &
1479 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1480 inp2_sel = (cfg1 >> 4) &
1481 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1482
1483 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1484 (inp2_sel == inp)) {
1485 /* rate is in Hz */
1486 /*
1487 * Ear and speaker primary path does not support
1488 * native sample rates
1489 */
1490 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1491 j == INTERP_SPKR2) && rate == 44100)
1492 dev_err(wcd->dev,
1493 "Cannot set 44.1KHz on INT%d\n",
1494 j);
1495 else
1496 snd_soc_component_update_bits(comp,
1497 WCD934X_CDC_RX_PATH_CTL(j),
1498 WCD934X_CDC_MIX_PCM_RATE_MASK,
1499 rate_val);
1500 }
1501 }
1502 }
1503
1504 return 0;
1505 }
1506
1507 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1508 int rate_val, u32 rate)
1509 {
1510 struct snd_soc_component *component = dai->component;
1511 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1512 struct wcd934x_slim_ch *ch;
1513 int val, j;
1514
1515 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1516 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1517 /* Interpolators 5 and 6 are not aviliable in Tavil */
1518 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1519 continue;
1520 val = snd_soc_component_read32(component,
1521 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1522 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1523
1524 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1525 /*
1526 * Ear mix path supports only 48, 96, 192,
1527 * 384KHz only
1528 */
1529 if ((j == INTERP_EAR) &&
1530 (rate_val < 0x4 ||
1531 rate_val > 0x7)) {
1532 dev_err(component->dev,
1533 "Invalid rate for AIF_PB DAI(%d)\n",
1534 dai->id);
1535 return -EINVAL;
1536 }
1537
1538 snd_soc_component_update_bits(component,
1539 WCD934X_CDC_RX_PATH_MIX_CTL(j),
1540 WCD934X_CDC_MIX_PCM_RATE_MASK,
1541 rate_val);
1542 }
1543 }
1544 }
1545
1546 return 0;
1547 }
1548
1549 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1550 u32 sample_rate)
1551 {
1552 int rate_val = 0;
1553 int i, ret;
1554
1555 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1556 if (sample_rate == sr_val_tbl[i].sample_rate) {
1557 rate_val = sr_val_tbl[i].rate_val;
1558 break;
1559 }
1560 }
1561 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1562 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1563 return -EINVAL;
1564 }
1565
1566 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1567 sample_rate);
1568 if (ret)
1569 return ret;
1570 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1571 sample_rate);
1572 if (ret)
1573 return ret;
1574
1575 return ret;
1576 }
1577
1578 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1579 u8 rate_val, u32 rate)
1580 {
1581 struct snd_soc_component *comp = dai->component;
1582 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1583 u8 shift = 0, shift_val = 0, tx_mux_sel;
1584 struct wcd934x_slim_ch *ch;
1585 int tx_port, tx_port_reg;
1586 int decimator = -1;
1587
1588 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1589 tx_port = ch->port;
1590 /* Find the SB TX MUX input - which decimator is connected */
1591 switch (tx_port) {
1592 case 0 ... 3:
1593 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1594 shift = (tx_port << 1);
1595 shift_val = 0x03;
1596 break;
1597 case 4 ... 7:
1598 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1599 shift = ((tx_port - 4) << 1);
1600 shift_val = 0x03;
1601 break;
1602 case 8 ... 10:
1603 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1604 shift = ((tx_port - 8) << 1);
1605 shift_val = 0x03;
1606 break;
1607 case 11:
1608 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1609 shift = 0;
1610 shift_val = 0x0F;
1611 break;
1612 case 13:
1613 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1614 shift = 4;
1615 shift_val = 0x03;
1616 break;
1617 default:
1618 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1619 tx_port, dai->id);
1620 return -EINVAL;
1621 }
1622
1623 tx_mux_sel = snd_soc_component_read32(comp, tx_port_reg) &
1624 (shift_val << shift);
1625
1626 tx_mux_sel = tx_mux_sel >> shift;
1627 switch (tx_port) {
1628 case 0 ... 8:
1629 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1630 decimator = tx_port;
1631 break;
1632 case 9 ... 10:
1633 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1634 decimator = ((tx_port == 9) ? 7 : 6);
1635 break;
1636 case 11:
1637 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1638 decimator = tx_mux_sel - 1;
1639 break;
1640 case 13:
1641 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1642 decimator = 5;
1643 break;
1644 default:
1645 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1646 tx_port);
1647 return -EINVAL;
1648 }
1649
1650 snd_soc_component_update_bits(comp,
1651 WCD934X_CDC_TX_PATH_CTL(decimator),
1652 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1653 rate_val);
1654 }
1655
1656 return 0;
1657 }
1658
1659 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1660 struct wcd_slim_codec_dai_data *dai_data,
1661 int direction)
1662 {
1663 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1664 struct slim_stream_config *cfg = &dai_data->sconfig;
1665 struct wcd934x_slim_ch *ch;
1666 u16 payload = 0;
1667 int ret, i;
1668
1669 cfg->ch_count = 0;
1670 cfg->direction = direction;
1671 cfg->port_mask = 0;
1672
1673 /* Configure slave interface device */
1674 list_for_each_entry(ch, slim_ch_list, list) {
1675 cfg->ch_count++;
1676 payload |= 1 << ch->shift;
1677 cfg->port_mask |= BIT(ch->port);
1678 }
1679
1680 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1681 if (!cfg->chs)
1682 return -ENOMEM;
1683
1684 i = 0;
1685 list_for_each_entry(ch, slim_ch_list, list) {
1686 cfg->chs[i++] = ch->ch_num;
1687 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1688 /* write to interface device */
1689 ret = regmap_write(wcd->if_regmap,
1690 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1691 payload);
1692
1693 if (ret < 0)
1694 goto err;
1695
1696 /* configure the slave port for water mark and enable*/
1697 ret = regmap_write(wcd->if_regmap,
1698 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1699 WCD934X_SLIM_WATER_MARK_VAL);
1700 if (ret < 0)
1701 goto err;
1702 } else {
1703 ret = regmap_write(wcd->if_regmap,
1704 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1705 payload & 0x00FF);
1706 if (ret < 0)
1707 goto err;
1708
1709 /* ports 8,9 */
1710 ret = regmap_write(wcd->if_regmap,
1711 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1712 (payload & 0xFF00) >> 8);
1713 if (ret < 0)
1714 goto err;
1715
1716 /* configure the slave port for water mark and enable*/
1717 ret = regmap_write(wcd->if_regmap,
1718 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1719 WCD934X_SLIM_WATER_MARK_VAL);
1720
1721 if (ret < 0)
1722 goto err;
1723 }
1724 }
1725
1726 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1727
1728 return 0;
1729
1730 err:
1731 dev_err(wcd->dev, "Error Setting slim hw params\n");
1732 kfree(cfg->chs);
1733 cfg->chs = NULL;
1734
1735 return ret;
1736 }
1737
1738 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1739 struct snd_pcm_hw_params *params,
1740 struct snd_soc_dai *dai)
1741 {
1742 struct wcd934x_codec *wcd;
1743 int ret, tx_fs_rate = 0;
1744
1745 wcd = snd_soc_component_get_drvdata(dai->component);
1746
1747 switch (substream->stream) {
1748 case SNDRV_PCM_STREAM_PLAYBACK:
1749 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1750 if (ret) {
1751 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1752 params_rate(params));
1753 return ret;
1754 }
1755 switch (params_width(params)) {
1756 case 16 ... 24:
1757 wcd->dai[dai->id].sconfig.bps = params_width(params);
1758 break;
1759 default:
1760 dev_err(wcd->dev, "Invalid format 0x%x\n",
1761 params_width(params));
1762 return -EINVAL;
1763 }
1764 break;
1765
1766 case SNDRV_PCM_STREAM_CAPTURE:
1767 switch (params_rate(params)) {
1768 case 8000:
1769 tx_fs_rate = 0;
1770 break;
1771 case 16000:
1772 tx_fs_rate = 1;
1773 break;
1774 case 32000:
1775 tx_fs_rate = 3;
1776 break;
1777 case 48000:
1778 tx_fs_rate = 4;
1779 break;
1780 case 96000:
1781 tx_fs_rate = 5;
1782 break;
1783 case 192000:
1784 tx_fs_rate = 6;
1785 break;
1786 case 384000:
1787 tx_fs_rate = 7;
1788 break;
1789 default:
1790 dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1791 params_rate(params));
1792 return -EINVAL;
1793
1794 };
1795
1796 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1797 params_rate(params));
1798 if (ret < 0) {
1799 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1800 return ret;
1801 }
1802 switch (params_width(params)) {
1803 case 16 ... 32:
1804 wcd->dai[dai->id].sconfig.bps = params_width(params);
1805 break;
1806 default:
1807 dev_err(wcd->dev, "Invalid format 0x%x\n",
1808 params_width(params));
1809 return -EINVAL;
1810 };
1811 break;
1812 default:
1813 dev_err(wcd->dev, "Invalid stream type %d\n",
1814 substream->stream);
1815 return -EINVAL;
1816 };
1817
1818 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1819 wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1820
1821 return 0;
1822 }
1823
1824 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1825 struct snd_soc_dai *dai)
1826 {
1827 struct wcd_slim_codec_dai_data *dai_data;
1828 struct wcd934x_codec *wcd;
1829
1830 wcd = snd_soc_component_get_drvdata(dai->component);
1831
1832 dai_data = &wcd->dai[dai->id];
1833
1834 kfree(dai_data->sconfig.chs);
1835
1836 return 0;
1837 }
1838
1839 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1840 struct snd_soc_dai *dai)
1841 {
1842 struct wcd_slim_codec_dai_data *dai_data;
1843 struct wcd934x_codec *wcd;
1844 struct slim_stream_config *cfg;
1845
1846 wcd = snd_soc_component_get_drvdata(dai->component);
1847
1848 dai_data = &wcd->dai[dai->id];
1849
1850 switch (cmd) {
1851 case SNDRV_PCM_TRIGGER_START:
1852 case SNDRV_PCM_TRIGGER_RESUME:
1853 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1854 cfg = &dai_data->sconfig;
1855 slim_stream_prepare(dai_data->sruntime, cfg);
1856 slim_stream_enable(dai_data->sruntime);
1857 break;
1858 case SNDRV_PCM_TRIGGER_STOP:
1859 case SNDRV_PCM_TRIGGER_SUSPEND:
1860 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1861 slim_stream_unprepare(dai_data->sruntime);
1862 slim_stream_disable(dai_data->sruntime);
1863 break;
1864 default:
1865 break;
1866 }
1867
1868 return 0;
1869 }
1870
1871 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1872 unsigned int tx_num, unsigned int *tx_slot,
1873 unsigned int rx_num, unsigned int *rx_slot)
1874 {
1875 struct wcd934x_codec *wcd;
1876 int i;
1877
1878 wcd = snd_soc_component_get_drvdata(dai->component);
1879
1880 if (!tx_slot || !rx_slot) {
1881 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1882 tx_slot, rx_slot);
1883 return -EINVAL;
1884 }
1885
1886 if (wcd->rx_chs) {
1887 wcd->num_rx_port = rx_num;
1888 for (i = 0; i < rx_num; i++) {
1889 wcd->rx_chs[i].ch_num = rx_slot[i];
1890 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1891 }
1892 }
1893
1894 if (wcd->tx_chs) {
1895 wcd->num_tx_port = tx_num;
1896 for (i = 0; i < tx_num; i++) {
1897 wcd->tx_chs[i].ch_num = tx_slot[i];
1898 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1899 }
1900 }
1901
1902 return 0;
1903 }
1904
1905 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1906 unsigned int *tx_num, unsigned int *tx_slot,
1907 unsigned int *rx_num, unsigned int *rx_slot)
1908 {
1909 struct wcd934x_slim_ch *ch;
1910 struct wcd934x_codec *wcd;
1911 int i = 0;
1912
1913 wcd = snd_soc_component_get_drvdata(dai->component);
1914
1915 switch (dai->id) {
1916 case AIF1_PB:
1917 case AIF2_PB:
1918 case AIF3_PB:
1919 case AIF4_PB:
1920 if (!rx_slot || !rx_num) {
1921 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1922 rx_slot, rx_num);
1923 return -EINVAL;
1924 }
1925
1926 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1927 rx_slot[i++] = ch->ch_num;
1928
1929 *rx_num = i;
1930 break;
1931 case AIF1_CAP:
1932 case AIF2_CAP:
1933 case AIF3_CAP:
1934 if (!tx_slot || !tx_num) {
1935 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1936 tx_slot, tx_num);
1937 return -EINVAL;
1938 }
1939
1940 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1941 tx_slot[i++] = ch->ch_num;
1942
1943 *tx_num = i;
1944 break;
1945 default:
1946 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
1947 break;
1948 }
1949
1950 return 0;
1951 }
1952
1953 static struct snd_soc_dai_ops wcd934x_dai_ops = {
1954 .hw_params = wcd934x_hw_params,
1955 .hw_free = wcd934x_hw_free,
1956 .trigger = wcd934x_trigger,
1957 .set_channel_map = wcd934x_set_channel_map,
1958 .get_channel_map = wcd934x_get_channel_map,
1959 };
1960
1961 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
1962 [0] = {
1963 .name = "wcd934x_rx1",
1964 .id = AIF1_PB,
1965 .playback = {
1966 .stream_name = "AIF1 Playback",
1967 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1968 .formats = WCD934X_FORMATS_S16_S24_LE,
1969 .rate_max = 192000,
1970 .rate_min = 8000,
1971 .channels_min = 1,
1972 .channels_max = 2,
1973 },
1974 .ops = &wcd934x_dai_ops,
1975 },
1976 [1] = {
1977 .name = "wcd934x_tx1",
1978 .id = AIF1_CAP,
1979 .capture = {
1980 .stream_name = "AIF1 Capture",
1981 .rates = WCD934X_RATES_MASK,
1982 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1983 .rate_min = 8000,
1984 .rate_max = 192000,
1985 .channels_min = 1,
1986 .channels_max = 4,
1987 },
1988 .ops = &wcd934x_dai_ops,
1989 },
1990 [2] = {
1991 .name = "wcd934x_rx2",
1992 .id = AIF2_PB,
1993 .playback = {
1994 .stream_name = "AIF2 Playback",
1995 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1996 .formats = WCD934X_FORMATS_S16_S24_LE,
1997 .rate_min = 8000,
1998 .rate_max = 192000,
1999 .channels_min = 1,
2000 .channels_max = 2,
2001 },
2002 .ops = &wcd934x_dai_ops,
2003 },
2004 [3] = {
2005 .name = "wcd934x_tx2",
2006 .id = AIF2_CAP,
2007 .capture = {
2008 .stream_name = "AIF2 Capture",
2009 .rates = WCD934X_RATES_MASK,
2010 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2011 .rate_min = 8000,
2012 .rate_max = 192000,
2013 .channels_min = 1,
2014 .channels_max = 4,
2015 },
2016 .ops = &wcd934x_dai_ops,
2017 },
2018 [4] = {
2019 .name = "wcd934x_rx3",
2020 .id = AIF3_PB,
2021 .playback = {
2022 .stream_name = "AIF3 Playback",
2023 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2024 .formats = WCD934X_FORMATS_S16_S24_LE,
2025 .rate_min = 8000,
2026 .rate_max = 192000,
2027 .channels_min = 1,
2028 .channels_max = 2,
2029 },
2030 .ops = &wcd934x_dai_ops,
2031 },
2032 [5] = {
2033 .name = "wcd934x_tx3",
2034 .id = AIF3_CAP,
2035 .capture = {
2036 .stream_name = "AIF3 Capture",
2037 .rates = WCD934X_RATES_MASK,
2038 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2039 .rate_min = 8000,
2040 .rate_max = 192000,
2041 .channels_min = 1,
2042 .channels_max = 4,
2043 },
2044 .ops = &wcd934x_dai_ops,
2045 },
2046 [6] = {
2047 .name = "wcd934x_rx4",
2048 .id = AIF4_PB,
2049 .playback = {
2050 .stream_name = "AIF4 Playback",
2051 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2052 .formats = WCD934X_FORMATS_S16_S24_LE,
2053 .rate_min = 8000,
2054 .rate_max = 192000,
2055 .channels_min = 1,
2056 .channels_max = 2,
2057 },
2058 .ops = &wcd934x_dai_ops,
2059 },
2060 };
2061
2062 static int swclk_gate_enable(struct clk_hw *hw)
2063 {
2064 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2065 }
2066
2067 static void swclk_gate_disable(struct clk_hw *hw)
2068 {
2069 wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2070 }
2071
2072 static int swclk_gate_is_enabled(struct clk_hw *hw)
2073 {
2074 struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2075 int ret, val;
2076
2077 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2078 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2079
2080 return ret;
2081 }
2082
2083 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2084 unsigned long parent_rate)
2085 {
2086 return parent_rate / 2;
2087 }
2088
2089 static const struct clk_ops swclk_gate_ops = {
2090 .prepare = swclk_gate_enable,
2091 .unprepare = swclk_gate_disable,
2092 .is_enabled = swclk_gate_is_enabled,
2093 .recalc_rate = swclk_recalc_rate,
2094
2095 };
2096
2097 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2098 {
2099 struct clk *parent = wcd->extclk;
2100 struct device *dev = wcd->dev;
2101 struct device_node *np = dev->parent->of_node;
2102 const char *parent_clk_name = NULL;
2103 const char *clk_name = "mclk";
2104 struct clk_hw *hw;
2105 struct clk_init_data init;
2106 int ret;
2107
2108 if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2109 return NULL;
2110
2111 parent_clk_name = __clk_get_name(parent);
2112
2113 of_property_read_string(np, "clock-output-names", &clk_name);
2114
2115 init.name = clk_name;
2116 init.ops = &swclk_gate_ops;
2117 init.flags = 0;
2118 init.parent_names = &parent_clk_name;
2119 init.num_parents = 1;
2120 wcd->hw.init = &init;
2121
2122 hw = &wcd->hw;
2123 ret = clk_hw_register(wcd->dev->parent, hw);
2124 if (ret)
2125 return ERR_PTR(ret);
2126
2127 of_clk_add_provider(np, of_clk_src_simple_get, hw->clk);
2128
2129 return NULL;
2130 }
2131
2132 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias)
2133 {
2134 int mv;
2135
2136 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2137 dev_err(dev, "%s value not found, using default\n", micbias);
2138 mv = WCD934X_DEF_MICBIAS_MV;
2139 } else {
2140 /* convert it to milli volts */
2141 mv = mv/1000;
2142 }
2143
2144 if (mv < 1000 || mv > 2850) {
2145 dev_err(dev, "%s value not in valid range, using default\n",
2146 micbias);
2147 mv = WCD934X_DEF_MICBIAS_MV;
2148 }
2149
2150 return (mv - 1000) / 50;
2151 }
2152
2153 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2154 {
2155 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2156 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2157 u32 def_dmic_rate, dmic_clk_drv;
2158
2159 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2160 "qcom,micbias1-microvolt");
2161 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2162 "qcom,micbias2-microvolt");
2163 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2164 "qcom,micbias3-microvolt");
2165 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2166 "qcom,micbias4-microvolt");
2167
2168 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2169 WCD934X_MICB_VAL_MASK, vout_ctl_1);
2170 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2171 WCD934X_MICB_VAL_MASK, vout_ctl_2);
2172 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2173 WCD934X_MICB_VAL_MASK, vout_ctl_3);
2174 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2175 WCD934X_MICB_VAL_MASK, vout_ctl_4);
2176
2177 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2178 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2179 else
2180 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2181
2182 wcd->dmic_sample_rate = def_dmic_rate;
2183
2184 dmic_clk_drv = 0;
2185 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2186 0x0C, dmic_clk_drv << 2);
2187
2188 return 0;
2189 }
2190
2191 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2192 {
2193 struct regmap *rm = wcd->regmap;
2194
2195 /* set SPKR rate to FS_2P4_3P072 */
2196 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2197 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2198
2199 /* Take DMICs out of reset */
2200 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2201 }
2202
2203 static int wcd934x_comp_init(struct snd_soc_component *component)
2204 {
2205 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2206
2207 wcd934x_hw_init(wcd);
2208 wcd934x_enable_efuse_sensing(wcd);
2209 wcd934x_get_version(wcd);
2210
2211 return 0;
2212 }
2213
2214 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2215 {
2216 struct wcd934x_codec *wcd = data;
2217 unsigned long status = 0;
2218 int i, j, port_id;
2219 unsigned int val, int_val = 0;
2220 irqreturn_t ret = IRQ_NONE;
2221 bool tx;
2222 unsigned short reg = 0;
2223
2224 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2225 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2226 regmap_read(wcd->if_regmap, i, &val);
2227 status |= ((u32)val << (8 * j));
2228 }
2229
2230 for_each_set_bit(j, &status, 32) {
2231 tx = false;
2232 port_id = j;
2233
2234 if (j >= 16) {
2235 tx = true;
2236 port_id = j - 16;
2237 }
2238
2239 regmap_read(wcd->if_regmap,
2240 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2241 if (val) {
2242 if (!tx)
2243 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2244 (port_id / 8);
2245 else
2246 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2247 (port_id / 8);
2248 regmap_read(wcd->if_regmap, reg, &int_val);
2249 }
2250
2251 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2252 dev_err_ratelimited(wcd->dev,
2253 "overflow error on %s port %d, value %x\n",
2254 (tx ? "TX" : "RX"), port_id, val);
2255
2256 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2257 dev_err_ratelimited(wcd->dev,
2258 "underflow error on %s port %d, value %x\n",
2259 (tx ? "TX" : "RX"), port_id, val);
2260
2261 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2262 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2263 if (!tx)
2264 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2265 (port_id / 8);
2266 else
2267 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2268 (port_id / 8);
2269 regmap_read(
2270 wcd->if_regmap, reg, &int_val);
2271 if (int_val & (1 << (port_id % 8))) {
2272 int_val = int_val ^ (1 << (port_id % 8));
2273 regmap_write(wcd->if_regmap,
2274 reg, int_val);
2275 }
2276 }
2277
2278 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2279 dev_err_ratelimited(wcd->dev,
2280 "Port Closed %s port %d, value %x\n",
2281 (tx ? "TX" : "RX"), port_id, val);
2282
2283 regmap_write(wcd->if_regmap,
2284 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2285 BIT(j % 8));
2286 ret = IRQ_HANDLED;
2287 }
2288
2289 return ret;
2290 }
2291
2292 static int wcd934x_comp_probe(struct snd_soc_component *component)
2293 {
2294 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2295 int i;
2296
2297 snd_soc_component_init_regmap(component, wcd->regmap);
2298 wcd->component = component;
2299
2300 /* Class-H Init*/
2301 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
2302 if (IS_ERR(wcd->clsh_ctrl))
2303 return PTR_ERR(wcd->clsh_ctrl);
2304
2305 /* Default HPH Mode to Class-H Low HiFi */
2306 wcd->hph_mode = CLS_H_LOHIFI;
2307
2308 wcd934x_comp_init(component);
2309
2310 for (i = 0; i < NUM_CODEC_DAIS; i++)
2311 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
2312
2313 wcd934x_init_dmic(component);
2314 return 0;
2315 }
2316
2317 static void wcd934x_comp_remove(struct snd_soc_component *comp)
2318 {
2319 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2320
2321 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
2322 }
2323
2324 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
2325 int clk_id, int source,
2326 unsigned int freq, int dir)
2327 {
2328 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2329 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
2330
2331 wcd->rate = freq;
2332
2333 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
2334 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
2335
2336 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
2337 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
2338 val);
2339
2340 return clk_set_rate(wcd->extclk, freq);
2341 }
2342
2343 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2344 int iir_idx, int band_idx, int coeff_idx)
2345 {
2346 u32 value = 0;
2347 int reg, b2_reg;
2348
2349 /* Address does not automatically update if reading */
2350 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2351 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2352
2353 snd_soc_component_write(component, reg,
2354 ((band_idx * BAND_MAX + coeff_idx) *
2355 sizeof(uint32_t)) & 0x7F);
2356
2357 value |= snd_soc_component_read32(component, b2_reg);
2358 snd_soc_component_write(component, reg,
2359 ((band_idx * BAND_MAX + coeff_idx)
2360 * sizeof(uint32_t) + 1) & 0x7F);
2361
2362 value |= (snd_soc_component_read32(component, b2_reg) << 8);
2363 snd_soc_component_write(component, reg,
2364 ((band_idx * BAND_MAX + coeff_idx)
2365 * sizeof(uint32_t) + 2) & 0x7F);
2366
2367 value |= (snd_soc_component_read32(component, b2_reg) << 16);
2368 snd_soc_component_write(component, reg,
2369 ((band_idx * BAND_MAX + coeff_idx)
2370 * sizeof(uint32_t) + 3) & 0x7F);
2371
2372 /* Mask bits top 2 bits since they are reserved */
2373 value |= (snd_soc_component_read32(component, b2_reg) << 24);
2374 return value;
2375 }
2376
2377 static void set_iir_band_coeff(struct snd_soc_component *component,
2378 int iir_idx, int band_idx, uint32_t value)
2379 {
2380 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2381
2382 snd_soc_component_write(component, reg, (value & 0xFF));
2383 snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
2384 snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
2385 /* Mask top 2 bits, 7-8 are reserved */
2386 snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
2387 }
2388
2389 static int wcd934x_put_iir_band_audio_mixer(
2390 struct snd_kcontrol *kcontrol,
2391 struct snd_ctl_elem_value *ucontrol)
2392 {
2393 struct snd_soc_component *component =
2394 snd_soc_kcontrol_component(kcontrol);
2395 struct wcd_iir_filter_ctl *ctl =
2396 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2397 struct soc_bytes_ext *params = &ctl->bytes_ext;
2398 int iir_idx = ctl->iir_idx;
2399 int band_idx = ctl->band_idx;
2400 u32 coeff[BAND_MAX];
2401 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2402
2403 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2404
2405 /* Mask top bit it is reserved */
2406 /* Updates addr automatically for each B2 write */
2407 snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
2408 sizeof(uint32_t)) & 0x7F);
2409
2410 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
2411 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
2412 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
2413 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
2414 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
2415
2416 return 0;
2417 }
2418
2419 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2420 struct snd_ctl_elem_value *ucontrol)
2421 {
2422 struct snd_soc_component *component =
2423 snd_soc_kcontrol_component(kcontrol);
2424 struct wcd_iir_filter_ctl *ctl =
2425 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2426 struct soc_bytes_ext *params = &ctl->bytes_ext;
2427 int iir_idx = ctl->iir_idx;
2428 int band_idx = ctl->band_idx;
2429 u32 coeff[BAND_MAX];
2430
2431 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
2432 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
2433 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
2434 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
2435 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
2436
2437 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2438
2439 return 0;
2440 }
2441
2442 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
2443 struct snd_ctl_elem_info *ucontrol)
2444 {
2445 struct wcd_iir_filter_ctl *ctl =
2446 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2447 struct soc_bytes_ext *params = &ctl->bytes_ext;
2448
2449 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2450 ucontrol->count = params->max;
2451
2452 return 0;
2453 }
2454
2455 static int wcd934x_compander_get(struct snd_kcontrol *kc,
2456 struct snd_ctl_elem_value *ucontrol)
2457 {
2458 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2459 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2460 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2461
2462 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2463
2464 return 0;
2465 }
2466
2467 static int wcd934x_compander_set(struct snd_kcontrol *kc,
2468 struct snd_ctl_elem_value *ucontrol)
2469 {
2470 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2471 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2472 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2473 int value = ucontrol->value.integer.value[0];
2474 int sel;
2475
2476 wcd->comp_enabled[comp] = value;
2477 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
2478 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
2479
2480 /* Any specific register configuration for compander */
2481 switch (comp) {
2482 case COMPANDER_1:
2483 /* Set Gain Source Select based on compander enable/disable */
2484 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
2485 WCD934X_HPH_GAIN_SRC_SEL_MASK,
2486 sel);
2487 break;
2488 case COMPANDER_2:
2489 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
2490 WCD934X_HPH_GAIN_SRC_SEL_MASK,
2491 sel);
2492 break;
2493 case COMPANDER_3:
2494 case COMPANDER_4:
2495 case COMPANDER_7:
2496 case COMPANDER_8:
2497 break;
2498 default:
2499 break;
2500 };
2501
2502 return 0;
2503 }
2504
2505 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
2506 struct snd_ctl_elem_value *ucontrol)
2507 {
2508 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2509 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2510
2511 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2512
2513 return 0;
2514 }
2515
2516 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
2517 struct snd_ctl_elem_value *ucontrol)
2518 {
2519 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2520 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2521 u32 mode_val;
2522
2523 mode_val = ucontrol->value.enumerated.item[0];
2524
2525 if (mode_val == 0) {
2526 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2527 mode_val = CLS_H_LOHIFI;
2528 }
2529 wcd->hph_mode = mode_val;
2530
2531 return 0;
2532 }
2533
2534 static int slim_rx_mux_get(struct snd_kcontrol *kc,
2535 struct snd_ctl_elem_value *ucontrol)
2536 {
2537 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
2538 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2539 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
2540
2541 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
2542
2543 return 0;
2544 }
2545
2546 static int slim_rx_mux_put(struct snd_kcontrol *kc,
2547 struct snd_ctl_elem_value *ucontrol)
2548 {
2549 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2550 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
2551 struct soc_enum *e = (struct soc_enum *)kc->private_value;
2552 struct snd_soc_dapm_update *update = NULL;
2553 u32 port_id = w->shift;
2554
2555 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
2556 return 0;
2557
2558 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
2559
2560 switch (wcd->rx_port_value[port_id]) {
2561 case 0:
2562 list_del_init(&wcd->rx_chs[port_id].list);
2563 break;
2564 case 1:
2565 list_add_tail(&wcd->rx_chs[port_id].list,
2566 &wcd->dai[AIF1_PB].slim_ch_list);
2567 break;
2568 case 2:
2569 list_add_tail(&wcd->rx_chs[port_id].list,
2570 &wcd->dai[AIF2_PB].slim_ch_list);
2571 break;
2572 case 3:
2573 list_add_tail(&wcd->rx_chs[port_id].list,
2574 &wcd->dai[AIF3_PB].slim_ch_list);
2575 break;
2576 case 4:
2577 list_add_tail(&wcd->rx_chs[port_id].list,
2578 &wcd->dai[AIF4_PB].slim_ch_list);
2579 break;
2580 default:
2581 dev_err(wcd->dev, "Unknown AIF %d\n",
2582 wcd->rx_port_value[port_id]);
2583 goto err;
2584 }
2585
2586 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
2587 e, update);
2588
2589 return 0;
2590 err:
2591 return -EINVAL;
2592 }
2593
2594 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
2595 struct snd_ctl_elem_value *ucontrol)
2596 {
2597 struct soc_enum *e = (struct soc_enum *)kc->private_value;
2598 struct snd_soc_component *component;
2599 int reg, val, ret;
2600
2601 component = snd_soc_dapm_kcontrol_component(kc);
2602 val = ucontrol->value.enumerated.item[0];
2603 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
2604 reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
2605 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
2606 reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
2607 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
2608 reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
2609 else
2610 return -EINVAL;
2611
2612 /* Set Look Ahead Delay */
2613 if (val)
2614 snd_soc_component_update_bits(component, reg,
2615 WCD934X_RX_DLY_ZN_EN_MASK,
2616 WCD934X_RX_DLY_ZN_ENABLE);
2617 else
2618 snd_soc_component_update_bits(component, reg,
2619 WCD934X_RX_DLY_ZN_EN_MASK,
2620 WCD934X_RX_DLY_ZN_DISABLE);
2621
2622 ret = snd_soc_dapm_put_enum_double(kc, ucontrol);
2623
2624 return ret;
2625 }
2626
2627 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
2628 struct snd_ctl_elem_value *ucontrol)
2629 {
2630 struct snd_soc_component *comp;
2631 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2632 unsigned int val;
2633 u16 mic_sel_reg = 0;
2634 u8 mic_sel;
2635
2636 comp = snd_soc_dapm_kcontrol_component(kcontrol);
2637
2638 val = ucontrol->value.enumerated.item[0];
2639 if (val > e->items - 1)
2640 return -EINVAL;
2641
2642 switch (e->reg) {
2643 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
2644 if (e->shift_l == 0)
2645 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
2646 else if (e->shift_l == 2)
2647 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
2648 else if (e->shift_l == 4)
2649 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
2650 break;
2651 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
2652 if (e->shift_l == 0)
2653 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
2654 else if (e->shift_l == 2)
2655 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
2656 break;
2657 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
2658 if (e->shift_l == 0)
2659 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
2660 else if (e->shift_l == 2)
2661 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
2662 break;
2663 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
2664 if (e->shift_l == 0)
2665 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
2666 else if (e->shift_l == 2)
2667 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
2668 break;
2669 default:
2670 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
2671 __func__, e->reg);
2672 return -EINVAL;
2673 }
2674
2675 /* ADC: 0, DMIC: 1 */
2676 mic_sel = val ? 0x0 : 0x1;
2677 if (mic_sel_reg)
2678 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
2679 mic_sel << 7);
2680
2681 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
2682 }
2683
2684 static const struct snd_kcontrol_new rx_int0_2_mux =
2685 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
2686
2687 static const struct snd_kcontrol_new rx_int1_2_mux =
2688 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
2689
2690 static const struct snd_kcontrol_new rx_int2_2_mux =
2691 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
2692
2693 static const struct snd_kcontrol_new rx_int3_2_mux =
2694 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
2695
2696 static const struct snd_kcontrol_new rx_int4_2_mux =
2697 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
2698
2699 static const struct snd_kcontrol_new rx_int7_2_mux =
2700 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
2701
2702 static const struct snd_kcontrol_new rx_int8_2_mux =
2703 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
2704
2705 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
2706 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
2707
2708 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
2709 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
2710
2711 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
2712 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
2713
2714 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
2715 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
2716
2717 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
2718 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
2719
2720 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
2721 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
2722
2723 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
2724 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
2725
2726 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
2727 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
2728
2729 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
2730 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
2731
2732 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
2733 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
2734
2735 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
2736 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
2737
2738 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
2739 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
2740
2741 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
2742 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
2743
2744 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
2745 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
2746
2747 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
2748 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
2749
2750 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
2751 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
2752
2753 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
2754 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
2755
2756 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
2757 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
2758
2759 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
2760 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
2761
2762 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
2763 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
2764
2765 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
2766 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
2767
2768 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
2769 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
2770
2771 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
2772 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
2773
2774 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
2775 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
2776
2777 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
2778 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
2779
2780 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
2781 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
2782
2783 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
2784 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
2785
2786 static const struct snd_kcontrol_new iir0_inp0_mux =
2787 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
2788 static const struct snd_kcontrol_new iir0_inp1_mux =
2789 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
2790 static const struct snd_kcontrol_new iir0_inp2_mux =
2791 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
2792 static const struct snd_kcontrol_new iir0_inp3_mux =
2793 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
2794
2795 static const struct snd_kcontrol_new iir1_inp0_mux =
2796 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
2797 static const struct snd_kcontrol_new iir1_inp1_mux =
2798 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
2799 static const struct snd_kcontrol_new iir1_inp2_mux =
2800 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
2801 static const struct snd_kcontrol_new iir1_inp3_mux =
2802 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
2803
2804 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
2805 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
2806 slim_rx_mux_get, slim_rx_mux_put),
2807 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
2808 slim_rx_mux_get, slim_rx_mux_put),
2809 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
2810 slim_rx_mux_get, slim_rx_mux_put),
2811 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
2812 slim_rx_mux_get, slim_rx_mux_put),
2813 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
2814 slim_rx_mux_get, slim_rx_mux_put),
2815 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
2816 slim_rx_mux_get, slim_rx_mux_put),
2817 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
2818 slim_rx_mux_get, slim_rx_mux_put),
2819 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
2820 slim_rx_mux_get, slim_rx_mux_put),
2821 };
2822
2823 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
2824 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
2825 };
2826
2827 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
2828 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
2829 };
2830
2831 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
2832 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
2833 };
2834
2835 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
2836 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
2837 };
2838
2839 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
2840 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
2841 snd_soc_dapm_get_enum_double,
2842 wcd934x_int_dem_inp_mux_put);
2843
2844 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
2845 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
2846 snd_soc_dapm_get_enum_double,
2847 wcd934x_int_dem_inp_mux_put);
2848
2849 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
2850 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
2851 snd_soc_dapm_get_enum_double,
2852 wcd934x_int_dem_inp_mux_put);
2853
2854 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
2855 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
2856
2857 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
2858 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
2859
2860 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
2861 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
2862
2863 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
2864 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
2865
2866 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
2867 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
2868
2869 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
2870 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
2871
2872 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
2873 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
2874
2875 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
2876 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
2877
2878 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
2879 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
2880
2881 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
2882 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
2883
2884 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
2885 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
2886
2887 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
2888 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
2889
2890 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
2891 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
2892
2893 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
2894 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
2895
2896 static const struct snd_kcontrol_new tx_dmic_mux0 =
2897 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
2898
2899 static const struct snd_kcontrol_new tx_dmic_mux1 =
2900 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
2901
2902 static const struct snd_kcontrol_new tx_dmic_mux2 =
2903 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
2904
2905 static const struct snd_kcontrol_new tx_dmic_mux3 =
2906 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
2907
2908 static const struct snd_kcontrol_new tx_dmic_mux4 =
2909 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
2910
2911 static const struct snd_kcontrol_new tx_dmic_mux5 =
2912 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
2913
2914 static const struct snd_kcontrol_new tx_dmic_mux6 =
2915 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
2916
2917 static const struct snd_kcontrol_new tx_dmic_mux7 =
2918 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
2919
2920 static const struct snd_kcontrol_new tx_dmic_mux8 =
2921 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
2922
2923 static const struct snd_kcontrol_new tx_amic_mux0 =
2924 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
2925
2926 static const struct snd_kcontrol_new tx_amic_mux1 =
2927 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
2928
2929 static const struct snd_kcontrol_new tx_amic_mux2 =
2930 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
2931
2932 static const struct snd_kcontrol_new tx_amic_mux3 =
2933 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
2934
2935 static const struct snd_kcontrol_new tx_amic_mux4 =
2936 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
2937
2938 static const struct snd_kcontrol_new tx_amic_mux5 =
2939 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
2940
2941 static const struct snd_kcontrol_new tx_amic_mux6 =
2942 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
2943
2944 static const struct snd_kcontrol_new tx_amic_mux7 =
2945 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
2946
2947 static const struct snd_kcontrol_new tx_amic_mux8 =
2948 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
2949
2950 static const struct snd_kcontrol_new tx_amic4_5 =
2951 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
2952
2953 static const struct snd_kcontrol_new tx_adc_mux0_mux =
2954 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
2955 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2956 static const struct snd_kcontrol_new tx_adc_mux1_mux =
2957 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
2958 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2959 static const struct snd_kcontrol_new tx_adc_mux2_mux =
2960 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
2961 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2962 static const struct snd_kcontrol_new tx_adc_mux3_mux =
2963 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
2964 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2965 static const struct snd_kcontrol_new tx_adc_mux4_mux =
2966 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
2967 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2968 static const struct snd_kcontrol_new tx_adc_mux5_mux =
2969 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
2970 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2971 static const struct snd_kcontrol_new tx_adc_mux6_mux =
2972 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
2973 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2974 static const struct snd_kcontrol_new tx_adc_mux7_mux =
2975 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
2976 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2977 static const struct snd_kcontrol_new tx_adc_mux8_mux =
2978 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
2979 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2980
2981 static const struct snd_kcontrol_new cdc_if_tx0_mux =
2982 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
2983 static const struct snd_kcontrol_new cdc_if_tx1_mux =
2984 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
2985 static const struct snd_kcontrol_new cdc_if_tx2_mux =
2986 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
2987 static const struct snd_kcontrol_new cdc_if_tx3_mux =
2988 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
2989 static const struct snd_kcontrol_new cdc_if_tx4_mux =
2990 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
2991 static const struct snd_kcontrol_new cdc_if_tx5_mux =
2992 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
2993 static const struct snd_kcontrol_new cdc_if_tx6_mux =
2994 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
2995 static const struct snd_kcontrol_new cdc_if_tx7_mux =
2996 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
2997 static const struct snd_kcontrol_new cdc_if_tx8_mux =
2998 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
2999 static const struct snd_kcontrol_new cdc_if_tx9_mux =
3000 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
3001 static const struct snd_kcontrol_new cdc_if_tx10_mux =
3002 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3003 static const struct snd_kcontrol_new cdc_if_tx11_mux =
3004 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3005 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3006 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3007 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3008 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3009 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3010 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3011
3012 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3013 struct snd_ctl_elem_value *ucontrol)
3014 {
3015 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3016 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3017 struct soc_mixer_control *mixer =
3018 (struct soc_mixer_control *)kc->private_value;
3019 int port_id = mixer->shift;
3020
3021 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3022
3023 return 0;
3024 }
3025
3026 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3027 struct snd_ctl_elem_value *ucontrol)
3028 {
3029 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3030 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3031 struct snd_soc_dapm_update *update = NULL;
3032 struct soc_mixer_control *mixer =
3033 (struct soc_mixer_control *)kc->private_value;
3034 int enable = ucontrol->value.integer.value[0];
3035 int dai_id = widget->shift;
3036 int port_id = mixer->shift;
3037
3038 /* only add to the list if value not set */
3039 if (enable == wcd->tx_port_value[port_id])
3040 return 0;
3041
3042 wcd->tx_port_value[port_id] = enable;
3043
3044 if (enable)
3045 list_add_tail(&wcd->tx_chs[port_id].list,
3046 &wcd->dai[dai_id].slim_ch_list);
3047 else
3048 list_del_init(&wcd->tx_chs[port_id].list);
3049
3050 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3051
3052 return 0;
3053 }
3054
3055 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3056 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3057 slim_tx_mixer_get, slim_tx_mixer_put),
3058 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3059 slim_tx_mixer_get, slim_tx_mixer_put),
3060 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3061 slim_tx_mixer_get, slim_tx_mixer_put),
3062 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3063 slim_tx_mixer_get, slim_tx_mixer_put),
3064 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3065 slim_tx_mixer_get, slim_tx_mixer_put),
3066 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3067 slim_tx_mixer_get, slim_tx_mixer_put),
3068 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3069 slim_tx_mixer_get, slim_tx_mixer_put),
3070 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3071 slim_tx_mixer_get, slim_tx_mixer_put),
3072 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3073 slim_tx_mixer_get, slim_tx_mixer_put),
3074 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3075 slim_tx_mixer_get, slim_tx_mixer_put),
3076 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3077 slim_tx_mixer_get, slim_tx_mixer_put),
3078 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3079 slim_tx_mixer_get, slim_tx_mixer_put),
3080 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3081 slim_tx_mixer_get, slim_tx_mixer_put),
3082 };
3083
3084 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3085 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3086 slim_tx_mixer_get, slim_tx_mixer_put),
3087 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3088 slim_tx_mixer_get, slim_tx_mixer_put),
3089 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3090 slim_tx_mixer_get, slim_tx_mixer_put),
3091 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3092 slim_tx_mixer_get, slim_tx_mixer_put),
3093 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3094 slim_tx_mixer_get, slim_tx_mixer_put),
3095 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3096 slim_tx_mixer_get, slim_tx_mixer_put),
3097 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3098 slim_tx_mixer_get, slim_tx_mixer_put),
3099 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3100 slim_tx_mixer_get, slim_tx_mixer_put),
3101 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3102 slim_tx_mixer_get, slim_tx_mixer_put),
3103 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3104 slim_tx_mixer_get, slim_tx_mixer_put),
3105 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3106 slim_tx_mixer_get, slim_tx_mixer_put),
3107 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3108 slim_tx_mixer_get, slim_tx_mixer_put),
3109 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3110 slim_tx_mixer_get, slim_tx_mixer_put),
3111 };
3112
3113 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3114 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3115 slim_tx_mixer_get, slim_tx_mixer_put),
3116 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3117 slim_tx_mixer_get, slim_tx_mixer_put),
3118 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3119 slim_tx_mixer_get, slim_tx_mixer_put),
3120 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3121 slim_tx_mixer_get, slim_tx_mixer_put),
3122 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3123 slim_tx_mixer_get, slim_tx_mixer_put),
3124 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3125 slim_tx_mixer_get, slim_tx_mixer_put),
3126 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3127 slim_tx_mixer_get, slim_tx_mixer_put),
3128 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3129 slim_tx_mixer_get, slim_tx_mixer_put),
3130 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3131 slim_tx_mixer_get, slim_tx_mixer_put),
3132 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3133 slim_tx_mixer_get, slim_tx_mixer_put),
3134 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3135 slim_tx_mixer_get, slim_tx_mixer_put),
3136 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3137 slim_tx_mixer_get, slim_tx_mixer_put),
3138 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3139 slim_tx_mixer_get, slim_tx_mixer_put),
3140 };
3141
3142 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3143 /* Gain Controls */
3144 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3145 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3146 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3147 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3148 3, 16, 1, line_gain),
3149 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3150 3, 16, 1, line_gain),
3151
3152 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3153 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3154 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3155 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3156
3157 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3158 -84, 40, digital_gain), /* -84dB min - 40dB max */
3159 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3160 -84, 40, digital_gain),
3161 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3162 -84, 40, digital_gain),
3163 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3164 -84, 40, digital_gain),
3165 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3166 -84, 40, digital_gain),
3167 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
3168 -84, 40, digital_gain),
3169 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
3170 -84, 40, digital_gain),
3171 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
3172 WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
3173 -84, 40, digital_gain),
3174 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
3175 WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
3176 -84, 40, digital_gain),
3177 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
3178 WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
3179 -84, 40, digital_gain),
3180 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
3181 WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
3182 -84, 40, digital_gain),
3183 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
3184 WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
3185 -84, 40, digital_gain),
3186 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
3187 WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
3188 -84, 40, digital_gain),
3189 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
3190 WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
3191 -84, 40, digital_gain),
3192
3193 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
3194 -84, 40, digital_gain),
3195 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
3196 -84, 40, digital_gain),
3197 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
3198 -84, 40, digital_gain),
3199 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
3200 -84, 40, digital_gain),
3201 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
3202 -84, 40, digital_gain),
3203 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
3204 -84, 40, digital_gain),
3205 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
3206 -84, 40, digital_gain),
3207 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
3208 -84, 40, digital_gain),
3209 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
3210 -84, 40, digital_gain),
3211
3212 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
3213 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3214 digital_gain),
3215 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
3216 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3217 digital_gain),
3218 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
3219 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3220 digital_gain),
3221 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
3222 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3223 digital_gain),
3224 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
3225 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3226 digital_gain),
3227 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
3228 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3229 digital_gain),
3230 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
3231 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3232 digital_gain),
3233 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
3234 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3235 digital_gain),
3236
3237 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
3238 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
3239 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
3240 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
3241 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
3242 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
3243 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
3244 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
3245 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
3246
3247 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
3248 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
3249 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
3250 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
3251 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
3252 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
3253 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
3254 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
3255 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
3256 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
3257 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
3258 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
3259 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
3260 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
3261
3262 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
3263 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
3264
3265 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3266 0, 1, 0),
3267 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3268 1, 1, 0),
3269 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3270 2, 1, 0),
3271 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3272 3, 1, 0),
3273 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3274 4, 1, 0),
3275 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3276 0, 1, 0),
3277 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3278 1, 1, 0),
3279 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3280 2, 1, 0),
3281 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3282 3, 1, 0),
3283 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3284 4, 1, 0),
3285 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
3286 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
3287 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
3288 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
3289 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
3290
3291 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
3292 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
3293 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
3294 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
3295 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
3296
3297 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
3298 wcd934x_compander_get, wcd934x_compander_set),
3299 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
3300 wcd934x_compander_get, wcd934x_compander_set),
3301 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
3302 wcd934x_compander_get, wcd934x_compander_set),
3303 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
3304 wcd934x_compander_get, wcd934x_compander_set),
3305 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
3306 wcd934x_compander_get, wcd934x_compander_set),
3307 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
3308 wcd934x_compander_get, wcd934x_compander_set),
3309 };
3310
3311 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
3312 struct snd_soc_component *component)
3313 {
3314 int port_num = 0;
3315 unsigned short reg = 0;
3316 unsigned int val = 0;
3317 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3318 struct wcd934x_slim_ch *ch;
3319
3320 list_for_each_entry(ch, &dai->slim_ch_list, list) {
3321 if (ch->port >= WCD934X_RX_START) {
3322 port_num = ch->port - WCD934X_RX_START;
3323 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3324 } else {
3325 port_num = ch->port;
3326 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3327 }
3328
3329 regmap_read(wcd->if_regmap, reg, &val);
3330 if (!(val & BIT(port_num % 8)))
3331 regmap_write(wcd->if_regmap, reg,
3332 val | BIT(port_num % 8));
3333 }
3334 }
3335
3336 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
3337 struct snd_kcontrol *kc, int event)
3338 {
3339 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3340 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
3341 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3342
3343 switch (event) {
3344 case SND_SOC_DAPM_POST_PMU:
3345 wcd934x_codec_enable_int_port(dai, comp);
3346 break;
3347 }
3348
3349 return 0;
3350 }
3351
3352 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
3353 u16 interp_idx, int event)
3354 {
3355 u16 hd2_scale_reg;
3356 u16 hd2_enable_reg = 0;
3357
3358 switch (interp_idx) {
3359 case INTERP_HPHL:
3360 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
3361 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3362 break;
3363 case INTERP_HPHR:
3364 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
3365 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3366 break;
3367 default:
3368 return;
3369 }
3370
3371 if (SND_SOC_DAPM_EVENT_ON(event)) {
3372 snd_soc_component_update_bits(component, hd2_scale_reg,
3373 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3374 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
3375 snd_soc_component_update_bits(component, hd2_enable_reg,
3376 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3377 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
3378 }
3379
3380 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3381 snd_soc_component_update_bits(component, hd2_enable_reg,
3382 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3383 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
3384 snd_soc_component_update_bits(component, hd2_scale_reg,
3385 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3386 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3387 }
3388 }
3389
3390 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
3391 u16 interp_idx, int event)
3392 {
3393 u8 hph_dly_mask;
3394 u16 hph_lut_bypass_reg = 0;
3395 u16 hph_comp_ctrl7 = 0;
3396
3397 switch (interp_idx) {
3398 case INTERP_HPHL:
3399 hph_dly_mask = 1;
3400 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
3401 hph_comp_ctrl7 = WCD934X_CDC_COMPANDER1_CTL7;
3402 break;
3403 case INTERP_HPHR:
3404 hph_dly_mask = 2;
3405 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
3406 hph_comp_ctrl7 = WCD934X_CDC_COMPANDER2_CTL7;
3407 break;
3408 default:
3409 return;
3410 }
3411
3412 if (SND_SOC_DAPM_EVENT_ON(event)) {
3413 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3414 hph_dly_mask, 0x0);
3415 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3416 WCD934X_HPH_LUT_BYPASS_MASK,
3417 WCD934X_HPH_LUT_BYPASS_ENABLE);
3418 }
3419
3420 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3421 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3422 hph_dly_mask, hph_dly_mask);
3423 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3424 WCD934X_HPH_LUT_BYPASS_MASK,
3425 WCD934X_HPH_LUT_BYPASS_DISABLE);
3426 }
3427 }
3428
3429 static int wcd934x_config_compander(struct snd_soc_component *comp,
3430 int interp_n, int event)
3431 {
3432 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3433 int compander;
3434 u16 comp_ctl0_reg, rx_path_cfg0_reg;
3435
3436 /* EAR does not have compander */
3437 if (!interp_n)
3438 return 0;
3439
3440 compander = interp_n - 1;
3441 if (!wcd->comp_enabled[compander])
3442 return 0;
3443
3444 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
3445 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
3446
3447 switch (event) {
3448 case SND_SOC_DAPM_PRE_PMU:
3449 /* Enable Compander Clock */
3450 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3451 WCD934X_COMP_CLK_EN_MASK,
3452 WCD934X_COMP_CLK_ENABLE);
3453 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3454 WCD934X_COMP_SOFT_RST_MASK,
3455 WCD934X_COMP_SOFT_RST_ENABLE);
3456 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3457 WCD934X_COMP_SOFT_RST_MASK,
3458 WCD934X_COMP_SOFT_RST_DISABLE);
3459 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3460 WCD934X_HPH_CMP_EN_MASK,
3461 WCD934X_HPH_CMP_ENABLE);
3462 break;
3463 case SND_SOC_DAPM_POST_PMD:
3464 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3465 WCD934X_HPH_CMP_EN_MASK,
3466 WCD934X_HPH_CMP_DISABLE);
3467 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3468 WCD934X_COMP_HALT_MASK,
3469 WCD934X_COMP_HALT);
3470 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3471 WCD934X_COMP_SOFT_RST_MASK,
3472 WCD934X_COMP_SOFT_RST_ENABLE);
3473 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3474 WCD934X_COMP_SOFT_RST_MASK,
3475 WCD934X_COMP_SOFT_RST_DISABLE);
3476 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3477 WCD934X_COMP_CLK_EN_MASK, 0x0);
3478 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3479 WCD934X_COMP_SOFT_RST_MASK, 0x0);
3480 break;
3481 }
3482
3483 return 0;
3484 }
3485
3486 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
3487 struct snd_kcontrol *kc, int event)
3488 {
3489 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3490 int interp_idx = w->shift;
3491 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
3492
3493 switch (event) {
3494 case SND_SOC_DAPM_PRE_PMU:
3495 /* Clk enable */
3496 snd_soc_component_update_bits(comp, main_reg,
3497 WCD934X_RX_CLK_EN_MASK,
3498 WCD934X_RX_CLK_ENABLE);
3499 wcd934x_codec_hd2_control(comp, interp_idx, event);
3500 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3501 wcd934x_config_compander(comp, interp_idx, event);
3502 break;
3503 case SND_SOC_DAPM_POST_PMD:
3504 wcd934x_config_compander(comp, interp_idx, event);
3505 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3506 wcd934x_codec_hd2_control(comp, interp_idx, event);
3507 /* Clk Disable */
3508 snd_soc_component_update_bits(comp, main_reg,
3509 WCD934X_RX_CLK_EN_MASK, 0);
3510 /* Reset enable and disable */
3511 snd_soc_component_update_bits(comp, main_reg,
3512 WCD934X_RX_RESET_MASK,
3513 WCD934X_RX_RESET_ENABLE);
3514 snd_soc_component_update_bits(comp, main_reg,
3515 WCD934X_RX_RESET_MASK,
3516 WCD934X_RX_RESET_DISABLE);
3517 /* Reset rate to 48K*/
3518 snd_soc_component_update_bits(comp, main_reg,
3519 WCD934X_RX_PCM_RATE_MASK,
3520 WCD934X_RX_PCM_RATE_F_48K);
3521 break;
3522 }
3523
3524 return 0;
3525 }
3526
3527 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3528 struct snd_kcontrol *kc, int event)
3529 {
3530 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3531 int offset_val = 0;
3532 u16 gain_reg, mix_reg;
3533 int val = 0;
3534
3535 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
3536 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3537 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
3538 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3539
3540 switch (event) {
3541 case SND_SOC_DAPM_PRE_PMU:
3542 /* Clk enable */
3543 snd_soc_component_update_bits(comp, mix_reg,
3544 WCD934X_CDC_RX_MIX_CLK_EN_MASK,
3545 WCD934X_CDC_RX_MIX_CLK_ENABLE);
3546 break;
3547
3548 case SND_SOC_DAPM_POST_PMU:
3549 val = snd_soc_component_read32(comp, gain_reg);
3550 val += offset_val;
3551 snd_soc_component_write(comp, gain_reg, val);
3552 break;
3553 };
3554
3555 return 0;
3556 }
3557
3558 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
3559 struct snd_kcontrol *kcontrol, int event)
3560 {
3561 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3562 int reg = w->reg;
3563
3564 switch (event) {
3565 case SND_SOC_DAPM_POST_PMU:
3566 /* B1 GAIN */
3567 snd_soc_component_write(comp, reg,
3568 snd_soc_component_read32(comp, reg));
3569 /* B2 GAIN */
3570 reg++;
3571 snd_soc_component_write(comp, reg,
3572 snd_soc_component_read32(comp, reg));
3573 /* B3 GAIN */
3574 reg++;
3575 snd_soc_component_write(comp, reg,
3576 snd_soc_component_read32(comp, reg));
3577 /* B4 GAIN */
3578 reg++;
3579 snd_soc_component_write(comp, reg,
3580 snd_soc_component_read32(comp, reg));
3581 /* B5 GAIN */
3582 reg++;
3583 snd_soc_component_write(comp, reg,
3584 snd_soc_component_read32(comp, reg));
3585 break;
3586 default:
3587 break;
3588 }
3589 return 0;
3590 }
3591
3592 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
3593 struct snd_kcontrol *kcontrol,
3594 int event)
3595 {
3596 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3597 u16 gain_reg;
3598
3599 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
3600 WCD934X_RX_PATH_CTL_OFFSET);
3601
3602 switch (event) {
3603 case SND_SOC_DAPM_POST_PMU:
3604 snd_soc_component_write(comp, gain_reg,
3605 snd_soc_component_read32(comp, gain_reg));
3606 break;
3607 };
3608
3609 return 0;
3610 }
3611
3612 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3613 struct snd_kcontrol *kc, int event)
3614 {
3615 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3616 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3617
3618 switch (event) {
3619 case SND_SOC_DAPM_PRE_PMU:
3620 /* Disable AutoChop timer during power up */
3621 snd_soc_component_update_bits(comp,
3622 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3623 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3624 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3625 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3626
3627 break;
3628 case SND_SOC_DAPM_POST_PMD:
3629 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3630 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3631 break;
3632 };
3633
3634 return 0;
3635 }
3636
3637 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3638 struct snd_kcontrol *kcontrol,
3639 int event)
3640 {
3641 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3642 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3643 int hph_mode = wcd->hph_mode;
3644 u8 dem_inp;
3645
3646 switch (event) {
3647 case SND_SOC_DAPM_PRE_PMU:
3648 /* Read DEM INP Select */
3649 dem_inp = snd_soc_component_read32(comp,
3650 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
3651
3652 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3653 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3654 return -EINVAL;
3655 }
3656 if (hph_mode != CLS_H_LP)
3657 /* Ripple freq control enable */
3658 snd_soc_component_update_bits(comp,
3659 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3660 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3661 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3662 /* Disable AutoChop timer during power up */
3663 snd_soc_component_update_bits(comp,
3664 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3665 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3666 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3667 WCD_CLSH_STATE_HPHL, hph_mode);
3668
3669 break;
3670 case SND_SOC_DAPM_POST_PMD:
3671 /* 1000us required as per HW requirement */
3672 usleep_range(1000, 1100);
3673 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3674 WCD_CLSH_STATE_HPHL, hph_mode);
3675 if (hph_mode != CLS_H_LP)
3676 /* Ripple freq control disable */
3677 snd_soc_component_update_bits(comp,
3678 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3679 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3680
3681 break;
3682 default:
3683 break;
3684 };
3685
3686 return 0;
3687 }
3688
3689 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3690 struct snd_kcontrol *kcontrol,
3691 int event)
3692 {
3693 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3694 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3695 int hph_mode = wcd->hph_mode;
3696 u8 dem_inp;
3697
3698 switch (event) {
3699 case SND_SOC_DAPM_PRE_PMU:
3700 dem_inp = snd_soc_component_read32(comp,
3701 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
3702 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3703 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3704 return -EINVAL;
3705 }
3706 if (hph_mode != CLS_H_LP)
3707 /* Ripple freq control enable */
3708 snd_soc_component_update_bits(comp,
3709 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3710 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3711 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3712 /* Disable AutoChop timer during power up */
3713 snd_soc_component_update_bits(comp,
3714 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3715 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3716 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3717 WCD_CLSH_STATE_HPHR,
3718 hph_mode);
3719 break;
3720 case SND_SOC_DAPM_POST_PMD:
3721 /* 1000us required as per HW requirement */
3722 usleep_range(1000, 1100);
3723
3724 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3725 WCD_CLSH_STATE_HPHR, hph_mode);
3726 if (hph_mode != CLS_H_LP)
3727 /* Ripple freq control disable */
3728 snd_soc_component_update_bits(comp,
3729 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3730 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3731 break;
3732 default:
3733 break;
3734 };
3735
3736 return 0;
3737 }
3738
3739 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3740 struct snd_kcontrol *kc, int event)
3741 {
3742 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3743 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3744
3745 switch (event) {
3746 case SND_SOC_DAPM_PRE_PMU:
3747 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3748 WCD_CLSH_STATE_LO, CLS_AB);
3749 break;
3750 case SND_SOC_DAPM_POST_PMD:
3751 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3752 WCD_CLSH_STATE_LO, CLS_AB);
3753 break;
3754 }
3755
3756 return 0;
3757 }
3758
3759 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3760 struct snd_kcontrol *kcontrol,
3761 int event)
3762 {
3763 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3764
3765 switch (event) {
3766 case SND_SOC_DAPM_POST_PMU:
3767 /*
3768 * 7ms sleep is required after PA is enabled as per
3769 * HW requirement. If compander is disabled, then
3770 * 20ms delay is needed.
3771 */
3772 usleep_range(20000, 20100);
3773
3774 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3775 WCD934X_HPH_OCP_DET_MASK,
3776 WCD934X_HPH_OCP_DET_ENABLE);
3777 /* Remove Mute on primary path */
3778 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3779 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3780 0);
3781 /* Enable GM3 boost */
3782 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3783 WCD934X_HPH_GM3_BOOST_EN_MASK,
3784 WCD934X_HPH_GM3_BOOST_ENABLE);
3785 /* Enable AutoChop timer at the end of power up */
3786 snd_soc_component_update_bits(comp,
3787 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3788 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3789 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3790 /* Remove mix path mute */
3791 snd_soc_component_update_bits(comp,
3792 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3793 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
3794 break;
3795 case SND_SOC_DAPM_PRE_PMD:
3796 /* Enable DSD Mute before PA disable */
3797 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3798 WCD934X_HPH_OCP_DET_MASK,
3799 WCD934X_HPH_OCP_DET_DISABLE);
3800 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3801 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3802 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3803 snd_soc_component_update_bits(comp,
3804 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3805 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3806 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3807 break;
3808 case SND_SOC_DAPM_POST_PMD:
3809 /*
3810 * 5ms sleep is required after PA disable. If compander is
3811 * disabled, then 20ms delay is needed after PA disable.
3812 */
3813 usleep_range(20000, 20100);
3814 break;
3815 };
3816
3817 return 0;
3818 }
3819
3820 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3821 struct snd_kcontrol *kcontrol,
3822 int event)
3823 {
3824 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3825
3826 switch (event) {
3827 case SND_SOC_DAPM_POST_PMU:
3828 /*
3829 * 7ms sleep is required after PA is enabled as per
3830 * HW requirement. If compander is disabled, then
3831 * 20ms delay is needed.
3832 */
3833 usleep_range(20000, 20100);
3834 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3835 WCD934X_HPH_OCP_DET_MASK,
3836 WCD934X_HPH_OCP_DET_ENABLE);
3837 /* Remove mute */
3838 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3839 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3840 0);
3841 /* Enable GM3 boost */
3842 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3843 WCD934X_HPH_GM3_BOOST_EN_MASK,
3844 WCD934X_HPH_GM3_BOOST_ENABLE);
3845 /* Enable AutoChop timer at the end of power up */
3846 snd_soc_component_update_bits(comp,
3847 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3848 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3849 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3850 /* Remove mix path mute if it is enabled */
3851 if ((snd_soc_component_read32(comp,
3852 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
3853 snd_soc_component_update_bits(comp,
3854 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3855 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3856 WCD934X_CDC_RX_PGA_MUTE_DISABLE);
3857 break;
3858 case SND_SOC_DAPM_PRE_PMD:
3859 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3860 WCD934X_HPH_OCP_DET_MASK,
3861 WCD934X_HPH_OCP_DET_DISABLE);
3862 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3863 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3864 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3865 snd_soc_component_update_bits(comp,
3866 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3867 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3868 WCD934X_CDC_RX_PGA_MUTE_ENABLE);
3869 break;
3870 case SND_SOC_DAPM_POST_PMD:
3871 /*
3872 * 5ms sleep is required after PA disable. If compander is
3873 * disabled, then 20ms delay is needed after PA disable.
3874 */
3875 usleep_range(20000, 20100);
3876 break;
3877 };
3878
3879 return 0;
3880 }
3881
3882 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
3883 unsigned int dmic,
3884 struct wcd934x_codec *wcd)
3885 {
3886 u8 tx_stream_fs;
3887 u8 adc_mux_index = 0, adc_mux_sel = 0;
3888 bool dec_found = false;
3889 u16 adc_mux_ctl_reg, tx_fs_reg;
3890 u32 dmic_fs;
3891
3892 while (dec_found == 0 && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
3893 if (adc_mux_index < 4) {
3894 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
3895 (adc_mux_index * 2);
3896 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
3897 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
3898 adc_mux_index - 4;
3899 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
3900 ++adc_mux_index;
3901 continue;
3902 }
3903 adc_mux_sel = ((snd_soc_component_read32(comp, adc_mux_ctl_reg)
3904 & 0xF8) >> 3) - 1;
3905
3906 if (adc_mux_sel == dmic) {
3907 dec_found = true;
3908 break;
3909 }
3910
3911 ++adc_mux_index;
3912 }
3913
3914 if (dec_found && adc_mux_index <= 8) {
3915 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
3916 tx_stream_fs = snd_soc_component_read32(comp, tx_fs_reg) & 0x0F;
3917 if (tx_stream_fs <= 4) {
3918 if (wcd->dmic_sample_rate <=
3919 WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
3920 dmic_fs = wcd->dmic_sample_rate;
3921 else
3922 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ;
3923 } else
3924 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
3925 } else {
3926 dmic_fs = wcd->dmic_sample_rate;
3927 }
3928
3929 return dmic_fs;
3930 }
3931
3932 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
3933 u32 mclk_rate, u32 dmic_clk_rate)
3934 {
3935 u32 div_factor;
3936 u8 dmic_ctl_val;
3937
3938 /* Default value to return in case of error */
3939 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
3940 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
3941 else
3942 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
3943
3944 if (dmic_clk_rate == 0) {
3945 dev_err(comp->dev,
3946 "%s: dmic_sample_rate cannot be 0\n",
3947 __func__);
3948 goto done;
3949 }
3950
3951 div_factor = mclk_rate / dmic_clk_rate;
3952 switch (div_factor) {
3953 case 2:
3954 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
3955 break;
3956 case 3:
3957 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
3958 break;
3959 case 4:
3960 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
3961 break;
3962 case 6:
3963 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
3964 break;
3965 case 8:
3966 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
3967 break;
3968 case 16:
3969 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
3970 break;
3971 default:
3972 dev_err(comp->dev,
3973 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
3974 __func__, div_factor, mclk_rate, dmic_clk_rate);
3975 break;
3976 }
3977
3978 done:
3979 return dmic_ctl_val;
3980 }
3981
3982 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
3983 struct snd_kcontrol *kcontrol, int event)
3984 {
3985 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3986 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3987 u8 dmic_clk_en = 0x01;
3988 u16 dmic_clk_reg;
3989 s32 *dmic_clk_cnt;
3990 u8 dmic_rate_val, dmic_rate_shift = 1;
3991 unsigned int dmic;
3992 u32 dmic_sample_rate;
3993 int ret;
3994 char *wname;
3995
3996 wname = strpbrk(w->name, "012345");
3997 if (!wname) {
3998 dev_err(comp->dev, "%s: widget not found\n", __func__);
3999 return -EINVAL;
4000 }
4001
4002 ret = kstrtouint(wname, 10, &dmic);
4003 if (ret < 0) {
4004 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4005 __func__);
4006 return -EINVAL;
4007 }
4008
4009 switch (dmic) {
4010 case 0:
4011 case 1:
4012 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4013 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4014 break;
4015 case 2:
4016 case 3:
4017 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4018 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4019 break;
4020 case 4:
4021 case 5:
4022 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4023 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4024 break;
4025 default:
4026 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4027 __func__);
4028 return -EINVAL;
4029 };
4030
4031 switch (event) {
4032 case SND_SOC_DAPM_PRE_PMU:
4033 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4034 wcd);
4035 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4036 dmic_sample_rate);
4037 (*dmic_clk_cnt)++;
4038 if (*dmic_clk_cnt == 1) {
4039 dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4040 snd_soc_component_update_bits(comp, dmic_clk_reg,
4041 WCD934X_DMIC_RATE_MASK,
4042 dmic_rate_val);
4043 snd_soc_component_update_bits(comp, dmic_clk_reg,
4044 dmic_clk_en, dmic_clk_en);
4045 }
4046
4047 break;
4048 case SND_SOC_DAPM_POST_PMD:
4049 (*dmic_clk_cnt)--;
4050 if (*dmic_clk_cnt == 0)
4051 snd_soc_component_update_bits(comp, dmic_clk_reg,
4052 dmic_clk_en, 0);
4053 break;
4054 };
4055
4056 return 0;
4057 }
4058
4059 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4060 int adc_mux_n)
4061 {
4062 u16 mask, shift, adc_mux_in_reg;
4063 u16 amic_mux_sel_reg;
4064 bool is_amic;
4065
4066 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4067 adc_mux_n == WCD934X_INVALID_ADC_MUX)
4068 return 0;
4069
4070 if (adc_mux_n < 3) {
4071 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4072 adc_mux_n;
4073 mask = 0x03;
4074 shift = 0;
4075 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4076 2 * adc_mux_n;
4077 } else if (adc_mux_n < 4) {
4078 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4079 mask = 0x03;
4080 shift = 0;
4081 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4082 2 * adc_mux_n;
4083 } else if (adc_mux_n < 7) {
4084 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4085 (adc_mux_n - 4);
4086 mask = 0x0C;
4087 shift = 2;
4088 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4089 adc_mux_n - 4;
4090 } else if (adc_mux_n < 8) {
4091 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4092 mask = 0x0C;
4093 shift = 2;
4094 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4095 adc_mux_n - 4;
4096 } else if (adc_mux_n < 12) {
4097 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4098 ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4099 (adc_mux_n - 9));
4100 mask = 0x30;
4101 shift = 4;
4102 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4103 adc_mux_n - 4;
4104 } else if (adc_mux_n < 13) {
4105 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4106 mask = 0x30;
4107 shift = 4;
4108 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4109 adc_mux_n - 4;
4110 } else {
4111 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4112 mask = 0xC0;
4113 shift = 6;
4114 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4115 adc_mux_n - 4;
4116 }
4117
4118 is_amic = (((snd_soc_component_read32(comp, adc_mux_in_reg)
4119 & mask) >> shift) == 1);
4120 if (!is_amic)
4121 return 0;
4122
4123 return snd_soc_component_read32(comp, amic_mux_sel_reg) & 0x07;
4124 }
4125
4126 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4127 int amic)
4128 {
4129 u16 pwr_level_reg = 0;
4130
4131 switch (amic) {
4132 case 1:
4133 case 2:
4134 pwr_level_reg = WCD934X_ANA_AMIC1;
4135 break;
4136
4137 case 3:
4138 case 4:
4139 pwr_level_reg = WCD934X_ANA_AMIC3;
4140 break;
4141 default:
4142 break;
4143 }
4144
4145 return pwr_level_reg;
4146 }
4147
4148 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4149 struct snd_kcontrol *kcontrol, int event)
4150 {
4151 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4152 unsigned int decimator;
4153 char *dec_adc_mux_name = NULL;
4154 char *widget_name = NULL;
4155 char *wname;
4156 int ret = 0, amic_n;
4157 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4158 u16 tx_gain_ctl_reg;
4159 char *dec;
4160 u8 hpf_coff_freq;
4161
4162 widget_name = kstrndup(w->name, 15, GFP_KERNEL);
4163 if (!widget_name)
4164 return -ENOMEM;
4165
4166 wname = widget_name;
4167 dec_adc_mux_name = strsep(&widget_name, " ");
4168 if (!dec_adc_mux_name) {
4169 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4170 __func__, w->name);
4171 ret = -EINVAL;
4172 goto out;
4173 }
4174 dec_adc_mux_name = widget_name;
4175
4176 dec = strpbrk(dec_adc_mux_name, "012345678");
4177 if (!dec) {
4178 dev_err(comp->dev, "%s: decimator index not found\n",
4179 __func__);
4180 ret = -EINVAL;
4181 goto out;
4182 }
4183
4184 ret = kstrtouint(dec, 10, &decimator);
4185 if (ret < 0) {
4186 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4187 __func__, wname);
4188 ret = -EINVAL;
4189 goto out;
4190 }
4191
4192 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
4193 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
4194 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
4195 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
4196
4197 switch (event) {
4198 case SND_SOC_DAPM_PRE_PMU:
4199 amic_n = wcd934x_codec_find_amic_input(comp, decimator);
4200 if (amic_n)
4201 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
4202 amic_n);
4203
4204 if (!pwr_level_reg)
4205 break;
4206
4207 switch ((snd_soc_component_read32(comp, pwr_level_reg) &
4208 WCD934X_AMIC_PWR_LVL_MASK) >>
4209 WCD934X_AMIC_PWR_LVL_SHIFT) {
4210 case WCD934X_AMIC_PWR_LEVEL_LP:
4211 snd_soc_component_update_bits(comp, dec_cfg_reg,
4212 WCD934X_DEC_PWR_LVL_MASK,
4213 WCD934X_DEC_PWR_LVL_LP);
4214 break;
4215 case WCD934X_AMIC_PWR_LEVEL_HP:
4216 snd_soc_component_update_bits(comp, dec_cfg_reg,
4217 WCD934X_DEC_PWR_LVL_MASK,
4218 WCD934X_DEC_PWR_LVL_HP);
4219 break;
4220 case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
4221 case WCD934X_AMIC_PWR_LEVEL_HYBRID:
4222 default:
4223 snd_soc_component_update_bits(comp, dec_cfg_reg,
4224 WCD934X_DEC_PWR_LVL_MASK,
4225 WCD934X_DEC_PWR_LVL_DF);
4226 break;
4227 }
4228 break;
4229 case SND_SOC_DAPM_POST_PMU:
4230 hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
4231 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4232 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4233 snd_soc_component_update_bits(comp, dec_cfg_reg,
4234 TX_HPF_CUT_OFF_FREQ_MASK,
4235 CF_MIN_3DB_150HZ << 5);
4236 snd_soc_component_update_bits(comp, hpf_gate_reg,
4237 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4238 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4239 /*
4240 * Minimum 1 clk cycle delay is required as per
4241 * HW spec.
4242 */
4243 usleep_range(1000, 1010);
4244 snd_soc_component_update_bits(comp, hpf_gate_reg,
4245 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4246 0);
4247 }
4248 /* apply gain after decimator is enabled */
4249 snd_soc_component_write(comp, tx_gain_ctl_reg,
4250 snd_soc_component_read32(comp,
4251 tx_gain_ctl_reg));
4252 break;
4253 case SND_SOC_DAPM_PRE_PMD:
4254 hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
4255 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4256
4257 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4258 snd_soc_component_update_bits(comp, dec_cfg_reg,
4259 TX_HPF_CUT_OFF_FREQ_MASK,
4260 hpf_coff_freq << 5);
4261 snd_soc_component_update_bits(comp, hpf_gate_reg,
4262 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4263 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4264 /*
4265 * Minimum 1 clk cycle delay is required as per
4266 * HW spec.
4267 */
4268 usleep_range(1000, 1010);
4269 snd_soc_component_update_bits(comp, hpf_gate_reg,
4270 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4271 0);
4272 }
4273 break;
4274 case SND_SOC_DAPM_POST_PMD:
4275 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
4276 0x10, 0x00);
4277 snd_soc_component_update_bits(comp, dec_cfg_reg,
4278 WCD934X_DEC_PWR_LVL_MASK,
4279 WCD934X_DEC_PWR_LVL_DF);
4280 break;
4281 };
4282 out:
4283 kfree(wname);
4284 return ret;
4285 }
4286
4287 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
4288 u16 amic_reg, bool set)
4289 {
4290 u8 mask = 0x20;
4291 u8 val;
4292
4293 if (amic_reg == WCD934X_ANA_AMIC1 ||
4294 amic_reg == WCD934X_ANA_AMIC3)
4295 mask = 0x40;
4296
4297 val = set ? mask : 0x00;
4298
4299 switch (amic_reg) {
4300 case WCD934X_ANA_AMIC1:
4301 case WCD934X_ANA_AMIC2:
4302 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
4303 mask, val);
4304 break;
4305 case WCD934X_ANA_AMIC3:
4306 case WCD934X_ANA_AMIC4:
4307 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
4308 mask, val);
4309 break;
4310 default:
4311 break;
4312 }
4313 }
4314
4315 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
4316 struct snd_kcontrol *kcontrol, int event)
4317 {
4318 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4319
4320 switch (event) {
4321 case SND_SOC_DAPM_PRE_PMU:
4322 wcd934x_codec_set_tx_hold(comp, w->reg, true);
4323 break;
4324 default:
4325 break;
4326 }
4327
4328 return 0;
4329 }
4330
4331 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
4332 /* Analog Outputs */
4333 SND_SOC_DAPM_OUTPUT("EAR"),
4334 SND_SOC_DAPM_OUTPUT("HPHL"),
4335 SND_SOC_DAPM_OUTPUT("HPHR"),
4336 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4337 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4338 SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
4339 SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
4340 SND_SOC_DAPM_OUTPUT("ANC EAR"),
4341 SND_SOC_DAPM_OUTPUT("ANC HPHL"),
4342 SND_SOC_DAPM_OUTPUT("ANC HPHR"),
4343 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
4344 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
4345 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
4346 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4347 AIF1_PB, 0, wcd934x_codec_enable_slim,
4348 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4349 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4350 AIF2_PB, 0, wcd934x_codec_enable_slim,
4351 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4352 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4353 AIF3_PB, 0, wcd934x_codec_enable_slim,
4354 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4355 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4356 AIF4_PB, 0, wcd934x_codec_enable_slim,
4357 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4358
4359 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
4360 &slim_rx_mux[WCD934X_RX0]),
4361 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
4362 &slim_rx_mux[WCD934X_RX1]),
4363 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
4364 &slim_rx_mux[WCD934X_RX2]),
4365 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
4366 &slim_rx_mux[WCD934X_RX3]),
4367 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
4368 &slim_rx_mux[WCD934X_RX4]),
4369 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
4370 &slim_rx_mux[WCD934X_RX5]),
4371 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
4372 &slim_rx_mux[WCD934X_RX6]),
4373 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
4374 &slim_rx_mux[WCD934X_RX7]),
4375
4376 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4377 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4378 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4379 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4380 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4381 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4382 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4383 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4384
4385 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
4386 &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
4387 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4388 SND_SOC_DAPM_POST_PMD),
4389 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
4390 &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
4391 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4392 SND_SOC_DAPM_POST_PMD),
4393 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
4394 &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
4395 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4396 SND_SOC_DAPM_POST_PMD),
4397 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
4398 &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
4399 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4400 SND_SOC_DAPM_POST_PMD),
4401 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
4402 &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
4403 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4404 SND_SOC_DAPM_POST_PMD),
4405 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
4406 &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
4407 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4408 SND_SOC_DAPM_POST_PMD),
4409 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
4410 &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
4411 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4412 SND_SOC_DAPM_POST_PMD),
4413
4414 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4415 &rx_int0_1_mix_inp0_mux),
4416 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4417 &rx_int0_1_mix_inp1_mux),
4418 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4419 &rx_int0_1_mix_inp2_mux),
4420 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4421 &rx_int1_1_mix_inp0_mux),
4422 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4423 &rx_int1_1_mix_inp1_mux),
4424 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4425 &rx_int1_1_mix_inp2_mux),
4426 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4427 &rx_int2_1_mix_inp0_mux),
4428 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4429 &rx_int2_1_mix_inp1_mux),
4430 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4431 &rx_int2_1_mix_inp2_mux),
4432 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4433 &rx_int3_1_mix_inp0_mux),
4434 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4435 &rx_int3_1_mix_inp1_mux),
4436 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4437 &rx_int3_1_mix_inp2_mux),
4438 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4439 &rx_int4_1_mix_inp0_mux),
4440 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4441 &rx_int4_1_mix_inp1_mux),
4442 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4443 &rx_int4_1_mix_inp2_mux),
4444 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4445 &rx_int7_1_mix_inp0_mux),
4446 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4447 &rx_int7_1_mix_inp1_mux),
4448 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4449 &rx_int7_1_mix_inp2_mux),
4450 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4451 &rx_int8_1_mix_inp0_mux),
4452 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4453 &rx_int8_1_mix_inp1_mux),
4454 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4455 &rx_int8_1_mix_inp2_mux),
4456 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4457 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4458 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4459 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
4460 rx_int1_asrc_switch,
4461 ARRAY_SIZE(rx_int1_asrc_switch)),
4462 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4463 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
4464 rx_int2_asrc_switch,
4465 ARRAY_SIZE(rx_int2_asrc_switch)),
4466 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4467 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
4468 rx_int3_asrc_switch,
4469 ARRAY_SIZE(rx_int3_asrc_switch)),
4470 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4471 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
4472 rx_int4_asrc_switch,
4473 ARRAY_SIZE(rx_int4_asrc_switch)),
4474 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4475 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4476 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4477 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4478 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4479 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4480 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4481 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4482 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4483 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4484 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4485 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4486 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4487
4488 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4489 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
4490 NULL, 0, NULL, 0),
4491 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
4492 NULL, 0, NULL, 0),
4493 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
4494 0, &rx_int0_mix2_inp_mux, NULL,
4495 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4496 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
4497 0, &rx_int1_mix2_inp_mux, NULL,
4498 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4499 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
4500 0, &rx_int2_mix2_inp_mux, NULL,
4501 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4502 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
4503 0, &rx_int3_mix2_inp_mux, NULL,
4504 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4505 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
4506 0, &rx_int4_mix2_inp_mux, NULL,
4507 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4508 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
4509 0, &rx_int7_mix2_inp_mux, NULL,
4510 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4511
4512 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
4513 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
4514 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
4515 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
4516 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
4517 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
4518 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
4519 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
4520
4521 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
4522 0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4523 SND_SOC_DAPM_POST_PMU),
4524 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
4525 1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4526 SND_SOC_DAPM_POST_PMU),
4527 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
4528 4, 0, NULL, 0),
4529 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
4530 4, 0, NULL, 0),
4531 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4532 &rx_int0_dem_inp_mux),
4533 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4534 &rx_int1_dem_inp_mux),
4535 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4536 &rx_int2_dem_inp_mux),
4537
4538 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
4539 &rx_int0_1_interp_mux,
4540 wcd934x_codec_enable_main_path,
4541 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4542 SND_SOC_DAPM_POST_PMD),
4543 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
4544 &rx_int1_1_interp_mux,
4545 wcd934x_codec_enable_main_path,
4546 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4547 SND_SOC_DAPM_POST_PMD),
4548 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
4549 &rx_int2_1_interp_mux,
4550 wcd934x_codec_enable_main_path,
4551 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4552 SND_SOC_DAPM_POST_PMD),
4553 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
4554 &rx_int3_1_interp_mux,
4555 wcd934x_codec_enable_main_path,
4556 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4557 SND_SOC_DAPM_POST_PMD),
4558 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
4559 &rx_int4_1_interp_mux,
4560 wcd934x_codec_enable_main_path,
4561 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4562 SND_SOC_DAPM_POST_PMD),
4563 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
4564 &rx_int7_1_interp_mux,
4565 wcd934x_codec_enable_main_path,
4566 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4567 SND_SOC_DAPM_POST_PMD),
4568 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
4569 &rx_int8_1_interp_mux,
4570 wcd934x_codec_enable_main_path,
4571 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4572 SND_SOC_DAPM_POST_PMD),
4573
4574 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
4575 &rx_int0_2_interp_mux),
4576 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
4577 &rx_int1_2_interp_mux),
4578 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
4579 &rx_int2_2_interp_mux),
4580 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
4581 &rx_int3_2_interp_mux),
4582 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
4583 &rx_int4_2_interp_mux),
4584 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
4585 &rx_int7_2_interp_mux),
4586 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
4587 &rx_int8_2_interp_mux),
4588 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4589 0, 0, wcd934x_codec_ear_dac_event,
4590 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4591 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4592 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
4593 5, 0, wcd934x_codec_hphl_dac_event,
4594 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4595 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4596 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
4597 4, 0, wcd934x_codec_hphr_dac_event,
4598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4599 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4600 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4601 0, 0, wcd934x_codec_lineout_dac_event,
4602 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4603 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4604 0, 0, wcd934x_codec_lineout_dac_event,
4605 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4606 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
4607 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
4608 wcd934x_codec_enable_hphl_pa,
4609 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4610 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4611 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
4612 wcd934x_codec_enable_hphr_pa,
4613 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4614 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4615 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
4616 NULL, 0),
4617 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
4618 NULL, 0),
4619 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
4620 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4621 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
4622 0, 0, NULL, 0),
4623 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
4624 0, 0, NULL, 0),
4625 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
4626 0, 0, NULL, 0),
4627 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
4628 0, 0, NULL, 0),
4629 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
4630 wcd934x_codec_enable_interp_clk,
4631 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4632 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
4633 wcd934x_codec_enable_interp_clk,
4634 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4635 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
4636 wcd934x_codec_enable_interp_clk,
4637 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4638 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
4639 wcd934x_codec_enable_interp_clk,
4640 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4641 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
4642 wcd934x_codec_enable_interp_clk,
4643 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4644 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
4645 wcd934x_codec_enable_interp_clk,
4646 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4647 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
4648 wcd934x_codec_enable_interp_clk,
4649 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4650 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
4651 0, 0, NULL, 0),
4652 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
4653 0, 0, NULL, 0),
4654 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
4655 0, 0, NULL, 0),
4656 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
4657 0, 0, NULL, 0),
4658 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
4659 0, 0, NULL, 0),
4660 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
4661 0, 0, NULL, 0),
4662 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
4663 0, 0, NULL, 0),
4664 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4665 wcd934x_codec_enable_mclk,
4666 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4667
4668 /* TX */
4669 SND_SOC_DAPM_INPUT("AMIC1"),
4670 SND_SOC_DAPM_INPUT("AMIC2"),
4671 SND_SOC_DAPM_INPUT("AMIC3"),
4672 SND_SOC_DAPM_INPUT("AMIC4"),
4673 SND_SOC_DAPM_INPUT("AMIC5"),
4674 SND_SOC_DAPM_INPUT("DMIC0 Pin"),
4675 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
4676 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
4677 SND_SOC_DAPM_INPUT("DMIC3 Pin"),
4678 SND_SOC_DAPM_INPUT("DMIC4 Pin"),
4679 SND_SOC_DAPM_INPUT("DMIC5 Pin"),
4680
4681 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4682 AIF1_CAP, 0, wcd934x_codec_enable_slim,
4683 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4684 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4685 AIF2_CAP, 0, wcd934x_codec_enable_slim,
4686 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4687 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4688 AIF3_CAP, 0, wcd934x_codec_enable_slim,
4689 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4690
4691 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4692 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4693 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4694 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4695 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4696 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4697 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4698 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4699 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
4700 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
4701 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
4702 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
4703 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
4704
4705 /* Digital Mic Inputs */
4706 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4707 wcd934x_codec_enable_dmic,
4708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4709 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4710 wcd934x_codec_enable_dmic,
4711 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4712 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4713 wcd934x_codec_enable_dmic,
4714 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4715 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4716 wcd934x_codec_enable_dmic,
4717 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4718 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4719 wcd934x_codec_enable_dmic,
4720 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4721 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4722 wcd934x_codec_enable_dmic,
4723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4724 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
4725 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
4726 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
4727 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
4728 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
4729 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
4730 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
4731 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
4732 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
4733 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
4734 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
4735 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
4736 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
4737 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
4738 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
4739 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
4740 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
4741 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
4742 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
4743 &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
4744 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4745 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4746 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
4747 &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
4748 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4749 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4750 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
4751 &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
4752 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4753 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4754 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
4755 &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
4756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4757 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4758 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
4759 &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
4760 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4761 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4762 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
4763 &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
4764 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4765 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4766 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
4767 &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
4768 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4769 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4770 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
4771 &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
4772 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4773 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4774 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
4775 &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
4776 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4777 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4778 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
4779 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4780 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
4781 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4782 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
4783 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4784 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
4785 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4786 SND_SOC_DAPM_SUPPLY("MIC BIAS1", WCD934X_ANA_MICB1, 6, 0, NULL,
4787 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4788 SND_SOC_DAPM_SUPPLY("MIC BIAS2", WCD934X_ANA_MICB2, 6, 0, NULL,
4789 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4790 SND_SOC_DAPM_SUPPLY("MIC BIAS3", WCD934X_ANA_MICB3, 6, 0, NULL,
4791 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4792 SND_SOC_DAPM_SUPPLY("MIC BIAS4", WCD934X_ANA_MICB4, 6, 0, NULL,
4793 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4794
4795 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
4796 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
4797 &cdc_if_tx0_mux),
4798 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
4799 &cdc_if_tx1_mux),
4800 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
4801 &cdc_if_tx2_mux),
4802 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
4803 &cdc_if_tx3_mux),
4804 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
4805 &cdc_if_tx4_mux),
4806 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
4807 &cdc_if_tx5_mux),
4808 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
4809 &cdc_if_tx6_mux),
4810 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
4811 &cdc_if_tx7_mux),
4812 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
4813 &cdc_if_tx8_mux),
4814 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
4815 &cdc_if_tx9_mux),
4816 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
4817 &cdc_if_tx10_mux),
4818 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4819 &cdc_if_tx11_mux),
4820 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4821 &cdc_if_tx11_inp1_mux),
4822 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4823 &cdc_if_tx13_mux),
4824 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4825 &cdc_if_tx13_inp1_mux),
4826 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4827 aif1_slim_cap_mixer,
4828 ARRAY_SIZE(aif1_slim_cap_mixer)),
4829 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4830 aif2_slim_cap_mixer,
4831 ARRAY_SIZE(aif2_slim_cap_mixer)),
4832 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4833 aif3_slim_cap_mixer,
4834 ARRAY_SIZE(aif3_slim_cap_mixer)),
4835 };
4836
4837 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
4838 /* RX0-RX7 */
4839 WCD934X_SLIM_RX_AIF_PATH(0),
4840 WCD934X_SLIM_RX_AIF_PATH(1),
4841 WCD934X_SLIM_RX_AIF_PATH(2),
4842 WCD934X_SLIM_RX_AIF_PATH(3),
4843 WCD934X_SLIM_RX_AIF_PATH(4),
4844 WCD934X_SLIM_RX_AIF_PATH(5),
4845 WCD934X_SLIM_RX_AIF_PATH(6),
4846 WCD934X_SLIM_RX_AIF_PATH(7),
4847
4848 /* RX0 Ear out */
4849 WCD934X_INTERPOLATOR_PATH(0),
4850 WCD934X_INTERPOLATOR_MIX2(0),
4851 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
4852 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
4853 {"RX INT0 DAC", NULL, "RX_BIAS"},
4854 {"EAR PA", NULL, "RX INT0 DAC"},
4855 {"EAR", NULL, "EAR PA"},
4856
4857 /* RX1 Headphone left */
4858 WCD934X_INTERPOLATOR_PATH(1),
4859 WCD934X_INTERPOLATOR_MIX2(1),
4860 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
4861 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
4862 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
4863 {"RX INT1 DAC", NULL, "RX_BIAS"},
4864 {"HPHL PA", NULL, "RX INT1 DAC"},
4865 {"HPHL", NULL, "HPHL PA"},
4866
4867 /* RX2 Headphone right */
4868 WCD934X_INTERPOLATOR_PATH(2),
4869 WCD934X_INTERPOLATOR_MIX2(2),
4870 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
4871 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
4872 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
4873 {"RX INT2 DAC", NULL, "RX_BIAS"},
4874 {"HPHR PA", NULL, "RX INT2 DAC"},
4875 {"HPHR", NULL, "HPHR PA"},
4876
4877 /* RX3 HIFi LineOut1 */
4878 WCD934X_INTERPOLATOR_PATH(3),
4879 WCD934X_INTERPOLATOR_MIX2(3),
4880 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
4881 {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
4882 {"RX INT3 DAC", NULL, "RX_BIAS"},
4883 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
4884 {"LINEOUT1", NULL, "LINEOUT1 PA"},
4885
4886 /* RX4 HIFi LineOut2 */
4887 WCD934X_INTERPOLATOR_PATH(4),
4888 WCD934X_INTERPOLATOR_MIX2(4),
4889 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
4890 {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
4891 {"RX INT4 DAC", NULL, "RX_BIAS"},
4892 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
4893 {"LINEOUT2", NULL, "LINEOUT2 PA"},
4894
4895 /* RX7 Speaker Left Out PA */
4896 WCD934X_INTERPOLATOR_PATH(7),
4897 WCD934X_INTERPOLATOR_MIX2(7),
4898 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
4899 {"RX INT7 CHAIN", NULL, "RX_BIAS"},
4900 {"RX INT7 CHAIN", NULL, "SBOOST0"},
4901 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
4902 {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
4903
4904 /* RX8 Speaker Right Out PA */
4905 WCD934X_INTERPOLATOR_PATH(8),
4906 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
4907 {"RX INT8 CHAIN", NULL, "RX_BIAS"},
4908 {"RX INT8 CHAIN", NULL, "SBOOST1"},
4909 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
4910 {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
4911
4912 /* Tx */
4913 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
4914 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
4915 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
4916
4917 WCD934X_SLIM_TX_AIF_PATH(0),
4918 WCD934X_SLIM_TX_AIF_PATH(1),
4919 WCD934X_SLIM_TX_AIF_PATH(2),
4920 WCD934X_SLIM_TX_AIF_PATH(3),
4921 WCD934X_SLIM_TX_AIF_PATH(4),
4922 WCD934X_SLIM_TX_AIF_PATH(5),
4923 WCD934X_SLIM_TX_AIF_PATH(6),
4924 WCD934X_SLIM_TX_AIF_PATH(7),
4925 WCD934X_SLIM_TX_AIF_PATH(8),
4926
4927 WCD934X_ADC_MUX(0),
4928 WCD934X_ADC_MUX(1),
4929 WCD934X_ADC_MUX(2),
4930 WCD934X_ADC_MUX(3),
4931 WCD934X_ADC_MUX(4),
4932 WCD934X_ADC_MUX(5),
4933 WCD934X_ADC_MUX(6),
4934 WCD934X_ADC_MUX(7),
4935 WCD934X_ADC_MUX(8),
4936
4937 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
4938 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
4939 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
4940 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
4941 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
4942 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
4943 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
4944 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
4945 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
4946
4947 {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
4948 {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
4949
4950 { "DMIC0", NULL, "DMIC0 Pin" },
4951 { "DMIC1", NULL, "DMIC1 Pin" },
4952 { "DMIC2", NULL, "DMIC2 Pin" },
4953 { "DMIC3", NULL, "DMIC3 Pin" },
4954 { "DMIC4", NULL, "DMIC4 Pin" },
4955 { "DMIC5", NULL, "DMIC5 Pin" },
4956
4957 {"ADC1", NULL, "AMIC1"},
4958 {"ADC2", NULL, "AMIC2"},
4959 {"ADC3", NULL, "AMIC3"},
4960 {"ADC4", NULL, "AMIC4_5 SEL"},
4961
4962 WCD934X_IIR_INP_MUX(0),
4963 WCD934X_IIR_INP_MUX(1),
4964
4965 {"SRC0", NULL, "IIR0"},
4966 {"SRC1", NULL, "IIR1"},
4967 };
4968
4969 static const struct snd_soc_component_driver wcd934x_component_drv = {
4970 .probe = wcd934x_comp_probe,
4971 .remove = wcd934x_comp_remove,
4972 .set_sysclk = wcd934x_comp_set_sysclk,
4973 .controls = wcd934x_snd_controls,
4974 .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
4975 .dapm_widgets = wcd934x_dapm_widgets,
4976 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
4977 .dapm_routes = wcd934x_audio_map,
4978 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
4979 };
4980
4981 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
4982 {
4983 struct device *dev = &wcd->sdev->dev;
4984 struct device_node *ifc_dev_np;
4985
4986 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
4987 if (!ifc_dev_np) {
4988 dev_err(dev, "No Interface device found\n");
4989 return -EINVAL;
4990 }
4991
4992 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
4993 if (!wcd->sidev) {
4994 dev_err(dev, "Unable to get SLIM Interface device\n");
4995 return -EINVAL;
4996 }
4997
4998 slim_get_logical_addr(wcd->sidev);
4999 wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
5000 &wcd934x_ifc_regmap_config);
5001 if (IS_ERR(wcd->if_regmap)) {
5002 dev_err(dev, "Failed to allocate ifc register map\n");
5003 return PTR_ERR(wcd->if_regmap);
5004 }
5005
5006 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5007 &wcd->dmic_sample_rate);
5008
5009 return 0;
5010 }
5011
5012 static int wcd934x_codec_probe(struct platform_device *pdev)
5013 {
5014 struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
5015 struct wcd934x_codec *wcd;
5016 struct device *dev = &pdev->dev;
5017 int ret, irq;
5018
5019 wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
5020 if (!wcd)
5021 return -ENOMEM;
5022
5023 wcd->dev = dev;
5024 wcd->regmap = data->regmap;
5025 wcd->extclk = data->extclk;
5026 wcd->sdev = to_slim_device(data->dev);
5027 mutex_init(&wcd->sysclk_mutex);
5028
5029 ret = wcd934x_codec_parse_data(wcd);
5030 if (ret) {
5031 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5032 return ret;
5033 }
5034
5035 /* set default rate 9P6MHz */
5036 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5037 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5038 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5039 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5040 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5041
5042 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5043 if (irq < 0) {
5044 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5045 return irq;
5046 }
5047
5048 ret = devm_request_threaded_irq(dev, irq, NULL,
5049 wcd934x_slim_irq_handler,
5050 IRQF_TRIGGER_RISING,
5051 "slim", wcd);
5052 if (ret) {
5053 dev_err(dev, "Failed to request slimbus irq\n");
5054 return ret;
5055 }
5056
5057 wcd934x_register_mclk_output(wcd);
5058 platform_set_drvdata(pdev, wcd);
5059
5060 return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5061 wcd934x_slim_dais,
5062 ARRAY_SIZE(wcd934x_slim_dais));
5063 }
5064
5065 static const struct platform_device_id wcd934x_driver_id[] = {
5066 {
5067 .name = "wcd934x-codec",
5068 },
5069 {},
5070 };
5071 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5072
5073 static struct platform_driver wcd934x_codec_driver = {
5074 .probe = &wcd934x_codec_probe,
5075 .id_table = wcd934x_driver_id,
5076 .driver = {
5077 .name = "wcd934x-codec",
5078 }
5079 };
5080
5081 MODULE_ALIAS("platform:wcd934x-codec");
5082 module_platform_driver(wcd934x_codec_driver);
5083 MODULE_DESCRIPTION("WCD934x codec driver");
5084 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support