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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / sound / soc / fsl / fsl_spdif.c
blob7858a5499ac5d0b5b648e0fea2fadc708bdc4e60
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
4 //
5 // Copyright (C) 2013 Freescale Semiconductor, Inc.
6 //
7 // Based on stmp3xxx_spdif_dai.c
8 // Vladimir Barinov <vbarinov@embeddedalley.com>
9 // Copyright 2008 SigmaTel, Inc
10 // Copyright 2008 Embedded Alley Solutions, Inc
11
12 #include <linux/bitrev.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/regmap.h>
19
20 #include <sound/asoundef.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/soc.h>
23
24 #include "fsl_spdif.h"
25 #include "imx-pcm.h"
26
27 #define FSL_SPDIF_TXFIFO_WML 0x8
28 #define FSL_SPDIF_RXFIFO_WML 0x8
29
30 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
31 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
32 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
33 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
34 INT_LOSS_LOCK | INT_DPLL_LOCKED)
35
36 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
37
38 /* Index list for the values that has if (DPLL Locked) condition */
39 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
40 #define SRPC_NODPLL_START1 0x5
41 #define SRPC_NODPLL_START2 0xc
42
43 #define DEFAULT_RXCLK_SRC 1
44
45 /*
46 * SPDIF control structure
47 * Defines channel status, subcode and Q sub
48 */
49 struct spdif_mixer_control {
50 /* spinlock to access control data */
51 spinlock_t ctl_lock;
52
53 /* IEC958 channel tx status bit */
54 unsigned char ch_status[4];
55
56 /* User bits */
57 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
58
59 /* Q subcode part of user bits */
60 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
61
62 /* Buffer offset for U/Q */
63 u32 upos;
64 u32 qpos;
65
66 /* Ready buffer index of the two buffers */
67 u32 ready_buf;
68 };
69
70 /**
71 * fsl_spdif_priv: Freescale SPDIF private data
72 *
73 * @fsl_spdif_control: SPDIF control data
74 * @cpu_dai_drv: cpu dai driver
75 * @pdev: platform device pointer
76 * @regmap: regmap handler
77 * @dpll_locked: dpll lock flag
78 * @txrate: the best rates for playback
79 * @txclk_df: STC_TXCLK_DF dividers value for playback
80 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
81 * @txclk_src: STC_TXCLK_SRC values for playback
82 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
83 * @txclk: tx clock sources for playback
84 * @rxclk: rx clock sources for capture
85 * @coreclk: core clock for register access via DMA
86 * @sysclk: system clock for rx clock rate measurement
87 * @spbaclk: SPBA clock (optional, depending on SoC design)
88 * @dma_params_tx: DMA parameters for transmit channel
89 * @dma_params_rx: DMA parameters for receive channel
90 */
91 struct fsl_spdif_priv {
92 struct spdif_mixer_control fsl_spdif_control;
93 struct snd_soc_dai_driver cpu_dai_drv;
94 struct platform_device *pdev;
95 struct regmap *regmap;
96 bool dpll_locked;
97 u32 txrate[SPDIF_TXRATE_MAX];
98 u8 txclk_df[SPDIF_TXRATE_MAX];
99 u16 sysclk_df[SPDIF_TXRATE_MAX];
100 u8 txclk_src[SPDIF_TXRATE_MAX];
101 u8 rxclk_src;
102 struct clk *txclk[SPDIF_TXRATE_MAX];
103 struct clk *rxclk;
104 struct clk *coreclk;
105 struct clk *sysclk;
106 struct clk *spbaclk;
107 struct snd_dmaengine_dai_dma_data dma_params_tx;
108 struct snd_dmaengine_dai_dma_data dma_params_rx;
109 /* regcache for SRPC */
110 u32 regcache_srpc;
111 };
112
113 /* DPLL locked and lock loss interrupt handler */
114 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
115 {
116 struct regmap *regmap = spdif_priv->regmap;
117 struct platform_device *pdev = spdif_priv->pdev;
118 u32 locked;
119
120 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
121 locked &= SRPC_DPLL_LOCKED;
122
123 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
124 locked ? "locked" : "loss lock");
125
126 spdif_priv->dpll_locked = locked ? true : false;
127 }
128
129 /* Receiver found illegal symbol interrupt handler */
130 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
131 {
132 struct regmap *regmap = spdif_priv->regmap;
133 struct platform_device *pdev = spdif_priv->pdev;
134
135 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
136
137 /* Clear illegal symbol if DPLL unlocked since no audio stream */
138 if (!spdif_priv->dpll_locked)
139 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
140 }
141
142 /* U/Q Channel receive register full */
143 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
144 {
145 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
146 struct regmap *regmap = spdif_priv->regmap;
147 struct platform_device *pdev = spdif_priv->pdev;
148 u32 *pos, size, val, reg;
149
150 switch (name) {
151 case 'U':
152 pos = &ctrl->upos;
153 size = SPDIF_UBITS_SIZE;
154 reg = REG_SPDIF_SRU;
155 break;
156 case 'Q':
157 pos = &ctrl->qpos;
158 size = SPDIF_QSUB_SIZE;
159 reg = REG_SPDIF_SRQ;
160 break;
161 default:
162 dev_err(&pdev->dev, "unsupported channel name\n");
163 return;
164 }
165
166 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
167
168 if (*pos >= size * 2) {
169 *pos = 0;
170 } else if (unlikely((*pos % size) + 3 > size)) {
171 dev_err(&pdev->dev, "User bit receive buffer overflow\n");
172 return;
173 }
174
175 regmap_read(regmap, reg, &val);
176 ctrl->subcode[*pos++] = val >> 16;
177 ctrl->subcode[*pos++] = val >> 8;
178 ctrl->subcode[*pos++] = val;
179 }
180
181 /* U/Q Channel sync found */
182 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
183 {
184 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
185 struct platform_device *pdev = spdif_priv->pdev;
186
187 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
188
189 /* U/Q buffer reset */
190 if (ctrl->qpos == 0)
191 return;
192
193 /* Set ready to this buffer */
194 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
195 }
196
197 /* U/Q Channel framing error */
198 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
199 {
200 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
201 struct regmap *regmap = spdif_priv->regmap;
202 struct platform_device *pdev = spdif_priv->pdev;
203 u32 val;
204
205 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
206
207 /* Read U/Q data to clear the irq and do buffer reset */
208 regmap_read(regmap, REG_SPDIF_SRU, &val);
209 regmap_read(regmap, REG_SPDIF_SRQ, &val);
210
211 /* Drop this U/Q buffer */
212 ctrl->ready_buf = 0;
213 ctrl->upos = 0;
214 ctrl->qpos = 0;
215 }
216
217 /* Get spdif interrupt status and clear the interrupt */
218 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
219 {
220 struct regmap *regmap = spdif_priv->regmap;
221 u32 val, val2;
222
223 regmap_read(regmap, REG_SPDIF_SIS, &val);
224 regmap_read(regmap, REG_SPDIF_SIE, &val2);
225
226 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
227
228 return val;
229 }
230
231 static irqreturn_t spdif_isr(int irq, void *devid)
232 {
233 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
234 struct platform_device *pdev = spdif_priv->pdev;
235 u32 sis;
236
237 sis = spdif_intr_status_clear(spdif_priv);
238
239 if (sis & INT_DPLL_LOCKED)
240 spdif_irq_dpll_lock(spdif_priv);
241
242 if (sis & INT_TXFIFO_UNOV)
243 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
244
245 if (sis & INT_TXFIFO_RESYNC)
246 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
247
248 if (sis & INT_CNEW)
249 dev_dbg(&pdev->dev, "isr: cstatus new\n");
250
251 if (sis & INT_VAL_NOGOOD)
252 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
253
254 if (sis & INT_SYM_ERR)
255 spdif_irq_sym_error(spdif_priv);
256
257 if (sis & INT_BIT_ERR)
258 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
259
260 if (sis & INT_URX_FUL)
261 spdif_irq_uqrx_full(spdif_priv, 'U');
262
263 if (sis & INT_URX_OV)
264 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
265
266 if (sis & INT_QRX_FUL)
267 spdif_irq_uqrx_full(spdif_priv, 'Q');
268
269 if (sis & INT_QRX_OV)
270 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
271
272 if (sis & INT_UQ_SYNC)
273 spdif_irq_uq_sync(spdif_priv);
274
275 if (sis & INT_UQ_ERR)
276 spdif_irq_uq_err(spdif_priv);
277
278 if (sis & INT_RXFIFO_UNOV)
279 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
280
281 if (sis & INT_RXFIFO_RESYNC)
282 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
283
284 if (sis & INT_LOSS_LOCK)
285 spdif_irq_dpll_lock(spdif_priv);
286
287 /* FIXME: Write Tx FIFO to clear TxEm */
288 if (sis & INT_TX_EM)
289 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
290
291 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
292 if (sis & INT_RXFIFO_FUL)
293 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
294
295 return IRQ_HANDLED;
296 }
297
298 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
299 {
300 struct regmap *regmap = spdif_priv->regmap;
301 u32 val, cycle = 1000;
302
303 regcache_cache_bypass(regmap, true);
304
305 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
306
307 /*
308 * RESET bit would be cleared after finishing its reset procedure,
309 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
310 */
311 do {
312 regmap_read(regmap, REG_SPDIF_SCR, &val);
313 } while ((val & SCR_SOFT_RESET) && cycle--);
314
315 regcache_cache_bypass(regmap, false);
316 regcache_mark_dirty(regmap);
317 regcache_sync(regmap);
318
319 if (cycle)
320 return 0;
321 else
322 return -EBUSY;
323 }
324
325 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
326 u8 mask, u8 cstatus)
327 {
328 ctrl->ch_status[3] &= ~mask;
329 ctrl->ch_status[3] |= cstatus & mask;
330 }
331
332 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
333 {
334 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
335 struct regmap *regmap = spdif_priv->regmap;
336 struct platform_device *pdev = spdif_priv->pdev;
337 u32 ch_status;
338
339 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
340 (bitrev8(ctrl->ch_status[1]) << 8) |
341 bitrev8(ctrl->ch_status[2]);
342 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
343
344 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
345
346 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
347 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
348
349 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
350 }
351
352 /* Set SPDIF PhaseConfig register for rx clock */
353 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
354 enum spdif_gainsel gainsel, int dpll_locked)
355 {
356 struct regmap *regmap = spdif_priv->regmap;
357 u8 clksrc = spdif_priv->rxclk_src;
358
359 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
360 return -EINVAL;
361
362 regmap_update_bits(regmap, REG_SPDIF_SRPC,
363 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
364 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
365
366 return 0;
367 }
368
369 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
370 int sample_rate)
371 {
372 struct snd_soc_pcm_runtime *rtd = substream->private_data;
373 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
374 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
375 struct regmap *regmap = spdif_priv->regmap;
376 struct platform_device *pdev = spdif_priv->pdev;
377 unsigned long csfs = 0;
378 u32 stc, mask, rate;
379 u16 sysclk_df;
380 u8 clk, txclk_df;
381 int ret;
382
383 switch (sample_rate) {
384 case 32000:
385 rate = SPDIF_TXRATE_32000;
386 csfs = IEC958_AES3_CON_FS_32000;
387 break;
388 case 44100:
389 rate = SPDIF_TXRATE_44100;
390 csfs = IEC958_AES3_CON_FS_44100;
391 break;
392 case 48000:
393 rate = SPDIF_TXRATE_48000;
394 csfs = IEC958_AES3_CON_FS_48000;
395 break;
396 case 96000:
397 rate = SPDIF_TXRATE_96000;
398 csfs = IEC958_AES3_CON_FS_96000;
399 break;
400 case 192000:
401 rate = SPDIF_TXRATE_192000;
402 csfs = IEC958_AES3_CON_FS_192000;
403 break;
404 default:
405 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
406 return -EINVAL;
407 }
408
409 clk = spdif_priv->txclk_src[rate];
410 if (clk >= STC_TXCLK_SRC_MAX) {
411 dev_err(&pdev->dev, "tx clock source is out of range\n");
412 return -EINVAL;
413 }
414
415 txclk_df = spdif_priv->txclk_df[rate];
416 if (txclk_df == 0) {
417 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
418 return -EINVAL;
419 }
420
421 sysclk_df = spdif_priv->sysclk_df[rate];
422
423 /* Don't mess up the clocks from other modules */
424 if (clk != STC_TXCLK_SPDIF_ROOT)
425 goto clk_set_bypass;
426
427 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
428 ret = clk_set_rate(spdif_priv->txclk[rate],
429 64 * sample_rate * txclk_df);
430 if (ret) {
431 dev_err(&pdev->dev, "failed to set tx clock rate\n");
432 return ret;
433 }
434
435 clk_set_bypass:
436 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
437 (64 * sample_rate * txclk_df * sysclk_df));
438 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
439 clk_get_rate(spdif_priv->txclk[rate]));
440
441 /* set fs field in consumer channel status */
442 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
443
444 /* select clock source and divisor */
445 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
446 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
447 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
448 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
449 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
450
451 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
452 spdif_priv->txrate[rate], sample_rate);
453
454 return 0;
455 }
456
457 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
458 struct snd_soc_dai *cpu_dai)
459 {
460 struct snd_soc_pcm_runtime *rtd = substream->private_data;
461 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
462 struct platform_device *pdev = spdif_priv->pdev;
463 struct regmap *regmap = spdif_priv->regmap;
464 u32 scr, mask;
465 int i;
466 int ret;
467
468 /* Reset module and interrupts only for first initialization */
469 if (!cpu_dai->active) {
470 ret = clk_prepare_enable(spdif_priv->coreclk);
471 if (ret) {
472 dev_err(&pdev->dev, "failed to enable core clock\n");
473 return ret;
474 }
475
476 if (!IS_ERR(spdif_priv->spbaclk)) {
477 ret = clk_prepare_enable(spdif_priv->spbaclk);
478 if (ret) {
479 dev_err(&pdev->dev, "failed to enable spba clock\n");
480 goto err_spbaclk;
481 }
482 }
483
484 ret = spdif_softreset(spdif_priv);
485 if (ret) {
486 dev_err(&pdev->dev, "failed to soft reset\n");
487 goto err;
488 }
489
490 /* Disable all the interrupts */
491 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
492 }
493
494 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
495 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
496 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
497 SCR_TXFIFO_FSEL_IF8;
498 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
499 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
500 SCR_TXFIFO_FSEL_MASK;
501 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
502 ret = clk_prepare_enable(spdif_priv->txclk[i]);
503 if (ret)
504 goto disable_txclk;
505 }
506 } else {
507 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
508 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
509 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
510 ret = clk_prepare_enable(spdif_priv->rxclk);
511 if (ret)
512 goto err;
513 }
514 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
515
516 /* Power up SPDIF module */
517 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
518
519 return 0;
520
521 disable_txclk:
522 for (i--; i >= 0; i--)
523 clk_disable_unprepare(spdif_priv->txclk[i]);
524 err:
525 if (!IS_ERR(spdif_priv->spbaclk))
526 clk_disable_unprepare(spdif_priv->spbaclk);
527 err_spbaclk:
528 clk_disable_unprepare(spdif_priv->coreclk);
529
530 return ret;
531 }
532
533 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
534 struct snd_soc_dai *cpu_dai)
535 {
536 struct snd_soc_pcm_runtime *rtd = substream->private_data;
537 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
538 struct regmap *regmap = spdif_priv->regmap;
539 u32 scr, mask, i;
540
541 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
542 scr = 0;
543 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
544 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
545 SCR_TXFIFO_FSEL_MASK;
546 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
547 clk_disable_unprepare(spdif_priv->txclk[i]);
548 } else {
549 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
550 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
551 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
552 clk_disable_unprepare(spdif_priv->rxclk);
553 }
554 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
555
556 /* Power down SPDIF module only if tx&rx are both inactive */
557 if (!cpu_dai->active) {
558 spdif_intr_status_clear(spdif_priv);
559 regmap_update_bits(regmap, REG_SPDIF_SCR,
560 SCR_LOW_POWER, SCR_LOW_POWER);
561 if (!IS_ERR(spdif_priv->spbaclk))
562 clk_disable_unprepare(spdif_priv->spbaclk);
563 clk_disable_unprepare(spdif_priv->coreclk);
564 }
565 }
566
567 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
568 struct snd_pcm_hw_params *params,
569 struct snd_soc_dai *dai)
570 {
571 struct snd_soc_pcm_runtime *rtd = substream->private_data;
572 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
573 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
574 struct platform_device *pdev = spdif_priv->pdev;
575 u32 sample_rate = params_rate(params);
576 int ret = 0;
577
578 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
579 ret = spdif_set_sample_rate(substream, sample_rate);
580 if (ret) {
581 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
582 __func__, sample_rate);
583 return ret;
584 }
585 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
586 IEC958_AES3_CON_CLOCK_1000PPM);
587 spdif_write_channel_status(spdif_priv);
588 } else {
589 /* Setup rx clock source */
590 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
591 }
592
593 return ret;
594 }
595
596 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
597 int cmd, struct snd_soc_dai *dai)
598 {
599 struct snd_soc_pcm_runtime *rtd = substream->private_data;
600 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
601 struct regmap *regmap = spdif_priv->regmap;
602 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
603 u32 intr = SIE_INTR_FOR(tx);
604 u32 dmaen = SCR_DMA_xX_EN(tx);
605
606 switch (cmd) {
607 case SNDRV_PCM_TRIGGER_START:
608 case SNDRV_PCM_TRIGGER_RESUME:
609 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
610 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
611 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
612 break;
613 case SNDRV_PCM_TRIGGER_STOP:
614 case SNDRV_PCM_TRIGGER_SUSPEND:
615 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
616 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
617 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
618 break;
619 default:
620 return -EINVAL;
621 }
622
623 return 0;
624 }
625
626 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
627 .startup = fsl_spdif_startup,
628 .hw_params = fsl_spdif_hw_params,
629 .trigger = fsl_spdif_trigger,
630 .shutdown = fsl_spdif_shutdown,
631 };
632
633
634 /*
635 * FSL SPDIF IEC958 controller(mixer) functions
636 *
637 * Channel status get/put control
638 * User bit value get/put control
639 * Valid bit value get control
640 * DPLL lock status get control
641 * User bit sync mode selection control
642 */
643
644 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
645 struct snd_ctl_elem_info *uinfo)
646 {
647 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
648 uinfo->count = 1;
649
650 return 0;
651 }
652
653 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
654 struct snd_ctl_elem_value *uvalue)
655 {
656 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
657 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
658 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
659
660 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
661 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
662 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
663 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
664
665 return 0;
666 }
667
668 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
669 struct snd_ctl_elem_value *uvalue)
670 {
671 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
672 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
673 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
674
675 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
676 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
677 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
678 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
679
680 spdif_write_channel_status(spdif_priv);
681
682 return 0;
683 }
684
685 /* Get channel status from SPDIF_RX_CCHAN register */
686 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
687 struct snd_ctl_elem_value *ucontrol)
688 {
689 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
690 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
691 struct regmap *regmap = spdif_priv->regmap;
692 u32 cstatus, val;
693
694 regmap_read(regmap, REG_SPDIF_SIS, &val);
695 if (!(val & INT_CNEW))
696 return -EAGAIN;
697
698 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
699 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
700 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
701 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
702
703 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
704 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
705 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
706 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
707
708 /* Clear intr */
709 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
710
711 return 0;
712 }
713
714 /*
715 * Get User bits (subcode) from chip value which readed out
716 * in UChannel register.
717 */
718 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
719 struct snd_ctl_elem_value *ucontrol)
720 {
721 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
722 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
723 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
724 unsigned long flags;
725 int ret = -EAGAIN;
726
727 spin_lock_irqsave(&ctrl->ctl_lock, flags);
728 if (ctrl->ready_buf) {
729 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
730 memcpy(&ucontrol->value.iec958.subcode[0],
731 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
732 ret = 0;
733 }
734 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
735
736 return ret;
737 }
738
739 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
740 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
741 struct snd_ctl_elem_info *uinfo)
742 {
743 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
744 uinfo->count = SPDIF_QSUB_SIZE;
745
746 return 0;
747 }
748
749 /* Get Q subcode from chip value which readed out in QChannel register */
750 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
751 struct snd_ctl_elem_value *ucontrol)
752 {
753 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
754 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
755 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
756 unsigned long flags;
757 int ret = -EAGAIN;
758
759 spin_lock_irqsave(&ctrl->ctl_lock, flags);
760 if (ctrl->ready_buf) {
761 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
762 memcpy(&ucontrol->value.bytes.data[0],
763 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
764 ret = 0;
765 }
766 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
767
768 return ret;
769 }
770
771 /* Valid bit information */
772 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
773 struct snd_ctl_elem_info *uinfo)
774 {
775 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
776 uinfo->count = 1;
777 uinfo->value.integer.min = 0;
778 uinfo->value.integer.max = 1;
779
780 return 0;
781 }
782
783 /* Get valid good bit from interrupt status register */
784 static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
785 struct snd_ctl_elem_value *ucontrol)
786 {
787 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
788 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
789 struct regmap *regmap = spdif_priv->regmap;
790 u32 val;
791
792 regmap_read(regmap, REG_SPDIF_SIS, &val);
793 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
794 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
795
796 return 0;
797 }
798
799 /* DPLL lock information */
800 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
801 struct snd_ctl_elem_info *uinfo)
802 {
803 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
804 uinfo->count = 1;
805 uinfo->value.integer.min = 16000;
806 uinfo->value.integer.max = 96000;
807
808 return 0;
809 }
810
811 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
812 24, 16, 12, 8, 6, 4, 3,
813 };
814
815 /* Get RX data clock rate given the SPDIF bus_clk */
816 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
817 enum spdif_gainsel gainsel)
818 {
819 struct regmap *regmap = spdif_priv->regmap;
820 struct platform_device *pdev = spdif_priv->pdev;
821 u64 tmpval64, busclk_freq = 0;
822 u32 freqmeas, phaseconf;
823 u8 clksrc;
824
825 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
826 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
827
828 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
829
830 /* Get bus clock from system */
831 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
832 busclk_freq = clk_get_rate(spdif_priv->sysclk);
833
834 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
835 tmpval64 = (u64) busclk_freq * freqmeas;
836 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
837 do_div(tmpval64, 128 * 1024);
838
839 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
840 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
841 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
842
843 return (int)tmpval64;
844 }
845
846 /*
847 * Get DPLL lock or not info from stable interrupt status register.
848 * User application must use this control to get locked,
849 * then can do next PCM operation
850 */
851 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
852 struct snd_ctl_elem_value *ucontrol)
853 {
854 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
855 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
856 int rate = 0;
857
858 if (spdif_priv->dpll_locked)
859 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
860
861 ucontrol->value.integer.value[0] = rate;
862
863 return 0;
864 }
865
866 /* User bit sync mode info */
867 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
868 struct snd_ctl_elem_info *uinfo)
869 {
870 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
871 uinfo->count = 1;
872 uinfo->value.integer.min = 0;
873 uinfo->value.integer.max = 1;
874
875 return 0;
876 }
877
878 /*
879 * User bit sync mode:
880 * 1 CD User channel subcode
881 * 0 Non-CD data
882 */
883 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
884 struct snd_ctl_elem_value *ucontrol)
885 {
886 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
887 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
888 struct regmap *regmap = spdif_priv->regmap;
889 u32 val;
890
891 regmap_read(regmap, REG_SPDIF_SRCD, &val);
892 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
893
894 return 0;
895 }
896
897 /*
898 * User bit sync mode:
899 * 1 CD User channel subcode
900 * 0 Non-CD data
901 */
902 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
903 struct snd_ctl_elem_value *ucontrol)
904 {
905 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
906 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
907 struct regmap *regmap = spdif_priv->regmap;
908 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
909
910 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
911
912 return 0;
913 }
914
915 /* FSL SPDIF IEC958 controller defines */
916 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
917 /* Status cchanel controller */
918 {
919 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
920 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
921 .access = SNDRV_CTL_ELEM_ACCESS_READ |
922 SNDRV_CTL_ELEM_ACCESS_WRITE |
923 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
924 .info = fsl_spdif_info,
925 .get = fsl_spdif_pb_get,
926 .put = fsl_spdif_pb_put,
927 },
928 {
929 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
930 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
931 .access = SNDRV_CTL_ELEM_ACCESS_READ |
932 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
933 .info = fsl_spdif_info,
934 .get = fsl_spdif_capture_get,
935 },
936 /* User bits controller */
937 {
938 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
939 .name = "IEC958 Subcode Capture Default",
940 .access = SNDRV_CTL_ELEM_ACCESS_READ |
941 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
942 .info = fsl_spdif_info,
943 .get = fsl_spdif_subcode_get,
944 },
945 {
946 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
947 .name = "IEC958 Q-subcode Capture Default",
948 .access = SNDRV_CTL_ELEM_ACCESS_READ |
949 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
950 .info = fsl_spdif_qinfo,
951 .get = fsl_spdif_qget,
952 },
953 /* Valid bit error controller */
954 {
955 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
956 .name = "IEC958 V-Bit Errors",
957 .access = SNDRV_CTL_ELEM_ACCESS_READ |
958 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
959 .info = fsl_spdif_vbit_info,
960 .get = fsl_spdif_vbit_get,
961 },
962 /* DPLL lock info get controller */
963 {
964 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
965 .name = "RX Sample Rate",
966 .access = SNDRV_CTL_ELEM_ACCESS_READ |
967 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
968 .info = fsl_spdif_rxrate_info,
969 .get = fsl_spdif_rxrate_get,
970 },
971 /* User bit sync mode set/get controller */
972 {
973 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
974 .name = "IEC958 USyncMode CDText",
975 .access = SNDRV_CTL_ELEM_ACCESS_READ |
976 SNDRV_CTL_ELEM_ACCESS_WRITE |
977 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
978 .info = fsl_spdif_usync_info,
979 .get = fsl_spdif_usync_get,
980 .put = fsl_spdif_usync_put,
981 },
982 };
983
984 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
985 {
986 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
987
988 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
989 &spdif_private->dma_params_rx);
990
991 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
992
993 return 0;
994 }
995
996 static struct snd_soc_dai_driver fsl_spdif_dai = {
997 .probe = &fsl_spdif_dai_probe,
998 .playback = {
999 .stream_name = "CPU-Playback",
1000 .channels_min = 2,
1001 .channels_max = 2,
1002 .rates = FSL_SPDIF_RATES_PLAYBACK,
1003 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
1004 },
1005 .capture = {
1006 .stream_name = "CPU-Capture",
1007 .channels_min = 2,
1008 .channels_max = 2,
1009 .rates = FSL_SPDIF_RATES_CAPTURE,
1010 .formats = FSL_SPDIF_FORMATS_CAPTURE,
1011 },
1012 .ops = &fsl_spdif_dai_ops,
1013 };
1014
1015 static const struct snd_soc_component_driver fsl_spdif_component = {
1016 .name = "fsl-spdif",
1017 };
1018
1019 /* FSL SPDIF REGMAP */
1020 static const struct reg_default fsl_spdif_reg_defaults[] = {
1021 {REG_SPDIF_SCR, 0x00000400},
1022 {REG_SPDIF_SRCD, 0x00000000},
1023 {REG_SPDIF_SIE, 0x00000000},
1024 {REG_SPDIF_STL, 0x00000000},
1025 {REG_SPDIF_STR, 0x00000000},
1026 {REG_SPDIF_STCSCH, 0x00000000},
1027 {REG_SPDIF_STCSCL, 0x00000000},
1028 {REG_SPDIF_STC, 0x00020f00},
1029 };
1030
1031 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1032 {
1033 switch (reg) {
1034 case REG_SPDIF_SCR:
1035 case REG_SPDIF_SRCD:
1036 case REG_SPDIF_SRPC:
1037 case REG_SPDIF_SIE:
1038 case REG_SPDIF_SIS:
1039 case REG_SPDIF_SRL:
1040 case REG_SPDIF_SRR:
1041 case REG_SPDIF_SRCSH:
1042 case REG_SPDIF_SRCSL:
1043 case REG_SPDIF_SRU:
1044 case REG_SPDIF_SRQ:
1045 case REG_SPDIF_STCSCH:
1046 case REG_SPDIF_STCSCL:
1047 case REG_SPDIF_SRFM:
1048 case REG_SPDIF_STC:
1049 return true;
1050 default:
1051 return false;
1052 }
1053 }
1054
1055 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
1056 {
1057 switch (reg) {
1058 case REG_SPDIF_SRPC:
1059 case REG_SPDIF_SIS:
1060 case REG_SPDIF_SRL:
1061 case REG_SPDIF_SRR:
1062 case REG_SPDIF_SRCSH:
1063 case REG_SPDIF_SRCSL:
1064 case REG_SPDIF_SRU:
1065 case REG_SPDIF_SRQ:
1066 case REG_SPDIF_SRFM:
1067 return true;
1068 default:
1069 return false;
1070 }
1071 }
1072
1073 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1074 {
1075 switch (reg) {
1076 case REG_SPDIF_SCR:
1077 case REG_SPDIF_SRCD:
1078 case REG_SPDIF_SRPC:
1079 case REG_SPDIF_SIE:
1080 case REG_SPDIF_SIC:
1081 case REG_SPDIF_STL:
1082 case REG_SPDIF_STR:
1083 case REG_SPDIF_STCSCH:
1084 case REG_SPDIF_STCSCL:
1085 case REG_SPDIF_STC:
1086 return true;
1087 default:
1088 return false;
1089 }
1090 }
1091
1092 static const struct regmap_config fsl_spdif_regmap_config = {
1093 .reg_bits = 32,
1094 .reg_stride = 4,
1095 .val_bits = 32,
1096
1097 .max_register = REG_SPDIF_STC,
1098 .reg_defaults = fsl_spdif_reg_defaults,
1099 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
1100 .readable_reg = fsl_spdif_readable_reg,
1101 .volatile_reg = fsl_spdif_volatile_reg,
1102 .writeable_reg = fsl_spdif_writeable_reg,
1103 .cache_type = REGCACHE_FLAT,
1104 };
1105
1106 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1107 struct clk *clk, u64 savesub,
1108 enum spdif_txrate index, bool round)
1109 {
1110 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1111 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1112 u64 rate_ideal, rate_actual, sub;
1113 u32 arate;
1114 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
1115 u8 txclk_df;
1116
1117 /* The sysclk has an extra divisor [2, 512] */
1118 sysclk_dfmin = is_sysclk ? 2 : 1;
1119 sysclk_dfmax = is_sysclk ? 512 : 1;
1120
1121 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1122 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1123 rate_ideal = rate[index] * txclk_df * 64ULL;
1124 if (round)
1125 rate_actual = clk_round_rate(clk, rate_ideal);
1126 else
1127 rate_actual = clk_get_rate(clk);
1128
1129 arate = rate_actual / 64;
1130 arate /= txclk_df * sysclk_df;
1131
1132 if (arate == rate[index]) {
1133 /* We are lucky */
1134 savesub = 0;
1135 spdif_priv->txclk_df[index] = txclk_df;
1136 spdif_priv->sysclk_df[index] = sysclk_df;
1137 spdif_priv->txrate[index] = arate;
1138 goto out;
1139 } else if (arate / rate[index] == 1) {
1140 /* A little bigger than expect */
1141 sub = (u64)(arate - rate[index]) * 100000;
1142 do_div(sub, rate[index]);
1143 if (sub >= savesub)
1144 continue;
1145 savesub = sub;
1146 spdif_priv->txclk_df[index] = txclk_df;
1147 spdif_priv->sysclk_df[index] = sysclk_df;
1148 spdif_priv->txrate[index] = arate;
1149 } else if (rate[index] / arate == 1) {
1150 /* A little smaller than expect */
1151 sub = (u64)(rate[index] - arate) * 100000;
1152 do_div(sub, rate[index]);
1153 if (sub >= savesub)
1154 continue;
1155 savesub = sub;
1156 spdif_priv->txclk_df[index] = txclk_df;
1157 spdif_priv->sysclk_df[index] = sysclk_df;
1158 spdif_priv->txrate[index] = arate;
1159 }
1160 }
1161 }
1162
1163 out:
1164 return savesub;
1165 }
1166
1167 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1168 enum spdif_txrate index)
1169 {
1170 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1171 struct platform_device *pdev = spdif_priv->pdev;
1172 struct device *dev = &pdev->dev;
1173 u64 savesub = 100000, ret;
1174 struct clk *clk;
1175 char tmp[16];
1176 int i;
1177
1178 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1179 sprintf(tmp, "rxtx%d", i);
1180 clk = devm_clk_get(&pdev->dev, tmp);
1181 if (IS_ERR(clk)) {
1182 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1183 return PTR_ERR(clk);
1184 }
1185 if (!clk_get_rate(clk))
1186 continue;
1187
1188 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1189 i == STC_TXCLK_SPDIF_ROOT);
1190 if (savesub == ret)
1191 continue;
1192
1193 savesub = ret;
1194 spdif_priv->txclk[index] = clk;
1195 spdif_priv->txclk_src[index] = i;
1196
1197 /* To quick catch a divisor, we allow a 0.1% deviation */
1198 if (savesub < 100)
1199 break;
1200 }
1201
1202 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1203 spdif_priv->txclk_src[index], rate[index]);
1204 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
1205 spdif_priv->txclk_df[index], rate[index]);
1206 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
1207 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
1208 spdif_priv->sysclk_df[index], rate[index]);
1209 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
1210 rate[index], spdif_priv->txrate[index]);
1211
1212 return 0;
1213 }
1214
1215 static int fsl_spdif_probe(struct platform_device *pdev)
1216 {
1217 struct device_node *np = pdev->dev.of_node;
1218 struct fsl_spdif_priv *spdif_priv;
1219 struct spdif_mixer_control *ctrl;
1220 struct resource *res;
1221 void __iomem *regs;
1222 int irq, ret, i;
1223
1224 if (!np)
1225 return -ENODEV;
1226
1227 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1228 if (!spdif_priv)
1229 return -ENOMEM;
1230
1231 spdif_priv->pdev = pdev;
1232
1233 /* Initialize this copy of the CPU DAI driver structure */
1234 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1235 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1236
1237 /* Get the addresses and IRQ */
1238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1239 regs = devm_ioremap_resource(&pdev->dev, res);
1240 if (IS_ERR(regs))
1241 return PTR_ERR(regs);
1242
1243 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1244 "core", regs, &fsl_spdif_regmap_config);
1245 if (IS_ERR(spdif_priv->regmap)) {
1246 dev_err(&pdev->dev, "regmap init failed\n");
1247 return PTR_ERR(spdif_priv->regmap);
1248 }
1249
1250 irq = platform_get_irq(pdev, 0);
1251 if (irq < 0)
1252 return irq;
1253
1254 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1255 dev_name(&pdev->dev), spdif_priv);
1256 if (ret) {
1257 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1258 return ret;
1259 }
1260
1261 /* Get system clock for rx clock rate calculation */
1262 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1263 if (IS_ERR(spdif_priv->sysclk)) {
1264 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1265 return PTR_ERR(spdif_priv->sysclk);
1266 }
1267
1268 /* Get core clock for data register access via DMA */
1269 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1270 if (IS_ERR(spdif_priv->coreclk)) {
1271 dev_err(&pdev->dev, "no core clock in devicetree\n");
1272 return PTR_ERR(spdif_priv->coreclk);
1273 }
1274
1275 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1276 if (IS_ERR(spdif_priv->spbaclk))
1277 dev_warn(&pdev->dev, "no spba clock in devicetree\n");
1278
1279 /* Select clock source for rx/tx clock */
1280 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1281 if (IS_ERR(spdif_priv->rxclk)) {
1282 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1283 return PTR_ERR(spdif_priv->rxclk);
1284 }
1285 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1286
1287 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1288 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1289 if (ret)
1290 return ret;
1291 }
1292
1293 /* Initial spinlock for control data */
1294 ctrl = &spdif_priv->fsl_spdif_control;
1295 spin_lock_init(&ctrl->ctl_lock);
1296
1297 /* Init tx channel status default value */
1298 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1299 IEC958_AES0_CON_EMPHASIS_5015;
1300 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1301 ctrl->ch_status[2] = 0x00;
1302 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1303 IEC958_AES3_CON_CLOCK_1000PPM;
1304
1305 spdif_priv->dpll_locked = false;
1306
1307 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
1308 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
1309 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1310 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1311
1312 /* Register with ASoC */
1313 dev_set_drvdata(&pdev->dev, spdif_priv);
1314
1315 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1316 &spdif_priv->cpu_dai_drv, 1);
1317 if (ret) {
1318 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1319 return ret;
1320 }
1321
1322 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
1323 if (ret && ret != -EPROBE_DEFER)
1324 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
1325
1326 return ret;
1327 }
1328
1329 #ifdef CONFIG_PM_SLEEP
1330 static int fsl_spdif_suspend(struct device *dev)
1331 {
1332 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1333
1334 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
1335 &spdif_priv->regcache_srpc);
1336
1337 regcache_cache_only(spdif_priv->regmap, true);
1338 regcache_mark_dirty(spdif_priv->regmap);
1339
1340 return 0;
1341 }
1342
1343 static int fsl_spdif_resume(struct device *dev)
1344 {
1345 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1346
1347 regcache_cache_only(spdif_priv->regmap, false);
1348
1349 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
1350 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
1351 spdif_priv->regcache_srpc);
1352
1353 return regcache_sync(spdif_priv->regmap);
1354 }
1355 #endif /* CONFIG_PM_SLEEP */
1356
1357 static const struct dev_pm_ops fsl_spdif_pm = {
1358 SET_SYSTEM_SLEEP_PM_OPS(fsl_spdif_suspend, fsl_spdif_resume)
1359 };
1360
1361 static const struct of_device_id fsl_spdif_dt_ids[] = {
1362 { .compatible = "fsl,imx35-spdif", },
1363 { .compatible = "fsl,vf610-spdif", },
1364 {}
1365 };
1366 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1367
1368 static struct platform_driver fsl_spdif_driver = {
1369 .driver = {
1370 .name = "fsl-spdif-dai",
1371 .of_match_table = fsl_spdif_dt_ids,
1372 .pm = &fsl_spdif_pm,
1373 },
1374 .probe = fsl_spdif_probe,
1375 };
1376
1377 module_platform_driver(fsl_spdif_driver);
1378
1379 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1380 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1381 MODULE_LICENSE("GPL v2");
1382 MODULE_ALIAS("platform:fsl-spdif-dai");
Linux with added FPC-III support