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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / sound / soc / intel / skylake / skl-pcm.c
blobb99509675d29a270437833cd552cb5b850c15900
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 *
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 */
12
13 #include <linux/pci.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/delay.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
18 #include "skl.h"
19 #include "skl-topology.h"
20 #include "skl-sst-dsp.h"
21 #include "skl-sst-ipc.h"
22
23 #define HDA_MONO 1
24 #define HDA_STEREO 2
25 #define HDA_QUAD 4
26 #define HDA_MAX 8
27
28 static const struct snd_pcm_hardware azx_pcm_hw = {
29 .info = (SNDRV_PCM_INFO_MMAP |
30 SNDRV_PCM_INFO_INTERLEAVED |
31 SNDRV_PCM_INFO_BLOCK_TRANSFER |
32 SNDRV_PCM_INFO_MMAP_VALID |
33 SNDRV_PCM_INFO_PAUSE |
34 SNDRV_PCM_INFO_RESUME |
35 SNDRV_PCM_INFO_SYNC_START |
36 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
37 SNDRV_PCM_INFO_HAS_LINK_ATIME |
38 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
39 .formats = SNDRV_PCM_FMTBIT_S16_LE |
40 SNDRV_PCM_FMTBIT_S32_LE |
41 SNDRV_PCM_FMTBIT_S24_LE,
42 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
43 SNDRV_PCM_RATE_8000,
44 .rate_min = 8000,
45 .rate_max = 48000,
46 .channels_min = 1,
47 .channels_max = 8,
48 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
49 .period_bytes_min = 128,
50 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
51 .periods_min = 2,
52 .periods_max = AZX_MAX_FRAG,
53 .fifo_size = 0,
54 };
55
56 static inline
57 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
58 {
59 return substream->runtime->private_data;
60 }
61
62 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
63 {
64 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
65 struct hdac_stream *hstream = hdac_stream(stream);
66 struct hdac_bus *bus = hstream->bus;
67 return bus;
68 }
69
70 static int skl_substream_alloc_pages(struct hdac_bus *bus,
71 struct snd_pcm_substream *substream,
72 size_t size)
73 {
74 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
75
76 hdac_stream(stream)->bufsize = 0;
77 hdac_stream(stream)->period_bytes = 0;
78 hdac_stream(stream)->format_val = 0;
79
80 return 0;
81 }
82
83 static void skl_set_pcm_constrains(struct hdac_bus *bus,
84 struct snd_pcm_runtime *runtime)
85 {
86 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
87
88 /* avoid wrap-around with wall-clock */
89 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
90 20, 178000000);
91 }
92
93 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
94 {
95 if (bus->ppcap)
96 return HDAC_EXT_STREAM_TYPE_HOST;
97 else
98 return HDAC_EXT_STREAM_TYPE_COUPLED;
99 }
100
101 /*
102 * check if the stream opened is marked as ignore_suspend by machine, if so
103 * then enable suspend_active refcount
104 *
105 * The count supend_active does not need lock as it is used in open/close
106 * and suspend context
107 */
108 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
109 struct snd_soc_dai *dai, bool enable)
110 {
111 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
112 struct snd_soc_dapm_widget *w;
113 struct skl_dev *skl = bus_to_skl(bus);
114
115 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
116 w = dai->playback_widget;
117 else
118 w = dai->capture_widget;
119
120 if (w->ignore_suspend && enable)
121 skl->supend_active++;
122 else if (w->ignore_suspend && !enable)
123 skl->supend_active--;
124 }
125
126 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
127 {
128 struct hdac_bus *bus = dev_get_drvdata(dev);
129 struct skl_dev *skl = bus_to_skl(bus);
130 unsigned int format_val;
131 struct hdac_stream *hstream;
132 struct hdac_ext_stream *stream;
133 int err;
134
135 hstream = snd_hdac_get_stream(bus, params->stream,
136 params->host_dma_id + 1);
137 if (!hstream)
138 return -EINVAL;
139
140 stream = stream_to_hdac_ext_stream(hstream);
141 snd_hdac_ext_stream_decouple(bus, stream, true);
142
143 format_val = snd_hdac_calc_stream_format(params->s_freq,
144 params->ch, params->format, params->host_bps, 0);
145
146 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
147 format_val, params->s_freq, params->ch, params->format);
148
149 snd_hdac_stream_reset(hdac_stream(stream));
150 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
151 if (err < 0)
152 return err;
153
154 /*
155 * The recommended SDxFMT programming sequence for BXT
156 * platforms is to couple the stream before writing the format
157 */
158 if (IS_BXT(skl->pci)) {
159 snd_hdac_ext_stream_decouple(bus, stream, false);
160 err = snd_hdac_stream_setup(hdac_stream(stream));
161 snd_hdac_ext_stream_decouple(bus, stream, true);
162 } else {
163 err = snd_hdac_stream_setup(hdac_stream(stream));
164 }
165
166 if (err < 0)
167 return err;
168
169 hdac_stream(stream)->prepared = 1;
170
171 return 0;
172 }
173
174 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
175 {
176 struct hdac_bus *bus = dev_get_drvdata(dev);
177 unsigned int format_val;
178 struct hdac_stream *hstream;
179 struct hdac_ext_stream *stream;
180 struct hdac_ext_link *link;
181 unsigned char stream_tag;
182
183 hstream = snd_hdac_get_stream(bus, params->stream,
184 params->link_dma_id + 1);
185 if (!hstream)
186 return -EINVAL;
187
188 stream = stream_to_hdac_ext_stream(hstream);
189 snd_hdac_ext_stream_decouple(bus, stream, true);
190 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
191 params->format, params->link_bps, 0);
192
193 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
194 format_val, params->s_freq, params->ch, params->format);
195
196 snd_hdac_ext_link_stream_reset(stream);
197
198 snd_hdac_ext_link_stream_setup(stream, format_val);
199
200 stream_tag = hstream->stream_tag;
201 if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
202 list_for_each_entry(link, &bus->hlink_list, list) {
203 if (link->index == params->link_index)
204 snd_hdac_ext_link_set_stream_id(link,
205 stream_tag);
206 }
207 }
208
209 stream->link_prepared = 1;
210
211 return 0;
212 }
213
214 static int skl_pcm_open(struct snd_pcm_substream *substream,
215 struct snd_soc_dai *dai)
216 {
217 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
218 struct hdac_ext_stream *stream;
219 struct snd_pcm_runtime *runtime = substream->runtime;
220 struct skl_dma_params *dma_params;
221 struct skl_dev *skl = get_skl_ctx(dai->dev);
222 struct skl_module_cfg *mconfig;
223
224 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
225
226 stream = snd_hdac_ext_stream_assign(bus, substream,
227 skl_get_host_stream_type(bus));
228 if (stream == NULL)
229 return -EBUSY;
230
231 skl_set_pcm_constrains(bus, runtime);
232
233 /*
234 * disable WALLCLOCK timestamps for capture streams
235 * until we figure out how to handle digital inputs
236 */
237 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
238 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
239 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
240 }
241
242 runtime->private_data = stream;
243
244 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
245 if (!dma_params)
246 return -ENOMEM;
247
248 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
249 snd_soc_dai_set_dma_data(dai, substream, dma_params);
250
251 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
252 dma_params->stream_tag);
253 skl_set_suspend_active(substream, dai, true);
254 snd_pcm_set_sync(substream);
255
256 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
257 if (!mconfig)
258 return -EINVAL;
259
260 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
261
262 return 0;
263 }
264
265 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
266 struct snd_soc_dai *dai)
267 {
268 struct skl_dev *skl = get_skl_ctx(dai->dev);
269 struct skl_module_cfg *mconfig;
270 int ret;
271
272 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
273
274 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
275
276 /*
277 * In case of XRUN recovery or in the case when the application
278 * calls prepare another time, reset the FW pipe to clean state
279 */
280 if (mconfig &&
281 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN ||
282 mconfig->pipe->state == SKL_PIPE_CREATED ||
283 mconfig->pipe->state == SKL_PIPE_PAUSED)) {
284
285 ret = skl_reset_pipe(skl, mconfig->pipe);
286
287 if (ret < 0)
288 return ret;
289
290 ret = skl_pcm_host_dma_prepare(dai->dev,
291 mconfig->pipe->p_params);
292 if (ret < 0)
293 return ret;
294 }
295
296 return 0;
297 }
298
299 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
300 struct snd_pcm_hw_params *params,
301 struct snd_soc_dai *dai)
302 {
303 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
304 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
305 struct snd_pcm_runtime *runtime = substream->runtime;
306 struct skl_pipe_params p_params = {0};
307 struct skl_module_cfg *m_cfg;
308 int ret, dma_id;
309
310 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
311 ret = skl_substream_alloc_pages(bus, substream,
312 params_buffer_bytes(params));
313 if (ret < 0)
314 return ret;
315
316 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
317 runtime->rate, runtime->channels, runtime->format);
318
319 dma_id = hdac_stream(stream)->stream_tag - 1;
320 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
321
322 p_params.s_fmt = snd_pcm_format_width(params_format(params));
323 p_params.ch = params_channels(params);
324 p_params.s_freq = params_rate(params);
325 p_params.host_dma_id = dma_id;
326 p_params.stream = substream->stream;
327 p_params.format = params_format(params);
328 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
329 p_params.host_bps = dai->driver->playback.sig_bits;
330 else
331 p_params.host_bps = dai->driver->capture.sig_bits;
332
333
334 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
335 if (m_cfg)
336 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
337
338 return 0;
339 }
340
341 static void skl_pcm_close(struct snd_pcm_substream *substream,
342 struct snd_soc_dai *dai)
343 {
344 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
345 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
346 struct skl_dma_params *dma_params = NULL;
347 struct skl_dev *skl = bus_to_skl(bus);
348 struct skl_module_cfg *mconfig;
349
350 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
351
352 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
353
354 dma_params = snd_soc_dai_get_dma_data(dai, substream);
355 /*
356 * now we should set this to NULL as we are freeing by the
357 * dma_params
358 */
359 snd_soc_dai_set_dma_data(dai, substream, NULL);
360 skl_set_suspend_active(substream, dai, false);
361
362 /*
363 * check if close is for "Reference Pin" and set back the
364 * CGCTL.MISCBDCGE if disabled by driver
365 */
366 if (!strncmp(dai->name, "Reference Pin", 13) &&
367 skl->miscbdcg_disabled) {
368 skl->enable_miscbdcge(dai->dev, true);
369 skl->miscbdcg_disabled = false;
370 }
371
372 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
373 if (mconfig)
374 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
375
376 kfree(dma_params);
377 }
378
379 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
380 struct snd_soc_dai *dai)
381 {
382 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
383 struct skl_dev *skl = get_skl_ctx(dai->dev);
384 struct skl_module_cfg *mconfig;
385 int ret;
386
387 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
388
389 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
390
391 if (mconfig) {
392 ret = skl_reset_pipe(skl, mconfig->pipe);
393 if (ret < 0)
394 dev_err(dai->dev, "%s:Reset failed ret =%d",
395 __func__, ret);
396 }
397
398 snd_hdac_stream_cleanup(hdac_stream(stream));
399 hdac_stream(stream)->prepared = 0;
400
401 return 0;
402 }
403
404 static int skl_be_hw_params(struct snd_pcm_substream *substream,
405 struct snd_pcm_hw_params *params,
406 struct snd_soc_dai *dai)
407 {
408 struct skl_pipe_params p_params = {0};
409
410 p_params.s_fmt = snd_pcm_format_width(params_format(params));
411 p_params.ch = params_channels(params);
412 p_params.s_freq = params_rate(params);
413 p_params.stream = substream->stream;
414
415 return skl_tplg_be_update_params(dai, &p_params);
416 }
417
418 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
419 int cmd)
420 {
421 struct hdac_bus *bus = get_bus_ctx(substream);
422 struct hdac_ext_stream *stream;
423 int start;
424 unsigned long cookie;
425 struct hdac_stream *hstr;
426
427 stream = get_hdac_ext_stream(substream);
428 hstr = hdac_stream(stream);
429
430 if (!hstr->prepared)
431 return -EPIPE;
432
433 switch (cmd) {
434 case SNDRV_PCM_TRIGGER_START:
435 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
436 case SNDRV_PCM_TRIGGER_RESUME:
437 start = 1;
438 break;
439
440 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
441 case SNDRV_PCM_TRIGGER_SUSPEND:
442 case SNDRV_PCM_TRIGGER_STOP:
443 start = 0;
444 break;
445
446 default:
447 return -EINVAL;
448 }
449
450 spin_lock_irqsave(&bus->reg_lock, cookie);
451
452 if (start) {
453 snd_hdac_stream_start(hdac_stream(stream), true);
454 snd_hdac_stream_timecounter_init(hstr, 0);
455 } else {
456 snd_hdac_stream_stop(hdac_stream(stream));
457 }
458
459 spin_unlock_irqrestore(&bus->reg_lock, cookie);
460
461 return 0;
462 }
463
464 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
465 struct snd_soc_dai *dai)
466 {
467 struct skl_dev *skl = get_skl_ctx(dai->dev);
468 struct skl_module_cfg *mconfig;
469 struct hdac_bus *bus = get_bus_ctx(substream);
470 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
471 struct snd_soc_dapm_widget *w;
472 int ret;
473
474 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
475 if (!mconfig)
476 return -EIO;
477
478 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
479 w = dai->playback_widget;
480 else
481 w = dai->capture_widget;
482
483 switch (cmd) {
484 case SNDRV_PCM_TRIGGER_RESUME:
485 if (!w->ignore_suspend) {
486 /*
487 * enable DMA Resume enable bit for the stream, set the
488 * dpib & lpib position to resume before starting the
489 * DMA
490 */
491 snd_hdac_ext_stream_drsm_enable(bus, true,
492 hdac_stream(stream)->index);
493 snd_hdac_ext_stream_set_dpibr(bus, stream,
494 stream->lpib);
495 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
496 }
497 /* fall through */
498
499 case SNDRV_PCM_TRIGGER_START:
500 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
501 /*
502 * Start HOST DMA and Start FE Pipe.This is to make sure that
503 * there are no underrun/overrun in the case when the FE
504 * pipeline is started but there is a delay in starting the
505 * DMA channel on the host.
506 */
507 ret = skl_decoupled_trigger(substream, cmd);
508 if (ret < 0)
509 return ret;
510 return skl_run_pipe(skl, mconfig->pipe);
511 break;
512
513 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
514 case SNDRV_PCM_TRIGGER_SUSPEND:
515 case SNDRV_PCM_TRIGGER_STOP:
516 /*
517 * Stop FE Pipe first and stop DMA. This is to make sure that
518 * there are no underrun/overrun in the case if there is a delay
519 * between the two operations.
520 */
521 ret = skl_stop_pipe(skl, mconfig->pipe);
522 if (ret < 0)
523 return ret;
524
525 ret = skl_decoupled_trigger(substream, cmd);
526 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
527 /* save the dpib and lpib positions */
528 stream->dpib = readl(bus->remap_addr +
529 AZX_REG_VS_SDXDPIB_XBASE +
530 (AZX_REG_VS_SDXDPIB_XINTERVAL *
531 hdac_stream(stream)->index));
532
533 stream->lpib = snd_hdac_stream_get_pos_lpib(
534 hdac_stream(stream));
535 snd_hdac_ext_stream_decouple(bus, stream, false);
536 }
537 break;
538
539 default:
540 return -EINVAL;
541 }
542
543 return 0;
544 }
545
546
547 static int skl_link_hw_params(struct snd_pcm_substream *substream,
548 struct snd_pcm_hw_params *params,
549 struct snd_soc_dai *dai)
550 {
551 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
552 struct hdac_ext_stream *link_dev;
553 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
554 struct snd_soc_dai *codec_dai = rtd->codec_dai;
555 struct skl_pipe_params p_params = {0};
556 struct hdac_ext_link *link;
557 int stream_tag;
558
559 link_dev = snd_hdac_ext_stream_assign(bus, substream,
560 HDAC_EXT_STREAM_TYPE_LINK);
561 if (!link_dev)
562 return -EBUSY;
563
564 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
565
566 link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name);
567 if (!link)
568 return -EINVAL;
569
570 stream_tag = hdac_stream(link_dev)->stream_tag;
571
572 /* set the stream tag in the codec dai dma params */
573 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
574 snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0);
575 else
576 snd_soc_dai_set_tdm_slot(codec_dai, 0, stream_tag, 0, 0);
577
578 p_params.s_fmt = snd_pcm_format_width(params_format(params));
579 p_params.ch = params_channels(params);
580 p_params.s_freq = params_rate(params);
581 p_params.stream = substream->stream;
582 p_params.link_dma_id = stream_tag - 1;
583 p_params.link_index = link->index;
584 p_params.format = params_format(params);
585
586 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
587 p_params.link_bps = codec_dai->driver->playback.sig_bits;
588 else
589 p_params.link_bps = codec_dai->driver->capture.sig_bits;
590
591 return skl_tplg_be_update_params(dai, &p_params);
592 }
593
594 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
595 struct snd_soc_dai *dai)
596 {
597 struct skl_dev *skl = get_skl_ctx(dai->dev);
598 struct skl_module_cfg *mconfig = NULL;
599
600 /* In case of XRUN recovery, reset the FW pipe to clean state */
601 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
602 if (mconfig && !mconfig->pipe->passthru &&
603 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN))
604 skl_reset_pipe(skl, mconfig->pipe);
605
606 return 0;
607 }
608
609 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
610 int cmd, struct snd_soc_dai *dai)
611 {
612 struct hdac_ext_stream *link_dev =
613 snd_soc_dai_get_dma_data(dai, substream);
614 struct hdac_bus *bus = get_bus_ctx(substream);
615 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
616
617 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
618 switch (cmd) {
619 case SNDRV_PCM_TRIGGER_RESUME:
620 case SNDRV_PCM_TRIGGER_START:
621 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
622 snd_hdac_ext_link_stream_start(link_dev);
623 break;
624
625 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
626 case SNDRV_PCM_TRIGGER_SUSPEND:
627 case SNDRV_PCM_TRIGGER_STOP:
628 snd_hdac_ext_link_stream_clear(link_dev);
629 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
630 snd_hdac_ext_stream_decouple(bus, stream, false);
631 break;
632
633 default:
634 return -EINVAL;
635 }
636 return 0;
637 }
638
639 static int skl_link_hw_free(struct snd_pcm_substream *substream,
640 struct snd_soc_dai *dai)
641 {
642 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
643 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
644 struct hdac_ext_stream *link_dev =
645 snd_soc_dai_get_dma_data(dai, substream);
646 struct hdac_ext_link *link;
647 unsigned char stream_tag;
648
649 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
650
651 link_dev->link_prepared = 0;
652
653 link = snd_hdac_ext_bus_get_link(bus, rtd->codec_dai->component->name);
654 if (!link)
655 return -EINVAL;
656
657 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
658 stream_tag = hdac_stream(link_dev)->stream_tag;
659 snd_hdac_ext_link_clear_stream_id(link, stream_tag);
660 }
661
662 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
663 return 0;
664 }
665
666 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
667 .startup = skl_pcm_open,
668 .shutdown = skl_pcm_close,
669 .prepare = skl_pcm_prepare,
670 .hw_params = skl_pcm_hw_params,
671 .hw_free = skl_pcm_hw_free,
672 .trigger = skl_pcm_trigger,
673 };
674
675 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
676 .hw_params = skl_be_hw_params,
677 };
678
679 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
680 .hw_params = skl_be_hw_params,
681 };
682
683 static const struct snd_soc_dai_ops skl_link_dai_ops = {
684 .prepare = skl_link_pcm_prepare,
685 .hw_params = skl_link_hw_params,
686 .hw_free = skl_link_hw_free,
687 .trigger = skl_link_pcm_trigger,
688 };
689
690 static struct snd_soc_dai_driver skl_fe_dai[] = {
691 {
692 .name = "System Pin",
693 .ops = &skl_pcm_dai_ops,
694 .playback = {
695 .stream_name = "System Playback",
696 .channels_min = HDA_MONO,
697 .channels_max = HDA_STEREO,
698 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
699 .formats = SNDRV_PCM_FMTBIT_S16_LE |
700 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
701 .sig_bits = 32,
702 },
703 .capture = {
704 .stream_name = "System Capture",
705 .channels_min = HDA_MONO,
706 .channels_max = HDA_STEREO,
707 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
708 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
709 .sig_bits = 32,
710 },
711 },
712 {
713 .name = "System Pin2",
714 .ops = &skl_pcm_dai_ops,
715 .playback = {
716 .stream_name = "Headset Playback",
717 .channels_min = HDA_MONO,
718 .channels_max = HDA_STEREO,
719 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
720 SNDRV_PCM_RATE_8000,
721 .formats = SNDRV_PCM_FMTBIT_S16_LE |
722 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
723 },
724 },
725 {
726 .name = "Echoref Pin",
727 .ops = &skl_pcm_dai_ops,
728 .capture = {
729 .stream_name = "Echoreference Capture",
730 .channels_min = HDA_STEREO,
731 .channels_max = HDA_STEREO,
732 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
733 SNDRV_PCM_RATE_8000,
734 .formats = SNDRV_PCM_FMTBIT_S16_LE |
735 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
736 },
737 },
738 {
739 .name = "Reference Pin",
740 .ops = &skl_pcm_dai_ops,
741 .capture = {
742 .stream_name = "Reference Capture",
743 .channels_min = HDA_MONO,
744 .channels_max = HDA_QUAD,
745 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
746 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
747 .sig_bits = 32,
748 },
749 },
750 {
751 .name = "Deepbuffer Pin",
752 .ops = &skl_pcm_dai_ops,
753 .playback = {
754 .stream_name = "Deepbuffer Playback",
755 .channels_min = HDA_STEREO,
756 .channels_max = HDA_STEREO,
757 .rates = SNDRV_PCM_RATE_48000,
758 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
759 .sig_bits = 32,
760 },
761 },
762 {
763 .name = "LowLatency Pin",
764 .ops = &skl_pcm_dai_ops,
765 .playback = {
766 .stream_name = "Low Latency Playback",
767 .channels_min = HDA_STEREO,
768 .channels_max = HDA_STEREO,
769 .rates = SNDRV_PCM_RATE_48000,
770 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
771 .sig_bits = 32,
772 },
773 },
774 {
775 .name = "DMIC Pin",
776 .ops = &skl_pcm_dai_ops,
777 .capture = {
778 .stream_name = "DMIC Capture",
779 .channels_min = HDA_MONO,
780 .channels_max = HDA_QUAD,
781 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
782 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
783 .sig_bits = 32,
784 },
785 },
786 {
787 .name = "HDMI1 Pin",
788 .ops = &skl_pcm_dai_ops,
789 .playback = {
790 .stream_name = "HDMI1 Playback",
791 .channels_min = HDA_STEREO,
792 .channels_max = 8,
793 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
794 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
795 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
796 SNDRV_PCM_RATE_192000,
797 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
798 SNDRV_PCM_FMTBIT_S32_LE,
799 .sig_bits = 32,
800 },
801 },
802 {
803 .name = "HDMI2 Pin",
804 .ops = &skl_pcm_dai_ops,
805 .playback = {
806 .stream_name = "HDMI2 Playback",
807 .channels_min = HDA_STEREO,
808 .channels_max = 8,
809 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
810 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
811 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
812 SNDRV_PCM_RATE_192000,
813 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
814 SNDRV_PCM_FMTBIT_S32_LE,
815 .sig_bits = 32,
816 },
817 },
818 {
819 .name = "HDMI3 Pin",
820 .ops = &skl_pcm_dai_ops,
821 .playback = {
822 .stream_name = "HDMI3 Playback",
823 .channels_min = HDA_STEREO,
824 .channels_max = 8,
825 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
826 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
827 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
828 SNDRV_PCM_RATE_192000,
829 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
830 SNDRV_PCM_FMTBIT_S32_LE,
831 .sig_bits = 32,
832 },
833 },
834 };
835
836 /* BE CPU Dais */
837 static struct snd_soc_dai_driver skl_platform_dai[] = {
838 {
839 .name = "SSP0 Pin",
840 .ops = &skl_be_ssp_dai_ops,
841 .playback = {
842 .stream_name = "ssp0 Tx",
843 .channels_min = HDA_STEREO,
844 .channels_max = HDA_STEREO,
845 .rates = SNDRV_PCM_RATE_48000,
846 .formats = SNDRV_PCM_FMTBIT_S16_LE,
847 },
848 .capture = {
849 .stream_name = "ssp0 Rx",
850 .channels_min = HDA_STEREO,
851 .channels_max = HDA_STEREO,
852 .rates = SNDRV_PCM_RATE_48000,
853 .formats = SNDRV_PCM_FMTBIT_S16_LE,
854 },
855 },
856 {
857 .name = "SSP1 Pin",
858 .ops = &skl_be_ssp_dai_ops,
859 .playback = {
860 .stream_name = "ssp1 Tx",
861 .channels_min = HDA_STEREO,
862 .channels_max = HDA_STEREO,
863 .rates = SNDRV_PCM_RATE_48000,
864 .formats = SNDRV_PCM_FMTBIT_S16_LE,
865 },
866 .capture = {
867 .stream_name = "ssp1 Rx",
868 .channels_min = HDA_STEREO,
869 .channels_max = HDA_STEREO,
870 .rates = SNDRV_PCM_RATE_48000,
871 .formats = SNDRV_PCM_FMTBIT_S16_LE,
872 },
873 },
874 {
875 .name = "SSP2 Pin",
876 .ops = &skl_be_ssp_dai_ops,
877 .playback = {
878 .stream_name = "ssp2 Tx",
879 .channels_min = HDA_STEREO,
880 .channels_max = HDA_STEREO,
881 .rates = SNDRV_PCM_RATE_48000,
882 .formats = SNDRV_PCM_FMTBIT_S16_LE,
883 },
884 .capture = {
885 .stream_name = "ssp2 Rx",
886 .channels_min = HDA_STEREO,
887 .channels_max = HDA_STEREO,
888 .rates = SNDRV_PCM_RATE_48000,
889 .formats = SNDRV_PCM_FMTBIT_S16_LE,
890 },
891 },
892 {
893 .name = "SSP3 Pin",
894 .ops = &skl_be_ssp_dai_ops,
895 .playback = {
896 .stream_name = "ssp3 Tx",
897 .channels_min = HDA_STEREO,
898 .channels_max = HDA_STEREO,
899 .rates = SNDRV_PCM_RATE_48000,
900 .formats = SNDRV_PCM_FMTBIT_S16_LE,
901 },
902 .capture = {
903 .stream_name = "ssp3 Rx",
904 .channels_min = HDA_STEREO,
905 .channels_max = HDA_STEREO,
906 .rates = SNDRV_PCM_RATE_48000,
907 .formats = SNDRV_PCM_FMTBIT_S16_LE,
908 },
909 },
910 {
911 .name = "SSP4 Pin",
912 .ops = &skl_be_ssp_dai_ops,
913 .playback = {
914 .stream_name = "ssp4 Tx",
915 .channels_min = HDA_STEREO,
916 .channels_max = HDA_STEREO,
917 .rates = SNDRV_PCM_RATE_48000,
918 .formats = SNDRV_PCM_FMTBIT_S16_LE,
919 },
920 .capture = {
921 .stream_name = "ssp4 Rx",
922 .channels_min = HDA_STEREO,
923 .channels_max = HDA_STEREO,
924 .rates = SNDRV_PCM_RATE_48000,
925 .formats = SNDRV_PCM_FMTBIT_S16_LE,
926 },
927 },
928 {
929 .name = "SSP5 Pin",
930 .ops = &skl_be_ssp_dai_ops,
931 .playback = {
932 .stream_name = "ssp5 Tx",
933 .channels_min = HDA_STEREO,
934 .channels_max = HDA_STEREO,
935 .rates = SNDRV_PCM_RATE_48000,
936 .formats = SNDRV_PCM_FMTBIT_S16_LE,
937 },
938 .capture = {
939 .stream_name = "ssp5 Rx",
940 .channels_min = HDA_STEREO,
941 .channels_max = HDA_STEREO,
942 .rates = SNDRV_PCM_RATE_48000,
943 .formats = SNDRV_PCM_FMTBIT_S16_LE,
944 },
945 },
946 {
947 .name = "iDisp1 Pin",
948 .ops = &skl_link_dai_ops,
949 .playback = {
950 .stream_name = "iDisp1 Tx",
951 .channels_min = HDA_STEREO,
952 .channels_max = 8,
953 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
954 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
955 SNDRV_PCM_FMTBIT_S24_LE,
956 },
957 },
958 {
959 .name = "iDisp2 Pin",
960 .ops = &skl_link_dai_ops,
961 .playback = {
962 .stream_name = "iDisp2 Tx",
963 .channels_min = HDA_STEREO,
964 .channels_max = 8,
965 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
966 SNDRV_PCM_RATE_48000,
967 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
968 SNDRV_PCM_FMTBIT_S24_LE,
969 },
970 },
971 {
972 .name = "iDisp3 Pin",
973 .ops = &skl_link_dai_ops,
974 .playback = {
975 .stream_name = "iDisp3 Tx",
976 .channels_min = HDA_STEREO,
977 .channels_max = 8,
978 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
979 SNDRV_PCM_RATE_48000,
980 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
981 SNDRV_PCM_FMTBIT_S24_LE,
982 },
983 },
984 {
985 .name = "DMIC01 Pin",
986 .ops = &skl_dmic_dai_ops,
987 .capture = {
988 .stream_name = "DMIC01 Rx",
989 .channels_min = HDA_MONO,
990 .channels_max = HDA_QUAD,
991 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
992 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
993 },
994 },
995 {
996 .name = "DMIC16k Pin",
997 .ops = &skl_dmic_dai_ops,
998 .capture = {
999 .stream_name = "DMIC16k Rx",
1000 .channels_min = HDA_MONO,
1001 .channels_max = HDA_QUAD,
1002 .rates = SNDRV_PCM_RATE_16000,
1003 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1004 },
1005 },
1006 {
1007 .name = "Analog CPU DAI",
1008 .ops = &skl_link_dai_ops,
1009 .playback = {
1010 .stream_name = "Analog CPU Playback",
1011 .channels_min = HDA_MONO,
1012 .channels_max = HDA_MAX,
1013 .rates = SNDRV_PCM_RATE_8000_192000,
1014 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1015 SNDRV_PCM_FMTBIT_S32_LE,
1016 },
1017 .capture = {
1018 .stream_name = "Analog CPU Capture",
1019 .channels_min = HDA_MONO,
1020 .channels_max = HDA_MAX,
1021 .rates = SNDRV_PCM_RATE_8000_192000,
1022 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1023 SNDRV_PCM_FMTBIT_S32_LE,
1024 },
1025 },
1026 {
1027 .name = "Alt Analog CPU DAI",
1028 .ops = &skl_link_dai_ops,
1029 .playback = {
1030 .stream_name = "Alt Analog CPU Playback",
1031 .channels_min = HDA_MONO,
1032 .channels_max = HDA_MAX,
1033 .rates = SNDRV_PCM_RATE_8000_192000,
1034 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1035 SNDRV_PCM_FMTBIT_S32_LE,
1036 },
1037 .capture = {
1038 .stream_name = "Alt Analog CPU Capture",
1039 .channels_min = HDA_MONO,
1040 .channels_max = HDA_MAX,
1041 .rates = SNDRV_PCM_RATE_8000_192000,
1042 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1043 SNDRV_PCM_FMTBIT_S32_LE,
1044 },
1045 },
1046 {
1047 .name = "Digital CPU DAI",
1048 .ops = &skl_link_dai_ops,
1049 .playback = {
1050 .stream_name = "Digital CPU Playback",
1051 .channels_min = HDA_MONO,
1052 .channels_max = HDA_MAX,
1053 .rates = SNDRV_PCM_RATE_8000_192000,
1054 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1055 SNDRV_PCM_FMTBIT_S32_LE,
1056 },
1057 .capture = {
1058 .stream_name = "Digital CPU Capture",
1059 .channels_min = HDA_MONO,
1060 .channels_max = HDA_MAX,
1061 .rates = SNDRV_PCM_RATE_8000_192000,
1062 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1063 SNDRV_PCM_FMTBIT_S32_LE,
1064 },
1065 },
1066 };
1067
1068 int skl_dai_load(struct snd_soc_component *cmp, int index,
1069 struct snd_soc_dai_driver *dai_drv,
1070 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1071 {
1072 dai_drv->ops = &skl_pcm_dai_ops;
1073
1074 return 0;
1075 }
1076
1077 static int skl_platform_soc_open(struct snd_soc_component *component,
1078 struct snd_pcm_substream *substream)
1079 {
1080 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1081 struct snd_soc_dai_link *dai_link = rtd->dai_link;
1082
1083 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
1084 dai_link->cpus->dai_name);
1085
1086 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1087
1088 return 0;
1089 }
1090
1091 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1092 int cmd)
1093 {
1094 struct hdac_bus *bus = get_bus_ctx(substream);
1095 struct hdac_ext_stream *stream;
1096 struct snd_pcm_substream *s;
1097 bool start;
1098 int sbits = 0;
1099 unsigned long cookie;
1100 struct hdac_stream *hstr;
1101
1102 stream = get_hdac_ext_stream(substream);
1103 hstr = hdac_stream(stream);
1104
1105 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1106
1107 if (!hstr->prepared)
1108 return -EPIPE;
1109
1110 switch (cmd) {
1111 case SNDRV_PCM_TRIGGER_START:
1112 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1113 case SNDRV_PCM_TRIGGER_RESUME:
1114 start = true;
1115 break;
1116
1117 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1118 case SNDRV_PCM_TRIGGER_SUSPEND:
1119 case SNDRV_PCM_TRIGGER_STOP:
1120 start = false;
1121 break;
1122
1123 default:
1124 return -EINVAL;
1125 }
1126
1127 snd_pcm_group_for_each_entry(s, substream) {
1128 if (s->pcm->card != substream->pcm->card)
1129 continue;
1130 stream = get_hdac_ext_stream(s);
1131 sbits |= 1 << hdac_stream(stream)->index;
1132 snd_pcm_trigger_done(s, substream);
1133 }
1134
1135 spin_lock_irqsave(&bus->reg_lock, cookie);
1136
1137 /* first, set SYNC bits of corresponding streams */
1138 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1139
1140 snd_pcm_group_for_each_entry(s, substream) {
1141 if (s->pcm->card != substream->pcm->card)
1142 continue;
1143 stream = get_hdac_ext_stream(s);
1144 if (start)
1145 snd_hdac_stream_start(hdac_stream(stream), true);
1146 else
1147 snd_hdac_stream_stop(hdac_stream(stream));
1148 }
1149 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1150
1151 snd_hdac_stream_sync(hstr, start, sbits);
1152
1153 spin_lock_irqsave(&bus->reg_lock, cookie);
1154
1155 /* reset SYNC bits */
1156 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1157 if (start)
1158 snd_hdac_stream_timecounter_init(hstr, sbits);
1159 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1160
1161 return 0;
1162 }
1163
1164 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1165 struct snd_pcm_substream *substream,
1166 int cmd)
1167 {
1168 struct hdac_bus *bus = get_bus_ctx(substream);
1169
1170 if (!bus->ppcap)
1171 return skl_coupled_trigger(substream, cmd);
1172
1173 return 0;
1174 }
1175
1176 static snd_pcm_uframes_t skl_platform_soc_pointer(
1177 struct snd_soc_component *component,
1178 struct snd_pcm_substream *substream)
1179 {
1180 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1181 struct hdac_bus *bus = get_bus_ctx(substream);
1182 unsigned int pos;
1183
1184 /*
1185 * Use DPIB for Playback stream as the periodic DMA Position-in-
1186 * Buffer Writes may be scheduled at the same time or later than
1187 * the MSI and does not guarantee to reflect the Position of the
1188 * last buffer that was transferred. Whereas DPIB register in
1189 * HAD space reflects the actual data that is transferred.
1190 * Use the position buffer for capture, as DPIB write gets
1191 * completed earlier than the actual data written to the DDR.
1192 *
1193 * For capture stream following workaround is required to fix the
1194 * incorrect position reporting.
1195 *
1196 * 1. Wait for 20us before reading the DMA position in buffer once
1197 * the interrupt is generated for stream completion as update happens
1198 * on the HDA frame boundary i.e. 20.833uSec.
1199 * 2. Read DPIB register to flush the DMA position value. This dummy
1200 * read is required to flush DMA position value.
1201 * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1202 * or greater than period boundary.
1203 */
1204
1205 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1206 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1207 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1208 hdac_stream(hstream)->index));
1209 } else {
1210 udelay(20);
1211 readl(bus->remap_addr +
1212 AZX_REG_VS_SDXDPIB_XBASE +
1213 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1214 hdac_stream(hstream)->index));
1215 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1216 }
1217
1218 if (pos >= hdac_stream(hstream)->bufsize)
1219 pos = 0;
1220
1221 return bytes_to_frames(substream->runtime, pos);
1222 }
1223
1224 static int skl_platform_soc_mmap(struct snd_soc_component *component,
1225 struct snd_pcm_substream *substream,
1226 struct vm_area_struct *area)
1227 {
1228 return snd_pcm_lib_default_mmap(substream, area);
1229 }
1230
1231 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1232 u64 nsec)
1233 {
1234 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
1235 struct snd_soc_dai *codec_dai = rtd->codec_dai;
1236 u64 codec_frames, codec_nsecs;
1237
1238 if (!codec_dai->driver->ops->delay)
1239 return nsec;
1240
1241 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1242 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1243 substream->runtime->rate);
1244
1245 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1246 return nsec + codec_nsecs;
1247
1248 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1249 }
1250
1251 static int skl_platform_soc_get_time_info(
1252 struct snd_soc_component *component,
1253 struct snd_pcm_substream *substream,
1254 struct timespec64 *system_ts, struct timespec64 *audio_ts,
1255 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1256 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1257 {
1258 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1259 struct hdac_stream *hstr = hdac_stream(sstream);
1260 u64 nsec;
1261
1262 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1263 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1264
1265 snd_pcm_gettime(substream->runtime, system_ts);
1266
1267 nsec = timecounter_read(&hstr->tc);
1268 nsec = div_u64(nsec, 3); /* can be optimized */
1269 if (audio_tstamp_config->report_delay)
1270 nsec = skl_adjust_codec_delay(substream, nsec);
1271
1272 *audio_ts = ns_to_timespec64(nsec);
1273
1274 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1275 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1276 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1277
1278 } else {
1279 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1280 }
1281
1282 return 0;
1283 }
1284
1285 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1286
1287 static int skl_platform_soc_new(struct snd_soc_component *component,
1288 struct snd_soc_pcm_runtime *rtd)
1289 {
1290 struct snd_soc_dai *dai = rtd->cpu_dai;
1291 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1292 struct snd_pcm *pcm = rtd->pcm;
1293 unsigned int size;
1294 struct skl_dev *skl = bus_to_skl(bus);
1295
1296 if (dai->driver->playback.channels_min ||
1297 dai->driver->capture.channels_min) {
1298 /* buffer pre-allocation */
1299 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1300 if (size > MAX_PREALLOC_SIZE)
1301 size = MAX_PREALLOC_SIZE;
1302 snd_pcm_set_managed_buffer_all(pcm,
1303 SNDRV_DMA_TYPE_DEV_SG,
1304 &skl->pci->dev,
1305 size, MAX_PREALLOC_SIZE);
1306 }
1307
1308 return 0;
1309 }
1310
1311 static int skl_get_module_info(struct skl_dev *skl,
1312 struct skl_module_cfg *mconfig)
1313 {
1314 struct skl_module_inst_id *pin_id;
1315 guid_t *uuid_mod, *uuid_tplg;
1316 struct skl_module *skl_module;
1317 struct uuid_module *module;
1318 int i, ret = -EIO;
1319
1320 uuid_mod = (guid_t *)mconfig->guid;
1321
1322 if (list_empty(&skl->uuid_list)) {
1323 dev_err(skl->dev, "Module list is empty\n");
1324 return -EIO;
1325 }
1326
1327 list_for_each_entry(module, &skl->uuid_list, list) {
1328 if (guid_equal(uuid_mod, &module->uuid)) {
1329 mconfig->id.module_id = module->id;
1330 if (mconfig->module)
1331 mconfig->module->loadable = module->is_loadable;
1332 ret = 0;
1333 break;
1334 }
1335 }
1336
1337 if (ret)
1338 return ret;
1339
1340 uuid_mod = &module->uuid;
1341 ret = -EIO;
1342 for (i = 0; i < skl->nr_modules; i++) {
1343 skl_module = skl->modules[i];
1344 uuid_tplg = &skl_module->uuid;
1345 if (guid_equal(uuid_mod, uuid_tplg)) {
1346 mconfig->module = skl_module;
1347 ret = 0;
1348 break;
1349 }
1350 }
1351 if (skl->nr_modules && ret)
1352 return ret;
1353
1354 list_for_each_entry(module, &skl->uuid_list, list) {
1355 for (i = 0; i < MAX_IN_QUEUE; i++) {
1356 pin_id = &mconfig->m_in_pin[i].id;
1357 if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1358 pin_id->module_id = module->id;
1359 }
1360
1361 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1362 pin_id = &mconfig->m_out_pin[i].id;
1363 if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1364 pin_id->module_id = module->id;
1365 }
1366 }
1367
1368 return 0;
1369 }
1370
1371 static int skl_populate_modules(struct skl_dev *skl)
1372 {
1373 struct skl_pipeline *p;
1374 struct skl_pipe_module *m;
1375 struct snd_soc_dapm_widget *w;
1376 struct skl_module_cfg *mconfig;
1377 int ret = 0;
1378
1379 list_for_each_entry(p, &skl->ppl_list, node) {
1380 list_for_each_entry(m, &p->pipe->w_list, node) {
1381 w = m->w;
1382 mconfig = w->priv;
1383
1384 ret = skl_get_module_info(skl, mconfig);
1385 if (ret < 0) {
1386 dev_err(skl->dev,
1387 "query module info failed\n");
1388 return ret;
1389 }
1390
1391 skl_tplg_add_moduleid_in_bind_params(skl, w);
1392 }
1393 }
1394
1395 return ret;
1396 }
1397
1398 static int skl_platform_soc_probe(struct snd_soc_component *component)
1399 {
1400 struct hdac_bus *bus = dev_get_drvdata(component->dev);
1401 struct skl_dev *skl = bus_to_skl(bus);
1402 const struct skl_dsp_ops *ops;
1403 int ret;
1404
1405 pm_runtime_get_sync(component->dev);
1406 if (bus->ppcap) {
1407 skl->component = component;
1408
1409 /* init debugfs */
1410 skl->debugfs = skl_debugfs_init(skl);
1411
1412 ret = skl_tplg_init(component, bus);
1413 if (ret < 0) {
1414 dev_err(component->dev, "Failed to init topology!\n");
1415 return ret;
1416 }
1417
1418 /* load the firmwares, since all is set */
1419 ops = skl_get_dsp_ops(skl->pci->device);
1420 if (!ops)
1421 return -EIO;
1422
1423 /*
1424 * Disable dynamic clock and power gating during firmware
1425 * and library download
1426 */
1427 skl->enable_miscbdcge(component->dev, false);
1428 skl->clock_power_gating(component->dev, false);
1429
1430 ret = ops->init_fw(component->dev, skl);
1431 skl->enable_miscbdcge(component->dev, true);
1432 skl->clock_power_gating(component->dev, true);
1433 if (ret < 0) {
1434 dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1435 return ret;
1436 }
1437 skl_populate_modules(skl);
1438 skl->update_d0i3c = skl_update_d0i3c;
1439
1440 if (skl->cfg.astate_cfg != NULL) {
1441 skl_dsp_set_astate_cfg(skl,
1442 skl->cfg.astate_cfg->count,
1443 skl->cfg.astate_cfg);
1444 }
1445 }
1446 pm_runtime_mark_last_busy(component->dev);
1447 pm_runtime_put_autosuspend(component->dev);
1448
1449 return 0;
1450 }
1451
1452 static void skl_platform_soc_remove(struct snd_soc_component *component)
1453 {
1454 struct hdac_bus *bus = dev_get_drvdata(component->dev);
1455 struct skl_dev *skl = bus_to_skl(bus);
1456
1457 skl_tplg_exit(component, bus);
1458
1459 skl_debugfs_exit(skl);
1460 }
1461
1462 static const struct snd_soc_component_driver skl_component = {
1463 .name = "pcm",
1464 .probe = skl_platform_soc_probe,
1465 .remove = skl_platform_soc_remove,
1466 .open = skl_platform_soc_open,
1467 .trigger = skl_platform_soc_trigger,
1468 .pointer = skl_platform_soc_pointer,
1469 .get_time_info = skl_platform_soc_get_time_info,
1470 .mmap = skl_platform_soc_mmap,
1471 .pcm_construct = skl_platform_soc_new,
1472 .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1473 };
1474
1475 int skl_platform_register(struct device *dev)
1476 {
1477 int ret;
1478 struct snd_soc_dai_driver *dais;
1479 int num_dais = ARRAY_SIZE(skl_platform_dai);
1480 struct hdac_bus *bus = dev_get_drvdata(dev);
1481 struct skl_dev *skl = bus_to_skl(bus);
1482
1483 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1484 GFP_KERNEL);
1485 if (!skl->dais) {
1486 ret = -ENOMEM;
1487 goto err;
1488 }
1489
1490 if (!skl->use_tplg_pcm) {
1491 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1492 sizeof(skl_platform_dai), GFP_KERNEL);
1493 if (!dais) {
1494 ret = -ENOMEM;
1495 goto err;
1496 }
1497
1498 skl->dais = dais;
1499 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1500 sizeof(skl_fe_dai));
1501 num_dais += ARRAY_SIZE(skl_fe_dai);
1502 }
1503
1504 ret = devm_snd_soc_register_component(dev, &skl_component,
1505 skl->dais, num_dais);
1506 if (ret)
1507 dev_err(dev, "soc component registration failed %d\n", ret);
1508 err:
1509 return ret;
1510 }
1511
1512 int skl_platform_unregister(struct device *dev)
1513 {
1514 struct hdac_bus *bus = dev_get_drvdata(dev);
1515 struct skl_dev *skl = bus_to_skl(bus);
1516 struct skl_module_deferred_bind *modules, *tmp;
1517
1518 if (!list_empty(&skl->bind_list)) {
1519 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1520 list_del(&modules->node);
1521 kfree(modules);
1522 }
1523 }
1524
1525 kfree(skl->dais);
1526
1527 return 0;
1528 }
Linux with added FPC-III support