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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / sound / soc / pxa / pxa-ssp.c
blobe615acaa0199ce419fdb633400679ddd789cc3ba
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * pxa-ssp.c -- ALSA Soc Audio Layer
4 *
5 * Copyright 2005,2008 Wolfson Microelectronics PLC.
6 * Author: Liam Girdwood
7 * Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * TODO:
10 * o Test network mode for > 16bit sample size
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/pxa2xx_ssp.h>
20 #include <linux/of.h>
21 #include <linux/dmaengine.h>
22
23 #include <asm/irq.h>
24
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/initval.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/pxa2xx-lib.h>
31 #include <sound/dmaengine_pcm.h>
32
33 #include "pxa-ssp.h"
34
35 /*
36 * SSP audio private data
37 */
38 struct ssp_priv {
39 struct ssp_device *ssp;
40 struct clk *extclk;
41 unsigned long ssp_clk;
42 unsigned int sysclk;
43 unsigned int dai_fmt;
44 unsigned int configured_dai_fmt;
45 #ifdef CONFIG_PM
46 uint32_t cr0;
47 uint32_t cr1;
48 uint32_t to;
49 uint32_t psp;
50 #endif
51 };
52
53 static void dump_registers(struct ssp_device *ssp)
54 {
55 dev_dbg(ssp->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
56 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
57 pxa_ssp_read_reg(ssp, SSTO));
58
59 dev_dbg(ssp->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
60 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
61 pxa_ssp_read_reg(ssp, SSACD));
62 }
63
64 static void pxa_ssp_enable(struct ssp_device *ssp)
65 {
66 uint32_t sscr0;
67
68 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
69 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
70 }
71
72 static void pxa_ssp_disable(struct ssp_device *ssp)
73 {
74 uint32_t sscr0;
75
76 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
77 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
78 }
79
80 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
81 int out, struct snd_dmaengine_dai_dma_data *dma)
82 {
83 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
84 DMA_SLAVE_BUSWIDTH_2_BYTES;
85 dma->maxburst = 16;
86 dma->addr = ssp->phys_base + SSDR;
87 }
88
89 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
90 struct snd_soc_dai *cpu_dai)
91 {
92 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
93 struct ssp_device *ssp = priv->ssp;
94 struct snd_dmaengine_dai_dma_data *dma;
95 int ret = 0;
96
97 if (!cpu_dai->active) {
98 clk_prepare_enable(ssp->clk);
99 pxa_ssp_disable(ssp);
100 }
101
102 if (priv->extclk)
103 clk_prepare_enable(priv->extclk);
104
105 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
106 if (!dma)
107 return -ENOMEM;
108 dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
109 "tx" : "rx";
110
111 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
112
113 return ret;
114 }
115
116 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
117 struct snd_soc_dai *cpu_dai)
118 {
119 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
120 struct ssp_device *ssp = priv->ssp;
121
122 if (!cpu_dai->active) {
123 pxa_ssp_disable(ssp);
124 clk_disable_unprepare(ssp->clk);
125 }
126
127 if (priv->extclk)
128 clk_disable_unprepare(priv->extclk);
129
130 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
131 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
132 }
133
134 #ifdef CONFIG_PM
135
136 static int pxa_ssp_suspend(struct snd_soc_component *component)
137 {
138 struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
139 struct ssp_device *ssp = priv->ssp;
140
141 if (!component->active)
142 clk_prepare_enable(ssp->clk);
143
144 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
145 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
146 priv->to = __raw_readl(ssp->mmio_base + SSTO);
147 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
148
149 pxa_ssp_disable(ssp);
150 clk_disable_unprepare(ssp->clk);
151 return 0;
152 }
153
154 static int pxa_ssp_resume(struct snd_soc_component *component)
155 {
156 struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
157 struct ssp_device *ssp = priv->ssp;
158 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
159
160 clk_prepare_enable(ssp->clk);
161
162 __raw_writel(sssr, ssp->mmio_base + SSSR);
163 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
164 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
165 __raw_writel(priv->to, ssp->mmio_base + SSTO);
166 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
167
168 if (component->active)
169 pxa_ssp_enable(ssp);
170 else
171 clk_disable_unprepare(ssp->clk);
172
173 return 0;
174 }
175
176 #else
177 #define pxa_ssp_suspend NULL
178 #define pxa_ssp_resume NULL
179 #endif
180
181 /**
182 * ssp_set_clkdiv - set SSP clock divider
183 * @div: serial clock rate divider
184 */
185 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
186 {
187 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
188
189 if (ssp->type == PXA25x_SSP) {
190 sscr0 &= ~0x0000ff00;
191 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
192 } else {
193 sscr0 &= ~0x000fff00;
194 sscr0 |= (div - 1) << 8; /* 1..4096 */
195 }
196 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
197 }
198
199 /*
200 * Set the SSP ports SYSCLK.
201 */
202 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
203 int clk_id, unsigned int freq, int dir)
204 {
205 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
206 struct ssp_device *ssp = priv->ssp;
207
208 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
209 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
210
211 if (priv->extclk) {
212 int ret;
213
214 /*
215 * For DT based boards, if an extclk is given, use it
216 * here and configure PXA_SSP_CLK_EXT.
217 */
218
219 ret = clk_set_rate(priv->extclk, freq);
220 if (ret < 0)
221 return ret;
222
223 clk_id = PXA_SSP_CLK_EXT;
224 }
225
226 dev_dbg(ssp->dev,
227 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
228 cpu_dai->id, clk_id, freq);
229
230 switch (clk_id) {
231 case PXA_SSP_CLK_NET_PLL:
232 sscr0 |= SSCR0_MOD;
233 break;
234 case PXA_SSP_CLK_PLL:
235 /* Internal PLL is fixed */
236 if (ssp->type == PXA25x_SSP)
237 priv->sysclk = 1843200;
238 else
239 priv->sysclk = 13000000;
240 break;
241 case PXA_SSP_CLK_EXT:
242 priv->sysclk = freq;
243 sscr0 |= SSCR0_ECS;
244 break;
245 case PXA_SSP_CLK_NET:
246 priv->sysclk = freq;
247 sscr0 |= SSCR0_NCS | SSCR0_MOD;
248 break;
249 case PXA_SSP_CLK_AUDIO:
250 priv->sysclk = 0;
251 pxa_ssp_set_scr(ssp, 1);
252 sscr0 |= SSCR0_ACS;
253 break;
254 default:
255 return -ENODEV;
256 }
257
258 /* The SSP clock must be disabled when changing SSP clock mode
259 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
260 if (ssp->type != PXA3xx_SSP)
261 clk_disable_unprepare(ssp->clk);
262 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
263 if (ssp->type != PXA3xx_SSP)
264 clk_prepare_enable(ssp->clk);
265
266 return 0;
267 }
268
269 /*
270 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
271 */
272 static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq)
273 {
274 struct ssp_device *ssp = priv->ssp;
275 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
276
277 if (ssp->type == PXA3xx_SSP)
278 pxa_ssp_write_reg(ssp, SSACDD, 0);
279
280 switch (freq) {
281 case 5622000:
282 break;
283 case 11345000:
284 ssacd |= (0x1 << 4);
285 break;
286 case 12235000:
287 ssacd |= (0x2 << 4);
288 break;
289 case 14857000:
290 ssacd |= (0x3 << 4);
291 break;
292 case 32842000:
293 ssacd |= (0x4 << 4);
294 break;
295 case 48000000:
296 ssacd |= (0x5 << 4);
297 break;
298 case 0:
299 /* Disable */
300 break;
301
302 default:
303 /* PXA3xx has a clock ditherer which can be used to generate
304 * a wider range of frequencies - calculate a value for it.
305 */
306 if (ssp->type == PXA3xx_SSP) {
307 u32 val;
308 u64 tmp = 19968;
309
310 tmp *= 1000000;
311 do_div(tmp, freq);
312 val = tmp;
313
314 val = (val << 16) | 64;
315 pxa_ssp_write_reg(ssp, SSACDD, val);
316
317 ssacd |= (0x6 << 4);
318
319 dev_dbg(ssp->dev,
320 "Using SSACDD %x to supply %uHz\n",
321 val, freq);
322 break;
323 }
324
325 return -EINVAL;
326 }
327
328 pxa_ssp_write_reg(ssp, SSACD, ssacd);
329
330 return 0;
331 }
332
333 /*
334 * Set the active slots in TDM/Network mode
335 */
336 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
337 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
338 {
339 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
340 struct ssp_device *ssp = priv->ssp;
341 u32 sscr0;
342
343 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
344 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
345
346 /* set slot width */
347 if (slot_width > 16)
348 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
349 else
350 sscr0 |= SSCR0_DataSize(slot_width);
351
352 if (slots > 1) {
353 /* enable network mode */
354 sscr0 |= SSCR0_MOD;
355
356 /* set number of active slots */
357 sscr0 |= SSCR0_SlotsPerFrm(slots);
358
359 /* set active slot mask */
360 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
361 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
362 }
363 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
364
365 return 0;
366 }
367
368 /*
369 * Tristate the SSP DAI lines
370 */
371 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
372 int tristate)
373 {
374 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
375 struct ssp_device *ssp = priv->ssp;
376 u32 sscr1;
377
378 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
379 if (tristate)
380 sscr1 &= ~SSCR1_TTE;
381 else
382 sscr1 |= SSCR1_TTE;
383 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
384
385 return 0;
386 }
387
388 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
389 unsigned int fmt)
390 {
391 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
392
393 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
394 case SND_SOC_DAIFMT_CBM_CFM:
395 case SND_SOC_DAIFMT_CBM_CFS:
396 case SND_SOC_DAIFMT_CBS_CFS:
397 break;
398 default:
399 return -EINVAL;
400 }
401
402 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
403 case SND_SOC_DAIFMT_NB_NF:
404 case SND_SOC_DAIFMT_NB_IF:
405 case SND_SOC_DAIFMT_IB_IF:
406 case SND_SOC_DAIFMT_IB_NF:
407 break;
408 default:
409 return -EINVAL;
410 }
411
412 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
413 case SND_SOC_DAIFMT_I2S:
414 case SND_SOC_DAIFMT_DSP_A:
415 case SND_SOC_DAIFMT_DSP_B:
416 break;
417
418 default:
419 return -EINVAL;
420 }
421
422 /* Settings will be applied in hw_params() */
423 priv->dai_fmt = fmt;
424
425 return 0;
426 }
427
428 /*
429 * Set up the SSP DAI format.
430 * The SSP Port must be inactive before calling this function as the
431 * physical interface format is changed.
432 */
433 static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
434 {
435 struct ssp_device *ssp = priv->ssp;
436 u32 sscr0, sscr1, sspsp, scfr;
437
438 /* check if we need to change anything at all */
439 if (priv->configured_dai_fmt == priv->dai_fmt)
440 return 0;
441
442 /* reset port settings */
443 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
444 ~(SSCR0_PSP | SSCR0_MOD);
445 sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
446 ~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
447 SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
448 sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
449 ~(SSPSP_SFRMP | SSPSP_SCMODE(3));
450
451 sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
452
453 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
454 case SND_SOC_DAIFMT_CBM_CFM:
455 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
456 break;
457 case SND_SOC_DAIFMT_CBM_CFS:
458 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
459 break;
460 case SND_SOC_DAIFMT_CBS_CFS:
461 break;
462 default:
463 return -EINVAL;
464 }
465
466 switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
467 case SND_SOC_DAIFMT_NB_NF:
468 sspsp |= SSPSP_SFRMP;
469 break;
470 case SND_SOC_DAIFMT_NB_IF:
471 break;
472 case SND_SOC_DAIFMT_IB_IF:
473 sspsp |= SSPSP_SCMODE(2);
474 break;
475 case SND_SOC_DAIFMT_IB_NF:
476 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
477 break;
478 default:
479 return -EINVAL;
480 }
481
482 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
483 case SND_SOC_DAIFMT_I2S:
484 sscr0 |= SSCR0_PSP;
485 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
486 /* See hw_params() */
487 break;
488
489 case SND_SOC_DAIFMT_DSP_A:
490 sspsp |= SSPSP_FSRT;
491 /* fall through */
492 case SND_SOC_DAIFMT_DSP_B:
493 sscr0 |= SSCR0_MOD | SSCR0_PSP;
494 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
495 break;
496
497 default:
498 return -EINVAL;
499 }
500
501 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
502 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
503 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
504
505 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
506 case SND_SOC_DAIFMT_CBM_CFM:
507 case SND_SOC_DAIFMT_CBM_CFS:
508 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
509 pxa_ssp_write_reg(ssp, SSCR1, scfr);
510
511 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
512 cpu_relax();
513 break;
514 }
515
516 dump_registers(ssp);
517
518 /* Since we are configuring the timings for the format by hand
519 * we have to defer some things until hw_params() where we
520 * know parameters like the sample size.
521 */
522 priv->configured_dai_fmt = priv->dai_fmt;
523
524 return 0;
525 }
526
527 struct pxa_ssp_clock_mode {
528 int rate;
529 int pll;
530 u8 acds;
531 u8 scdb;
532 };
533
534 static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = {
535 { .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
536 { .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X },
537 { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
538 { .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
539 { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
540 { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
541 { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
542 {}
543 };
544
545 /*
546 * Set the SSP audio DMA parameters and sample size.
547 * Can be called multiple times by oss emulation.
548 */
549 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
550 struct snd_pcm_hw_params *params,
551 struct snd_soc_dai *cpu_dai)
552 {
553 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
554 struct ssp_device *ssp = priv->ssp;
555 int chn = params_channels(params);
556 u32 sscr0, sspsp;
557 int width = snd_pcm_format_physical_width(params_format(params));
558 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
559 struct snd_dmaengine_dai_dma_data *dma_data;
560 int rate = params_rate(params);
561 int bclk = rate * chn * (width / 8);
562 int ret;
563
564 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
565
566 /* Network mode with one active slot (ttsa == 1) can be used
567 * to force 16-bit frame width on the wire (for S16_LE), even
568 * with two channels. Use 16-bit DMA transfers for this case.
569 */
570 pxa_ssp_set_dma_params(ssp,
571 ((chn == 2) && (ttsa != 1)) || (width == 32),
572 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
573
574 /* we can only change the settings if the port is not in use */
575 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
576 return 0;
577
578 ret = pxa_ssp_configure_dai_fmt(priv);
579 if (ret < 0)
580 return ret;
581
582 /* clear selected SSP bits */
583 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
584
585 /* bit size */
586 switch (params_format(params)) {
587 case SNDRV_PCM_FORMAT_S16_LE:
588 if (ssp->type == PXA3xx_SSP)
589 sscr0 |= SSCR0_FPCKE;
590 sscr0 |= SSCR0_DataSize(16);
591 break;
592 case SNDRV_PCM_FORMAT_S24_LE:
593 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
594 break;
595 case SNDRV_PCM_FORMAT_S32_LE:
596 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
597 break;
598 }
599 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
600
601 if (sscr0 & SSCR0_ACS) {
602 ret = pxa_ssp_set_pll(priv, bclk);
603
604 /*
605 * If we were able to generate the bclk directly,
606 * all is fine. Otherwise, look up the closest rate
607 * from the table and also set the dividers.
608 */
609
610 if (ret < 0) {
611 const struct pxa_ssp_clock_mode *m;
612 int ssacd, acds;
613
614 for (m = pxa_ssp_clock_modes; m->rate; m++) {
615 if (m->rate == rate)
616 break;
617 }
618
619 if (!m->rate)
620 return -EINVAL;
621
622 acds = m->acds;
623
624 /* The values in the table are for 16 bits */
625 if (width == 32)
626 acds--;
627
628 ret = pxa_ssp_set_pll(priv, bclk);
629 if (ret < 0)
630 return ret;
631
632 ssacd = pxa_ssp_read_reg(ssp, SSACD);
633 ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X);
634 ssacd |= SSACD_ACDS(m->acds);
635 ssacd |= m->scdb;
636 pxa_ssp_write_reg(ssp, SSACD, ssacd);
637 }
638 } else if (sscr0 & SSCR0_ECS) {
639 /*
640 * For setups with external clocking, the PLL and its diviers
641 * are not active. Instead, the SCR bits in SSCR0 can be used
642 * to divide the clock.
643 */
644 pxa_ssp_set_scr(ssp, bclk / rate);
645 }
646
647 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
648 case SND_SOC_DAIFMT_I2S:
649 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
650
651 if (((priv->sysclk / bclk) == 64) && (width == 16)) {
652 /* This is a special case where the bitclk is 64fs
653 * and we're not dealing with 2*32 bits of audio
654 * samples.
655 *
656 * The SSP values used for that are all found out by
657 * trying and failing a lot; some of the registers
658 * needed for that mode are only available on PXA3xx.
659 */
660 if (ssp->type != PXA3xx_SSP)
661 return -EINVAL;
662
663 sspsp |= SSPSP_SFRMWDTH(width * 2);
664 sspsp |= SSPSP_SFRMDLY(width * 4);
665 sspsp |= SSPSP_EDMYSTOP(3);
666 sspsp |= SSPSP_DMYSTOP(3);
667 sspsp |= SSPSP_DMYSTRT(1);
668 } else {
669 /* The frame width is the width the LRCLK is
670 * asserted for; the delay is expressed in
671 * half cycle units. We need the extra cycle
672 * because the data starts clocking out one BCLK
673 * after LRCLK changes polarity.
674 */
675 sspsp |= SSPSP_SFRMWDTH(width + 1);
676 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
677 sspsp |= SSPSP_DMYSTRT(1);
678 }
679
680 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
681 break;
682 default:
683 break;
684 }
685
686 /* When we use a network mode, we always require TDM slots
687 * - complain loudly and fail if they've not been set up yet.
688 */
689 if ((sscr0 & SSCR0_MOD) && !ttsa) {
690 dev_err(ssp->dev, "No TDM timeslot configured\n");
691 return -EINVAL;
692 }
693
694 dump_registers(ssp);
695
696 return 0;
697 }
698
699 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
700 struct ssp_device *ssp, int value)
701 {
702 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
703 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
704 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
705 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
706
707 if (value && (sscr0 & SSCR0_SSE))
708 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
709
710 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
711 if (value)
712 sscr1 |= SSCR1_TSRE;
713 else
714 sscr1 &= ~SSCR1_TSRE;
715 } else {
716 if (value)
717 sscr1 |= SSCR1_RSRE;
718 else
719 sscr1 &= ~SSCR1_RSRE;
720 }
721
722 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
723
724 if (value) {
725 pxa_ssp_write_reg(ssp, SSSR, sssr);
726 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
727 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
728 }
729 }
730
731 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
732 struct snd_soc_dai *cpu_dai)
733 {
734 int ret = 0;
735 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
736 struct ssp_device *ssp = priv->ssp;
737 int val;
738
739 switch (cmd) {
740 case SNDRV_PCM_TRIGGER_RESUME:
741 pxa_ssp_enable(ssp);
742 break;
743 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
744 pxa_ssp_set_running_bit(substream, ssp, 1);
745 val = pxa_ssp_read_reg(ssp, SSSR);
746 pxa_ssp_write_reg(ssp, SSSR, val);
747 break;
748 case SNDRV_PCM_TRIGGER_START:
749 pxa_ssp_set_running_bit(substream, ssp, 1);
750 break;
751 case SNDRV_PCM_TRIGGER_STOP:
752 pxa_ssp_set_running_bit(substream, ssp, 0);
753 break;
754 case SNDRV_PCM_TRIGGER_SUSPEND:
755 pxa_ssp_disable(ssp);
756 break;
757 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
758 pxa_ssp_set_running_bit(substream, ssp, 0);
759 break;
760
761 default:
762 ret = -EINVAL;
763 }
764
765 dump_registers(ssp);
766
767 return ret;
768 }
769
770 static int pxa_ssp_probe(struct snd_soc_dai *dai)
771 {
772 struct device *dev = dai->dev;
773 struct ssp_priv *priv;
774 int ret;
775
776 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
777 if (!priv)
778 return -ENOMEM;
779
780 if (dev->of_node) {
781 struct device_node *ssp_handle;
782
783 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
784 if (!ssp_handle) {
785 dev_err(dev, "unable to get 'port' phandle\n");
786 ret = -ENODEV;
787 goto err_priv;
788 }
789
790 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
791 if (priv->ssp == NULL) {
792 ret = -ENODEV;
793 goto err_priv;
794 }
795
796 priv->extclk = devm_clk_get(dev, "extclk");
797 if (IS_ERR(priv->extclk)) {
798 ret = PTR_ERR(priv->extclk);
799 if (ret == -EPROBE_DEFER)
800 return ret;
801
802 priv->extclk = NULL;
803 }
804 } else {
805 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
806 if (priv->ssp == NULL) {
807 ret = -ENODEV;
808 goto err_priv;
809 }
810 }
811
812 priv->dai_fmt = (unsigned int) -1;
813 snd_soc_dai_set_drvdata(dai, priv);
814
815 return 0;
816
817 err_priv:
818 kfree(priv);
819 return ret;
820 }
821
822 static int pxa_ssp_remove(struct snd_soc_dai *dai)
823 {
824 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
825
826 pxa_ssp_free(priv->ssp);
827 kfree(priv);
828 return 0;
829 }
830
831 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
832 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
833 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
834 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
835 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
836
837 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
838
839 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
840 .startup = pxa_ssp_startup,
841 .shutdown = pxa_ssp_shutdown,
842 .trigger = pxa_ssp_trigger,
843 .hw_params = pxa_ssp_hw_params,
844 .set_sysclk = pxa_ssp_set_dai_sysclk,
845 .set_fmt = pxa_ssp_set_dai_fmt,
846 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
847 .set_tristate = pxa_ssp_set_dai_tristate,
848 };
849
850 static struct snd_soc_dai_driver pxa_ssp_dai = {
851 .probe = pxa_ssp_probe,
852 .remove = pxa_ssp_remove,
853 .playback = {
854 .channels_min = 1,
855 .channels_max = 8,
856 .rates = PXA_SSP_RATES,
857 .formats = PXA_SSP_FORMATS,
858 },
859 .capture = {
860 .channels_min = 1,
861 .channels_max = 8,
862 .rates = PXA_SSP_RATES,
863 .formats = PXA_SSP_FORMATS,
864 },
865 .ops = &pxa_ssp_dai_ops,
866 };
867
868 static const struct snd_soc_component_driver pxa_ssp_component = {
869 .name = "pxa-ssp",
870 .pcm_construct = pxa2xx_soc_pcm_new,
871 .pcm_destruct = pxa2xx_soc_pcm_free,
872 .open = pxa2xx_soc_pcm_open,
873 .close = pxa2xx_soc_pcm_close,
874 .hw_params = pxa2xx_soc_pcm_hw_params,
875 .hw_free = pxa2xx_soc_pcm_hw_free,
876 .prepare = pxa2xx_soc_pcm_prepare,
877 .trigger = pxa2xx_soc_pcm_trigger,
878 .pointer = pxa2xx_soc_pcm_pointer,
879 .mmap = pxa2xx_soc_pcm_mmap,
880 .suspend = pxa_ssp_suspend,
881 .resume = pxa_ssp_resume,
882 };
883
884 #ifdef CONFIG_OF
885 static const struct of_device_id pxa_ssp_of_ids[] = {
886 { .compatible = "mrvl,pxa-ssp-dai" },
887 {}
888 };
889 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
890 #endif
891
892 static int asoc_ssp_probe(struct platform_device *pdev)
893 {
894 return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
895 &pxa_ssp_dai, 1);
896 }
897
898 static struct platform_driver asoc_ssp_driver = {
899 .driver = {
900 .name = "pxa-ssp-dai",
901 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
902 },
903
904 .probe = asoc_ssp_probe,
905 };
906
907 module_platform_driver(asoc_ssp_driver);
908
909 /* Module information */
910 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
911 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
912 MODULE_LICENSE("GPL");
913 MODULE_ALIAS("platform:pxa-ssp-dai");
Linux with added FPC-III support