sound/soc/sirf/sirf-usp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * SiRF USP in I2S/DSP mode
   4  *
   5  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   6  */
   7 #include <linux/module.h>
   8 #include <linux/io.h>
   9 #include <linux/of.h>
  10 #include <linux/clk.h>
  11 #include <linux/pm_runtime.h>
  12 #include <sound/soc.h>
  13 #include <sound/pcm_params.h>
  14 #include <sound/dmaengine_pcm.h>
  15
  16 #include "sirf-usp.h"
  17
  18 struct sirf_usp {
  19         struct regmap *regmap;
  20         struct clk *clk;
  21         u32 mode1_reg;
  22         u32 mode2_reg;
  23         int daifmt_format;
  24         struct snd_dmaengine_dai_dma_data playback_dma_data;
  25         struct snd_dmaengine_dai_dma_data capture_dma_data;
  26 };
  27
  28 static void sirf_usp_tx_enable(struct sirf_usp *usp)
  29 {
  30         regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
  31                 USP_TX_FIFO_RESET, USP_TX_FIFO_RESET);
  32         regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
  33
  34         regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
  35                 USP_TX_FIFO_START, USP_TX_FIFO_START);
  36
  37         regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
  38                 USP_TX_ENA, USP_TX_ENA);
  39 }
  40
  41 static void sirf_usp_tx_disable(struct sirf_usp *usp)
  42 {
  43         regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
  44                 USP_TX_ENA, ~USP_TX_ENA);
  45         /* FIFO stop */
  46         regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
  47 }
  48
  49 static void sirf_usp_rx_enable(struct sirf_usp *usp)
  50 {
  51         regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
  52                 USP_RX_FIFO_RESET, USP_RX_FIFO_RESET);
  53         regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
  54
  55         regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
  56                 USP_RX_FIFO_START, USP_RX_FIFO_START);
  57
  58         regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
  59                 USP_RX_ENA, USP_RX_ENA);
  60 }
  61
  62 static void sirf_usp_rx_disable(struct sirf_usp *usp)
  63 {
  64         regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
  65                 USP_RX_ENA, ~USP_RX_ENA);
  66         /* FIFO stop */
  67         regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
  68 }
  69
  70 static int sirf_usp_pcm_dai_probe(struct snd_soc_dai *dai)
  71 {
  72         struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
  73
  74         snd_soc_dai_init_dma_data(dai, &usp->playback_dma_data,
  75                         &usp->capture_dma_data);
  76         return 0;
  77 }
  78
  79 static int sirf_usp_pcm_set_dai_fmt(struct snd_soc_dai *dai,
  80                 unsigned int fmt)
  81 {
  82         struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
  83
  84         /* set master/slave audio interface */
  85         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  86         case SND_SOC_DAIFMT_CBM_CFM:
  87                 break;
  88         default:
  89                 dev_err(dai->dev, "Only CBM and CFM supported\n");
  90                 return -EINVAL;
  91         }
  92
  93         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  94         case SND_SOC_DAIFMT_I2S:
  95         case SND_SOC_DAIFMT_DSP_A:
  96                 usp->daifmt_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  97                 break;
  98         default:
  99                 dev_err(dai->dev, "Only I2S and DSP_A format supported\n");
 100                 return -EINVAL;
 101         }
 102
 103         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 104         case SND_SOC_DAIFMT_NB_NF:
 105                 break;
 106         case SND_SOC_DAIFMT_IB_NF:
 107                 usp->daifmt_format |= (fmt & SND_SOC_DAIFMT_INV_MASK);
 108                 break;
 109         default:
 110                 return -EINVAL;
 111         }
 112
 113         return 0;
 114 }
 115
 116 static void sirf_usp_i2s_init(struct sirf_usp *usp)
 117 {
 118         /* Configure RISC mode */
 119         regmap_update_bits(usp->regmap, USP_RISC_DSP_MODE,
 120                 USP_RISC_DSP_SEL, ~USP_RISC_DSP_SEL);
 121
 122         /*
 123          * Configure DMA IO Length register
 124          * Set no limit, USP can receive data continuously until it is diabled
 125          */
 126         regmap_write(usp->regmap, USP_TX_DMA_IO_LEN, 0);
 127         regmap_write(usp->regmap, USP_RX_DMA_IO_LEN, 0);
 128
 129         /* Configure Mode2 register */
 130         regmap_write(usp->regmap, USP_MODE2, (1 << USP_RXD_DELAY_LEN_OFFSET) |
 131                 (0 << USP_TXD_DELAY_LEN_OFFSET) |
 132                 USP_TFS_CLK_SLAVE_MODE | USP_RFS_CLK_SLAVE_MODE);
 133
 134         /* Configure Mode1 register */
 135         regmap_write(usp->regmap, USP_MODE1,
 136                 USP_SYNC_MODE | USP_EN | USP_TXD_ACT_EDGE_FALLING |
 137                 USP_RFS_ACT_LEVEL_LOGIC1 | USP_TFS_ACT_LEVEL_LOGIC1 |
 138                 USP_TX_UFLOW_REPEAT_ZERO | USP_CLOCK_MODE_SLAVE);
 139
 140         /* Configure RX DMA IO Control register */
 141         regmap_write(usp->regmap, USP_RX_DMA_IO_CTRL, 0);
 142
 143         /* Congiure RX FIFO Control register */
 144         regmap_write(usp->regmap, USP_RX_FIFO_CTRL,
 145                 (USP_RX_FIFO_THRESHOLD << USP_RX_FIFO_THD_OFFSET) |
 146                 (USP_TX_RX_FIFO_WIDTH_DWORD << USP_RX_FIFO_WIDTH_OFFSET));
 147
 148         /* Congiure RX FIFO Level Check register */
 149         regmap_write(usp->regmap, USP_RX_FIFO_LEVEL_CHK,
 150                 RX_FIFO_SC(0x04) | RX_FIFO_LC(0x0E) | RX_FIFO_HC(0x1B));
 151
 152         /* Configure TX DMA IO Control register*/
 153         regmap_write(usp->regmap, USP_TX_DMA_IO_CTRL, 0);
 154
 155         /* Configure TX FIFO Control register */
 156         regmap_write(usp->regmap, USP_TX_FIFO_CTRL,
 157                 (USP_TX_FIFO_THRESHOLD << USP_TX_FIFO_THD_OFFSET) |
 158                 (USP_TX_RX_FIFO_WIDTH_DWORD << USP_TX_FIFO_WIDTH_OFFSET));
 159         /* Congiure TX FIFO Level Check register */
 160         regmap_write(usp->regmap, USP_TX_FIFO_LEVEL_CHK,
 161                 TX_FIFO_SC(0x1B) | TX_FIFO_LC(0x0E) | TX_FIFO_HC(0x04));
 162 }
 163
 164 static int sirf_usp_pcm_hw_params(struct snd_pcm_substream *substream,
 165                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 166 {
 167         struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
 168         u32 data_len, frame_len, shifter_len;
 169
 170         switch (params_format(params)) {
 171         case SNDRV_PCM_FORMAT_S16_LE:
 172                 data_len = 16;
 173                 frame_len = 16;
 174                 break;
 175         case SNDRV_PCM_FORMAT_S24_LE:
 176                 data_len = 24;
 177                 frame_len = 32;
 178                 break;
 179         case SNDRV_PCM_FORMAT_S24_3LE:
 180                 data_len = 24;
 181                 frame_len = 24;
 182                 break;
 183         default:
 184                 dev_err(dai->dev, "Format unsupported\n");
 185                 return -EINVAL;
 186         }
 187
 188         shifter_len = data_len;
 189
 190         switch (usp->daifmt_format & SND_SOC_DAIFMT_FORMAT_MASK) {
 191         case SND_SOC_DAIFMT_I2S:
 192                 regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
 193                         USP_I2S_SYNC_CHG, USP_I2S_SYNC_CHG);
 194                 break;
 195         case SND_SOC_DAIFMT_DSP_A:
 196                 regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
 197                         USP_I2S_SYNC_CHG, 0);
 198                 frame_len = data_len * params_channels(params);
 199                 data_len = frame_len;
 200                 break;
 201         default:
 202                 dev_err(dai->dev, "Only support I2S and DSP_A mode\n");
 203                 return -EINVAL;
 204         }
 205
 206         switch (usp->daifmt_format & SND_SOC_DAIFMT_INV_MASK) {
 207         case SND_SOC_DAIFMT_NB_NF:
 208                 break;
 209         case SND_SOC_DAIFMT_IB_NF:
 210                 regmap_update_bits(usp->regmap, USP_MODE1,
 211                         USP_RXD_ACT_EDGE_FALLING | USP_TXD_ACT_EDGE_FALLING,
 212                         USP_RXD_ACT_EDGE_FALLING);
 213                 break;
 214         default:
 215                 return -EINVAL;
 216         }
 217
 218         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 219                 regmap_update_bits(usp->regmap, USP_TX_FRAME_CTRL,
 220                         USP_TXC_DATA_LEN_MASK | USP_TXC_FRAME_LEN_MASK
 221                         | USP_TXC_SHIFTER_LEN_MASK | USP_TXC_SLAVE_CLK_SAMPLE,
 222                         ((data_len - 1) << USP_TXC_DATA_LEN_OFFSET)
 223                         | ((frame_len - 1) << USP_TXC_FRAME_LEN_OFFSET)
 224                         | ((shifter_len - 1) << USP_TXC_SHIFTER_LEN_OFFSET)
 225                         | USP_TXC_SLAVE_CLK_SAMPLE);
 226         else
 227                 regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
 228                         USP_RXC_DATA_LEN_MASK | USP_RXC_FRAME_LEN_MASK
 229                         | USP_RXC_SHIFTER_LEN_MASK | USP_SINGLE_SYNC_MODE,
 230                         ((data_len - 1) << USP_RXC_DATA_LEN_OFFSET)
 231                         | ((frame_len - 1) << USP_RXC_FRAME_LEN_OFFSET)
 232                         | ((shifter_len - 1) << USP_RXC_SHIFTER_LEN_OFFSET)
 233                         | USP_SINGLE_SYNC_MODE);
 234
 235         return 0;
 236 }
 237
 238 static int sirf_usp_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 239                                 struct snd_soc_dai *dai)
 240 {
 241         struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
 242
 243         switch (cmd) {
 244         case SNDRV_PCM_TRIGGER_START:
 245         case SNDRV_PCM_TRIGGER_RESUME:
 246         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 247                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 248                         sirf_usp_tx_enable(usp);
 249                 else
 250                         sirf_usp_rx_enable(usp);
 251                 break;
 252         case SNDRV_PCM_TRIGGER_STOP:
 253         case SNDRV_PCM_TRIGGER_SUSPEND:
 254         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 255                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 256                         sirf_usp_tx_disable(usp);
 257                 else
 258                         sirf_usp_rx_disable(usp);
 259                 break;
 260         }
 261
 262         return 0;
 263 }
 264
 265 static const struct snd_soc_dai_ops sirf_usp_pcm_dai_ops = {
 266         .trigger = sirf_usp_pcm_trigger,
 267         .set_fmt = sirf_usp_pcm_set_dai_fmt,
 268         .hw_params = sirf_usp_pcm_hw_params,
 269 };
 270
 271 static struct snd_soc_dai_driver sirf_usp_pcm_dai = {
 272         .probe = sirf_usp_pcm_dai_probe,
 273         .name = "sirf-usp-pcm",
 274         .id = 0,
 275         .playback = {
 276                 .stream_name = "SiRF USP PCM Playback",
 277                 .channels_min = 1,
 278                 .channels_max = 2,
 279                 .rates = SNDRV_PCM_RATE_8000_192000,
 280                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 281                         SNDRV_PCM_FMTBIT_S24_3LE,
 282         },
 283         .capture = {
 284                 .stream_name = "SiRF USP PCM Capture",
 285                 .channels_min = 1,
 286                 .channels_max = 2,
 287                 .rates = SNDRV_PCM_RATE_8000_192000,
 288                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 289                         SNDRV_PCM_FMTBIT_S24_3LE,
 290         },
 291         .ops = &sirf_usp_pcm_dai_ops,
 292 };
 293
 294 static int sirf_usp_pcm_runtime_suspend(struct device *dev)
 295 {
 296         struct sirf_usp *usp = dev_get_drvdata(dev);
 297
 298         clk_disable_unprepare(usp->clk);
 299         return 0;
 300 }
 301
 302 static int sirf_usp_pcm_runtime_resume(struct device *dev)
 303 {
 304         struct sirf_usp *usp = dev_get_drvdata(dev);
 305         int ret;
 306
 307         ret = clk_prepare_enable(usp->clk);
 308         if (ret) {
 309                 dev_err(dev, "clk_enable failed: %d\n", ret);
 310                 return ret;
 311         }
 312         sirf_usp_i2s_init(usp);
 313         return 0;
 314 }
 315
 316 #ifdef CONFIG_PM_SLEEP
 317 static int sirf_usp_pcm_suspend(struct device *dev)
 318 {
 319         struct sirf_usp *usp = dev_get_drvdata(dev);
 320
 321         if (!pm_runtime_status_suspended(dev)) {
 322                 regmap_read(usp->regmap, USP_MODE1, &usp->mode1_reg);
 323                 regmap_read(usp->regmap, USP_MODE2, &usp->mode2_reg);
 324                 sirf_usp_pcm_runtime_suspend(dev);
 325         }
 326         return 0;
 327 }
 328
 329 static int sirf_usp_pcm_resume(struct device *dev)
 330 {
 331         struct sirf_usp *usp = dev_get_drvdata(dev);
 332         int ret;
 333
 334         if (!pm_runtime_status_suspended(dev)) {
 335                 ret = sirf_usp_pcm_runtime_resume(dev);
 336                 if (ret)
 337                         return ret;
 338                 regmap_write(usp->regmap, USP_MODE1, usp->mode1_reg);
 339                 regmap_write(usp->regmap, USP_MODE2, usp->mode2_reg);
 340         }
 341         return 0;
 342 }
 343 #endif
 344
 345 static const struct snd_soc_component_driver sirf_usp_component = {
 346         .name           = "sirf-usp",
 347 };
 348
 349 static const struct regmap_config sirf_usp_regmap_config = {
 350         .reg_bits = 32,
 351         .reg_stride = 4,
 352         .val_bits = 32,
 353         .max_register = USP_RX_FIFO_DATA,
 354         .cache_type = REGCACHE_NONE,
 355 };
 356
 357 static int sirf_usp_pcm_probe(struct platform_device *pdev)
 358 {
 359         int ret;
 360         struct sirf_usp *usp;
 361         void __iomem *base;
 362
 363         usp = devm_kzalloc(&pdev->dev, sizeof(struct sirf_usp),
 364                         GFP_KERNEL);
 365         if (!usp)
 366                 return -ENOMEM;
 367
 368         platform_set_drvdata(pdev, usp);
 369
 370         base = devm_platform_ioremap_resource(pdev, 0);
 371         if (IS_ERR(base))
 372                 return PTR_ERR(base);
 373         usp->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 374                                             &sirf_usp_regmap_config);
 375         if (IS_ERR(usp->regmap))
 376                 return PTR_ERR(usp->regmap);
 377
 378         usp->clk = devm_clk_get(&pdev->dev, NULL);
 379         if (IS_ERR(usp->clk)) {
 380                 dev_err(&pdev->dev, "Get clock failed.\n");
 381                 return PTR_ERR(usp->clk);
 382         }
 383
 384         pm_runtime_enable(&pdev->dev);
 385         if (!pm_runtime_enabled(&pdev->dev)) {
 386                 ret = sirf_usp_pcm_runtime_resume(&pdev->dev);
 387                 if (ret)
 388                         return ret;
 389         }
 390
 391         ret = devm_snd_soc_register_component(&pdev->dev, &sirf_usp_component,
 392                 &sirf_usp_pcm_dai, 1);
 393         if (ret) {
 394                 dev_err(&pdev->dev, "Register Audio SoC dai failed.\n");
 395                 return ret;
 396         }
 397         return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 398 }
 399
 400 static int sirf_usp_pcm_remove(struct platform_device *pdev)
 401 {
 402         if (!pm_runtime_enabled(&pdev->dev))
 403                 sirf_usp_pcm_runtime_suspend(&pdev->dev);
 404         else
 405                 pm_runtime_disable(&pdev->dev);
 406         return 0;
 407 }
 408
 409 static const struct of_device_id sirf_usp_pcm_of_match[] = {
 410         { .compatible = "sirf,prima2-usp-pcm", },
 411         {}
 412 };
 413 MODULE_DEVICE_TABLE(of, sirf_usp_pcm_of_match);
 414
 415 static const struct dev_pm_ops sirf_usp_pcm_pm_ops = {
 416         SET_RUNTIME_PM_OPS(sirf_usp_pcm_runtime_suspend,
 417                 sirf_usp_pcm_runtime_resume, NULL)
 418         SET_SYSTEM_SLEEP_PM_OPS(sirf_usp_pcm_suspend, sirf_usp_pcm_resume)
 419 };
 420
 421 static struct platform_driver sirf_usp_pcm_driver = {
 422         .driver = {
 423                 .name = "sirf-usp-pcm",
 424                 .of_match_table = sirf_usp_pcm_of_match,
 425                 .pm = &sirf_usp_pcm_pm_ops,
 426         },
 427         .probe = sirf_usp_pcm_probe,
 428         .remove = sirf_usp_pcm_remove,
 429 };
 430
 431 module_platform_driver(sirf_usp_pcm_driver);
 432
 433 MODULE_DESCRIPTION("SiRF SoC USP PCM bus driver");
 434 MODULE_AUTHOR("RongJun Ying <Rongjun.Ying@csr.com>");
 435 MODULE_LICENSE("GPL v2");