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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / sound / soc / ti / davinci-mcasp.c
blobe1e937eb1dc1acca46e63a0e42ac2f6e792a17ae
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 *
5 * Multi-channel Audio Serial Port Driver
6 *
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
8 * Suresh Rajashekara <suresh.r@ti.com>
9 * Steve Chen <schen@.mvista.com>
10 *
11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
12 * Copyright: (C) 2009 Texas Instruments, India
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/io.h>
21 #include <linux/clk.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/of.h>
24 #include <linux/of_platform.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_data/davinci_asp.h>
27 #include <linux/math64.h>
28 #include <linux/bitmap.h>
29 #include <linux/gpio/driver.h>
30
31 #include <sound/asoundef.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/initval.h>
36 #include <sound/soc.h>
37 #include <sound/dmaengine_pcm.h>
38
39 #include "edma-pcm.h"
40 #include "sdma-pcm.h"
41 #include "davinci-mcasp.h"
42
43 #define MCASP_MAX_AFIFO_DEPTH 64
44
45 #ifdef CONFIG_PM
46 static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
55 DAVINCI_MCASP_PDIR_REG,
56 DAVINCI_MCASP_PFUNC_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
61 };
62
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
67 bool pm_state;
68 };
69 #endif
70
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
73 int serializers;
74 };
75
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
78 void __iomem *base;
79 u32 fifo_base;
80 struct device *dev;
81 struct snd_pcm_substream *substreams[2];
82 unsigned int dai_fmt;
83
84 /* McASP specific data */
85 int tdm_slots;
86 u32 tdm_mask[2];
87 int slot_width;
88 u8 op_mode;
89 u8 dismod;
90 u8 num_serializer;
91 u8 *serial_dir;
92 u8 version;
93 u8 bclk_div;
94 int streams;
95 u32 irq_request[2];
96 int dma_request[2];
97
98 int sysclk_freq;
99 bool bclk_master;
100 u32 auxclk_fs_ratio;
101
102 unsigned long pdir; /* Pin direction bitfield */
103
104 /* McASP FIFO related */
105 u8 txnumevt;
106 u8 rxnumevt;
107
108 bool dat_port;
109
110 /* Used for comstraint setting on the second stream */
111 u32 channels;
112 int max_format_width;
113 u8 active_serializers[2];
114
115 #ifdef CONFIG_GPIOLIB
116 struct gpio_chip gpio_chip;
117 #endif
118
119 #ifdef CONFIG_PM
120 struct davinci_mcasp_context context;
121 #endif
122
123 struct davinci_mcasp_ruledata ruledata[2];
124 struct snd_pcm_hw_constraint_list chconstr[2];
125 };
126
127 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
128 u32 val)
129 {
130 void __iomem *reg = mcasp->base + offset;
131 __raw_writel(__raw_readl(reg) | val, reg);
132 }
133
134 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
135 u32 val)
136 {
137 void __iomem *reg = mcasp->base + offset;
138 __raw_writel((__raw_readl(reg) & ~(val)), reg);
139 }
140
141 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
142 u32 val, u32 mask)
143 {
144 void __iomem *reg = mcasp->base + offset;
145 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
146 }
147
148 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
149 u32 val)
150 {
151 __raw_writel(val, mcasp->base + offset);
152 }
153
154 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
155 {
156 return (u32)__raw_readl(mcasp->base + offset);
157 }
158
159 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
160 {
161 int i = 0;
162
163 mcasp_set_bits(mcasp, ctl_reg, val);
164
165 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
166 /* loop count is to avoid the lock-up */
167 for (i = 0; i < 1000; i++) {
168 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
169 break;
170 }
171
172 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
173 printk(KERN_ERR "GBLCTL write error\n");
174 }
175
176 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
177 {
178 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
179 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
180
181 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
182 }
183
184 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
185 {
186 u32 bit = PIN_BIT_AMUTE;
187
188 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
189 if (enable)
190 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
191 else
192 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
193 }
194 }
195
196 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
197 {
198 u32 bit;
199
200 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
201 if (enable)
202 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
203 else
204 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
205 }
206 }
207
208 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
209 {
210 if (mcasp->rxnumevt) { /* enable FIFO */
211 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
212
213 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
214 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
215 }
216
217 /* Start clocks */
218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
220 /*
221 * When ASYNC == 0 the transmit and receive sections operate
222 * synchronously from the transmit clock and frame sync. We need to make
223 * sure that the TX signlas are enabled when starting reception.
224 */
225 if (mcasp_is_synchronous(mcasp)) {
226 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
227 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
228 mcasp_set_clk_pdir(mcasp, true);
229 }
230
231 /* Activate serializer(s) */
232 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
234 /* Release RX state machine */
235 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
236 /* Release Frame Sync generator */
237 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
238 if (mcasp_is_synchronous(mcasp))
239 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
240
241 /* enable receive IRQs */
242 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
243 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
244 }
245
246 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
247 {
248 u32 cnt;
249
250 if (mcasp->txnumevt) { /* enable FIFO */
251 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
252
253 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
254 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
255 }
256
257 /* Start clocks */
258 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
259 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
260 mcasp_set_clk_pdir(mcasp, true);
261
262 /* Activate serializer(s) */
263 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
264 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
265
266 /* wait for XDATA to be cleared */
267 cnt = 0;
268 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
269 (cnt < 100000))
270 cnt++;
271
272 mcasp_set_axr_pdir(mcasp, true);
273
274 /* Release TX state machine */
275 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
276 /* Release Frame Sync generator */
277 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
278
279 /* enable transmit IRQs */
280 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
281 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
282 }
283
284 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
285 {
286 mcasp->streams++;
287
288 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
289 mcasp_start_tx(mcasp);
290 else
291 mcasp_start_rx(mcasp);
292 }
293
294 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
295 {
296 /* disable IRQ sources */
297 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
298 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
299
300 /*
301 * In synchronous mode stop the TX clocks if no other stream is
302 * running
303 */
304 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
305 mcasp_set_clk_pdir(mcasp, false);
306 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
307 }
308
309 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
310 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
311
312 if (mcasp->rxnumevt) { /* disable FIFO */
313 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
314
315 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
316 }
317 }
318
319 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
320 {
321 u32 val = 0;
322
323 /* disable IRQ sources */
324 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
325 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
326
327 /*
328 * In synchronous mode keep TX clocks running if the capture stream is
329 * still running.
330 */
331 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
332 val = TXHCLKRST | TXCLKRST | TXFSRST;
333 else
334 mcasp_set_clk_pdir(mcasp, false);
335
336
337 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
338 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
339
340 if (mcasp->txnumevt) { /* disable FIFO */
341 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
342
343 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
344 }
345
346 mcasp_set_axr_pdir(mcasp, false);
347 }
348
349 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
350 {
351 mcasp->streams--;
352
353 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
354 mcasp_stop_tx(mcasp);
355 else
356 mcasp_stop_rx(mcasp);
357 }
358
359 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
360 {
361 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
362 struct snd_pcm_substream *substream;
363 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
364 u32 handled_mask = 0;
365 u32 stat;
366
367 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
368 if (stat & XUNDRN & irq_mask) {
369 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
370 handled_mask |= XUNDRN;
371
372 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
373 if (substream)
374 snd_pcm_stop_xrun(substream);
375 }
376
377 if (!handled_mask)
378 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
379 stat);
380
381 if (stat & XRERR)
382 handled_mask |= XRERR;
383
384 /* Ack the handled event only */
385 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
386
387 return IRQ_RETVAL(handled_mask);
388 }
389
390 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
391 {
392 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
393 struct snd_pcm_substream *substream;
394 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
395 u32 handled_mask = 0;
396 u32 stat;
397
398 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
399 if (stat & ROVRN & irq_mask) {
400 dev_warn(mcasp->dev, "Receive buffer overflow\n");
401 handled_mask |= ROVRN;
402
403 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
404 if (substream)
405 snd_pcm_stop_xrun(substream);
406 }
407
408 if (!handled_mask)
409 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
410 stat);
411
412 if (stat & XRERR)
413 handled_mask |= XRERR;
414
415 /* Ack the handled event only */
416 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
417
418 return IRQ_RETVAL(handled_mask);
419 }
420
421 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
422 {
423 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
424 irqreturn_t ret = IRQ_NONE;
425
426 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
427 ret = davinci_mcasp_tx_irq_handler(irq, data);
428
429 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
430 ret |= davinci_mcasp_rx_irq_handler(irq, data);
431
432 return ret;
433 }
434
435 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
436 unsigned int fmt)
437 {
438 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
439 int ret = 0;
440 u32 data_delay;
441 bool fs_pol_rising;
442 bool inv_fs = false;
443
444 if (!fmt)
445 return 0;
446
447 pm_runtime_get_sync(mcasp->dev);
448 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
449 case SND_SOC_DAIFMT_DSP_A:
450 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
451 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
452 /* 1st data bit occur one ACLK cycle after the frame sync */
453 data_delay = 1;
454 break;
455 case SND_SOC_DAIFMT_DSP_B:
456 case SND_SOC_DAIFMT_AC97:
457 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
459 /* No delay after FS */
460 data_delay = 0;
461 break;
462 case SND_SOC_DAIFMT_I2S:
463 /* configure a full-word SYNC pulse (LRCLK) */
464 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
465 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
466 /* 1st data bit occur one ACLK cycle after the frame sync */
467 data_delay = 1;
468 /* FS need to be inverted */
469 inv_fs = true;
470 break;
471 case SND_SOC_DAIFMT_RIGHT_J:
472 case SND_SOC_DAIFMT_LEFT_J:
473 /* configure a full-word SYNC pulse (LRCLK) */
474 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
476 /* No delay after FS */
477 data_delay = 0;
478 break;
479 default:
480 ret = -EINVAL;
481 goto out;
482 }
483
484 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
485 FSXDLY(3));
486 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
487 FSRDLY(3));
488
489 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
490 case SND_SOC_DAIFMT_CBS_CFS:
491 /* codec is clock and frame slave */
492 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
493 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
494
495 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
496 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
497
498 /* BCLK */
499 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
500 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
501 /* Frame Sync */
502 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
503 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
504
505 mcasp->bclk_master = 1;
506 break;
507 case SND_SOC_DAIFMT_CBS_CFM:
508 /* codec is clock slave and frame master */
509 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
510 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
511
512 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
513 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
514
515 /* BCLK */
516 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
517 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
518 /* Frame Sync */
519 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
520 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
521
522 mcasp->bclk_master = 1;
523 break;
524 case SND_SOC_DAIFMT_CBM_CFS:
525 /* codec is clock master and frame slave */
526 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
527 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
528
529 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
530 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
531
532 /* BCLK */
533 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
534 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
535 /* Frame Sync */
536 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
537 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
538
539 mcasp->bclk_master = 0;
540 break;
541 case SND_SOC_DAIFMT_CBM_CFM:
542 /* codec is clock and frame master */
543 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
545
546 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
548
549 /* BCLK */
550 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
551 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
552 /* Frame Sync */
553 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
554 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
555
556 mcasp->bclk_master = 0;
557 break;
558 default:
559 ret = -EINVAL;
560 goto out;
561 }
562
563 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
564 case SND_SOC_DAIFMT_IB_NF:
565 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
567 fs_pol_rising = true;
568 break;
569 case SND_SOC_DAIFMT_NB_IF:
570 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
571 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
572 fs_pol_rising = false;
573 break;
574 case SND_SOC_DAIFMT_IB_IF:
575 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
576 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
577 fs_pol_rising = false;
578 break;
579 case SND_SOC_DAIFMT_NB_NF:
580 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
581 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
582 fs_pol_rising = true;
583 break;
584 default:
585 ret = -EINVAL;
586 goto out;
587 }
588
589 if (inv_fs)
590 fs_pol_rising = !fs_pol_rising;
591
592 if (fs_pol_rising) {
593 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
594 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
595 } else {
596 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
597 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
598 }
599
600 mcasp->dai_fmt = fmt;
601 out:
602 pm_runtime_put(mcasp->dev);
603 return ret;
604 }
605
606 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
607 int div, bool explicit)
608 {
609 pm_runtime_get_sync(mcasp->dev);
610 switch (div_id) {
611 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
612 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
613 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
614 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
615 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
616 break;
617
618 case MCASP_CLKDIV_BCLK: /* BCLK divider */
619 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
620 ACLKXDIV(div - 1), ACLKXDIV_MASK);
621 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
622 ACLKRDIV(div - 1), ACLKRDIV_MASK);
623 if (explicit)
624 mcasp->bclk_div = div;
625 break;
626
627 case MCASP_CLKDIV_BCLK_FS_RATIO:
628 /*
629 * BCLK/LRCLK ratio descries how many bit-clock cycles
630 * fit into one frame. The clock ratio is given for a
631 * full period of data (for I2S format both left and
632 * right channels), so it has to be divided by number
633 * of tdm-slots (for I2S - divided by 2).
634 * Instead of storing this ratio, we calculate a new
635 * tdm_slot width by dividing the the ratio by the
636 * number of configured tdm slots.
637 */
638 mcasp->slot_width = div / mcasp->tdm_slots;
639 if (div % mcasp->tdm_slots)
640 dev_warn(mcasp->dev,
641 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
642 __func__, div, mcasp->tdm_slots);
643 break;
644
645 default:
646 return -EINVAL;
647 }
648
649 pm_runtime_put(mcasp->dev);
650 return 0;
651 }
652
653 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
654 int div)
655 {
656 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
657
658 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
659 }
660
661 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
662 unsigned int freq, int dir)
663 {
664 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
665
666 pm_runtime_get_sync(mcasp->dev);
667
668 if (dir == SND_SOC_CLOCK_IN) {
669 switch (clk_id) {
670 case MCASP_CLK_HCLK_AHCLK:
671 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
672 AHCLKXE);
673 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
674 AHCLKRE);
675 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
676 break;
677 case MCASP_CLK_HCLK_AUXCLK:
678 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
679 AHCLKXE);
680 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
681 AHCLKRE);
682 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
683 break;
684 default:
685 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
686 goto out;
687 }
688 } else {
689 /* Select AUXCLK as HCLK */
690 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
691 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
692 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
693 }
694 /*
695 * When AHCLK X/R is selected to be output it means that the HCLK is
696 * the same clock - coming via AUXCLK.
697 */
698 mcasp->sysclk_freq = freq;
699 out:
700 pm_runtime_put(mcasp->dev);
701 return 0;
702 }
703
704 /* All serializers must have equal number of channels */
705 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
706 int serializers)
707 {
708 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
709 unsigned int *list = (unsigned int *) cl->list;
710 int slots = mcasp->tdm_slots;
711 int i, count = 0;
712
713 if (mcasp->tdm_mask[stream])
714 slots = hweight32(mcasp->tdm_mask[stream]);
715
716 for (i = 1; i <= slots; i++)
717 list[count++] = i;
718
719 for (i = 2; i <= serializers; i++)
720 list[count++] = i*slots;
721
722 cl->count = count;
723
724 return 0;
725 }
726
727 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
728 {
729 int rx_serializers = 0, tx_serializers = 0, ret, i;
730
731 for (i = 0; i < mcasp->num_serializer; i++)
732 if (mcasp->serial_dir[i] == TX_MODE)
733 tx_serializers++;
734 else if (mcasp->serial_dir[i] == RX_MODE)
735 rx_serializers++;
736
737 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
738 tx_serializers);
739 if (ret)
740 return ret;
741
742 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
743 rx_serializers);
744
745 return ret;
746 }
747
748
749 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
750 unsigned int tx_mask,
751 unsigned int rx_mask,
752 int slots, int slot_width)
753 {
754 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
755
756 dev_dbg(mcasp->dev,
757 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
758 __func__, tx_mask, rx_mask, slots, slot_width);
759
760 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
761 dev_err(mcasp->dev,
762 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
763 tx_mask, rx_mask, slots);
764 return -EINVAL;
765 }
766
767 if (slot_width &&
768 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
769 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
770 __func__, slot_width);
771 return -EINVAL;
772 }
773
774 mcasp->tdm_slots = slots;
775 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
776 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
777 mcasp->slot_width = slot_width;
778
779 return davinci_mcasp_set_ch_constraints(mcasp);
780 }
781
782 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
783 int sample_width)
784 {
785 u32 fmt;
786 u32 tx_rotate, rx_rotate, slot_width;
787 u32 mask = (1ULL << sample_width) - 1;
788
789 if (mcasp->slot_width)
790 slot_width = mcasp->slot_width;
791 else if (mcasp->max_format_width)
792 slot_width = mcasp->max_format_width;
793 else
794 slot_width = sample_width;
795 /*
796 * TX rotation:
797 * right aligned formats: rotate w/ slot_width
798 * left aligned formats: rotate w/ sample_width
799 *
800 * RX rotation:
801 * right aligned formats: no rotation needed
802 * left aligned formats: rotate w/ (slot_width - sample_width)
803 */
804 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
805 SND_SOC_DAIFMT_RIGHT_J) {
806 tx_rotate = (slot_width / 4) & 0x7;
807 rx_rotate = 0;
808 } else {
809 tx_rotate = (sample_width / 4) & 0x7;
810 rx_rotate = (slot_width - sample_width) / 4;
811 }
812
813 /* mapping of the XSSZ bit-field as described in the datasheet */
814 fmt = (slot_width >> 1) - 1;
815
816 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
817 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
818 RXSSZ(0x0F));
819 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
820 TXSSZ(0x0F));
821 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
822 TXROT(7));
823 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
824 RXROT(7));
825 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
826 }
827
828 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
829
830 return 0;
831 }
832
833 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
834 int period_words, int channels)
835 {
836 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
837 int i;
838 u8 tx_ser = 0;
839 u8 rx_ser = 0;
840 u8 slots = mcasp->tdm_slots;
841 u8 max_active_serializers = (channels + slots - 1) / slots;
842 u8 max_rx_serializers, max_tx_serializers;
843 int active_serializers, numevt;
844 u32 reg;
845 /* Default configuration */
846 if (mcasp->version < MCASP_VERSION_3)
847 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
848
849 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
850 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
851 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
852 max_tx_serializers = max_active_serializers;
853 max_rx_serializers =
854 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
855 } else {
856 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
857 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
858 max_tx_serializers =
859 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
860 max_rx_serializers = max_active_serializers;
861 }
862
863 for (i = 0; i < mcasp->num_serializer; i++) {
864 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
865 mcasp->serial_dir[i]);
866 if (mcasp->serial_dir[i] == TX_MODE &&
867 tx_ser < max_tx_serializers) {
868 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
869 mcasp->dismod, DISMOD_MASK);
870 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
871 tx_ser++;
872 } else if (mcasp->serial_dir[i] == RX_MODE &&
873 rx_ser < max_rx_serializers) {
874 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
875 rx_ser++;
876 } else {
877 /* Inactive or unused pin, set it to inactive */
878 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
879 SRMOD_INACTIVE, SRMOD_MASK);
880 /* If unused, set DISMOD for the pin */
881 if (mcasp->serial_dir[i] != INACTIVE_MODE)
882 mcasp_mod_bits(mcasp,
883 DAVINCI_MCASP_XRSRCTL_REG(i),
884 mcasp->dismod, DISMOD_MASK);
885 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
886 }
887 }
888
889 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
890 active_serializers = tx_ser;
891 numevt = mcasp->txnumevt;
892 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
893 } else {
894 active_serializers = rx_ser;
895 numevt = mcasp->rxnumevt;
896 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
897 }
898
899 if (active_serializers < max_active_serializers) {
900 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
901 "enabled in mcasp (%d)\n", channels,
902 active_serializers * slots);
903 return -EINVAL;
904 }
905
906 /* AFIFO is not in use */
907 if (!numevt) {
908 /* Configure the burst size for platform drivers */
909 if (active_serializers > 1) {
910 /*
911 * If more than one serializers are in use we have one
912 * DMA request to provide data for all serializers.
913 * For example if three serializers are enabled the DMA
914 * need to transfer three words per DMA request.
915 */
916 dma_data->maxburst = active_serializers;
917 } else {
918 dma_data->maxburst = 0;
919 }
920
921 goto out;
922 }
923
924 if (period_words % active_serializers) {
925 dev_err(mcasp->dev, "Invalid combination of period words and "
926 "active serializers: %d, %d\n", period_words,
927 active_serializers);
928 return -EINVAL;
929 }
930
931 /*
932 * Calculate the optimal AFIFO depth for platform side:
933 * The number of words for numevt need to be in steps of active
934 * serializers.
935 */
936 numevt = (numevt / active_serializers) * active_serializers;
937
938 while (period_words % numevt && numevt > 0)
939 numevt -= active_serializers;
940 if (numevt <= 0)
941 numevt = active_serializers;
942
943 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
944 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
945
946 /* Configure the burst size for platform drivers */
947 if (numevt == 1)
948 numevt = 0;
949 dma_data->maxburst = numevt;
950
951 out:
952 mcasp->active_serializers[stream] = active_serializers;
953
954 return 0;
955 }
956
957 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
958 int channels)
959 {
960 int i, active_slots;
961 int total_slots;
962 int active_serializers;
963 u32 mask = 0;
964 u32 busel = 0;
965
966 total_slots = mcasp->tdm_slots;
967
968 /*
969 * If more than one serializer is needed, then use them with
970 * all the specified tdm_slots. Otherwise, one serializer can
971 * cope with the transaction using just as many slots as there
972 * are channels in the stream.
973 */
974 if (mcasp->tdm_mask[stream]) {
975 active_slots = hweight32(mcasp->tdm_mask[stream]);
976 active_serializers = (channels + active_slots - 1) /
977 active_slots;
978 if (active_serializers == 1)
979 active_slots = channels;
980 for (i = 0; i < total_slots; i++) {
981 if ((1 << i) & mcasp->tdm_mask[stream]) {
982 mask |= (1 << i);
983 if (--active_slots <= 0)
984 break;
985 }
986 }
987 } else {
988 active_serializers = (channels + total_slots - 1) / total_slots;
989 if (active_serializers == 1)
990 active_slots = channels;
991 else
992 active_slots = total_slots;
993
994 for (i = 0; i < active_slots; i++)
995 mask |= (1 << i);
996 }
997
998 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
999
1000 if (!mcasp->dat_port)
1001 busel = TXSEL;
1002
1003 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1004 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
1005 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
1006 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1007 FSXMOD(total_slots), FSXMOD(0x1FF));
1008 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1009 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
1010 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
1011 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
1012 FSRMOD(total_slots), FSRMOD(0x1FF));
1013 /*
1014 * If McASP is set to be TX/RX synchronous and the playback is
1015 * not running already we need to configure the TX slots in
1016 * order to have correct FSX on the bus
1017 */
1018 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
1019 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1020 FSXMOD(total_slots), FSXMOD(0x1FF));
1021 }
1022
1023 return 0;
1024 }
1025
1026 /* S/PDIF */
1027 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1028 unsigned int rate)
1029 {
1030 u32 cs_value = 0;
1031 u8 *cs_bytes = (u8*) &cs_value;
1032
1033 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
1034 and LSB first */
1035 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
1036
1037 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1038 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1039
1040 /* Set the TX tdm : for all the slots */
1041 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1042
1043 /* Set the TX clock controls : div = 1 and internal */
1044 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1045
1046 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1047
1048 /* Only 44100 and 48000 are valid, both have the same setting */
1049 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
1050
1051 /* Enable the DIT */
1052 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1053
1054 /* Set S/PDIF channel status bits */
1055 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1056 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1057
1058 switch (rate) {
1059 case 22050:
1060 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1061 break;
1062 case 24000:
1063 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1064 break;
1065 case 32000:
1066 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1067 break;
1068 case 44100:
1069 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1070 break;
1071 case 48000:
1072 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1073 break;
1074 case 88200:
1075 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1076 break;
1077 case 96000:
1078 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1079 break;
1080 case 176400:
1081 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1082 break;
1083 case 192000:
1084 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1085 break;
1086 default:
1087 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1088 return -EINVAL;
1089 }
1090
1091 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1092 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1093
1094 return 0;
1095 }
1096
1097 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1098 unsigned int sysclk_freq,
1099 unsigned int bclk_freq, bool set)
1100 {
1101 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1102 int div = sysclk_freq / bclk_freq;
1103 int rem = sysclk_freq % bclk_freq;
1104 int error_ppm;
1105 int aux_div = 1;
1106
1107 if (div > (ACLKXDIV_MASK + 1)) {
1108 if (reg & AHCLKXE) {
1109 aux_div = div / (ACLKXDIV_MASK + 1);
1110 if (div % (ACLKXDIV_MASK + 1))
1111 aux_div++;
1112
1113 sysclk_freq /= aux_div;
1114 div = sysclk_freq / bclk_freq;
1115 rem = sysclk_freq % bclk_freq;
1116 } else if (set) {
1117 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1118 sysclk_freq);
1119 }
1120 }
1121
1122 if (rem != 0) {
1123 if (div == 0 ||
1124 ((sysclk_freq / div) - bclk_freq) >
1125 (bclk_freq - (sysclk_freq / (div+1)))) {
1126 div++;
1127 rem = rem - bclk_freq;
1128 }
1129 }
1130 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1131 (int)bclk_freq)) / div - 1000000;
1132
1133 if (set) {
1134 if (error_ppm)
1135 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1136 error_ppm);
1137
1138 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1139 if (reg & AHCLKXE)
1140 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1141 aux_div, 0);
1142 }
1143
1144 return error_ppm;
1145 }
1146
1147 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1148 {
1149 if (!mcasp->txnumevt)
1150 return 0;
1151
1152 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1153 }
1154
1155 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1156 {
1157 if (!mcasp->rxnumevt)
1158 return 0;
1159
1160 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1161 }
1162
1163 static snd_pcm_sframes_t davinci_mcasp_delay(
1164 struct snd_pcm_substream *substream,
1165 struct snd_soc_dai *cpu_dai)
1166 {
1167 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1168 u32 fifo_use;
1169
1170 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1171 fifo_use = davinci_mcasp_tx_delay(mcasp);
1172 else
1173 fifo_use = davinci_mcasp_rx_delay(mcasp);
1174
1175 /*
1176 * Divide the used locations with the channel count to get the
1177 * FIFO usage in samples (don't care about partial samples in the
1178 * buffer).
1179 */
1180 return fifo_use / substream->runtime->channels;
1181 }
1182
1183 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1184 struct snd_pcm_hw_params *params,
1185 struct snd_soc_dai *cpu_dai)
1186 {
1187 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1188 int word_length;
1189 int channels = params_channels(params);
1190 int period_size = params_period_size(params);
1191 int ret;
1192
1193 switch (params_format(params)) {
1194 case SNDRV_PCM_FORMAT_U8:
1195 case SNDRV_PCM_FORMAT_S8:
1196 word_length = 8;
1197 break;
1198
1199 case SNDRV_PCM_FORMAT_U16_LE:
1200 case SNDRV_PCM_FORMAT_S16_LE:
1201 word_length = 16;
1202 break;
1203
1204 case SNDRV_PCM_FORMAT_U24_3LE:
1205 case SNDRV_PCM_FORMAT_S24_3LE:
1206 word_length = 24;
1207 break;
1208
1209 case SNDRV_PCM_FORMAT_U24_LE:
1210 case SNDRV_PCM_FORMAT_S24_LE:
1211 word_length = 24;
1212 break;
1213
1214 case SNDRV_PCM_FORMAT_U32_LE:
1215 case SNDRV_PCM_FORMAT_S32_LE:
1216 word_length = 32;
1217 break;
1218
1219 default:
1220 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1221 return -EINVAL;
1222 }
1223
1224 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1225 if (ret)
1226 return ret;
1227
1228 /*
1229 * If mcasp is BCLK master, and a BCLK divider was not provided by
1230 * the machine driver, we need to calculate the ratio.
1231 */
1232 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1233 int slots = mcasp->tdm_slots;
1234 int rate = params_rate(params);
1235 int sbits = params_width(params);
1236
1237 if (mcasp->slot_width)
1238 sbits = mcasp->slot_width;
1239
1240 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1241 rate * sbits * slots, true);
1242 }
1243
1244 ret = mcasp_common_hw_param(mcasp, substream->stream,
1245 period_size * channels, channels);
1246 if (ret)
1247 return ret;
1248
1249 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1250 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1251 else
1252 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1253 channels);
1254
1255 if (ret)
1256 return ret;
1257
1258 davinci_config_channel_size(mcasp, word_length);
1259
1260 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1261 mcasp->channels = channels;
1262 if (!mcasp->max_format_width)
1263 mcasp->max_format_width = word_length;
1264 }
1265
1266 return 0;
1267 }
1268
1269 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1270 int cmd, struct snd_soc_dai *cpu_dai)
1271 {
1272 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1273 int ret = 0;
1274
1275 switch (cmd) {
1276 case SNDRV_PCM_TRIGGER_RESUME:
1277 case SNDRV_PCM_TRIGGER_START:
1278 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1279 davinci_mcasp_start(mcasp, substream->stream);
1280 break;
1281 case SNDRV_PCM_TRIGGER_SUSPEND:
1282 case SNDRV_PCM_TRIGGER_STOP:
1283 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1284 davinci_mcasp_stop(mcasp, substream->stream);
1285 break;
1286
1287 default:
1288 ret = -EINVAL;
1289 }
1290
1291 return ret;
1292 }
1293
1294 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1295 struct snd_pcm_hw_rule *rule)
1296 {
1297 struct davinci_mcasp_ruledata *rd = rule->private;
1298 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1299 struct snd_mask nfmt;
1300 int i, slot_width;
1301
1302 snd_mask_none(&nfmt);
1303 slot_width = rd->mcasp->slot_width;
1304
1305 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1306 if (snd_mask_test(fmt, i)) {
1307 if (snd_pcm_format_width(i) <= slot_width) {
1308 snd_mask_set(&nfmt, i);
1309 }
1310 }
1311 }
1312
1313 return snd_mask_refine(fmt, &nfmt);
1314 }
1315
1316 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,
1317 struct snd_pcm_hw_rule *rule)
1318 {
1319 struct davinci_mcasp_ruledata *rd = rule->private;
1320 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1321 struct snd_mask nfmt;
1322 int i, format_width;
1323
1324 snd_mask_none(&nfmt);
1325 format_width = rd->mcasp->max_format_width;
1326
1327 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1328 if (snd_mask_test(fmt, i)) {
1329 if (snd_pcm_format_width(i) == format_width) {
1330 snd_mask_set(&nfmt, i);
1331 }
1332 }
1333 }
1334
1335 return snd_mask_refine(fmt, &nfmt);
1336 }
1337
1338 static const unsigned int davinci_mcasp_dai_rates[] = {
1339 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1340 88200, 96000, 176400, 192000,
1341 };
1342
1343 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1344
1345 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1346 struct snd_pcm_hw_rule *rule)
1347 {
1348 struct davinci_mcasp_ruledata *rd = rule->private;
1349 struct snd_interval *ri =
1350 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1351 int sbits = params_width(params);
1352 int slots = rd->mcasp->tdm_slots;
1353 struct snd_interval range;
1354 int i;
1355
1356 if (rd->mcasp->slot_width)
1357 sbits = rd->mcasp->slot_width;
1358
1359 snd_interval_any(&range);
1360 range.empty = 1;
1361
1362 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1363 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1364 uint bclk_freq = sbits * slots *
1365 davinci_mcasp_dai_rates[i];
1366 unsigned int sysclk_freq;
1367 int ppm;
1368
1369 if (rd->mcasp->auxclk_fs_ratio)
1370 sysclk_freq = davinci_mcasp_dai_rates[i] *
1371 rd->mcasp->auxclk_fs_ratio;
1372 else
1373 sysclk_freq = rd->mcasp->sysclk_freq;
1374
1375 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1376 bclk_freq, false);
1377 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1378 if (range.empty) {
1379 range.min = davinci_mcasp_dai_rates[i];
1380 range.empty = 0;
1381 }
1382 range.max = davinci_mcasp_dai_rates[i];
1383 }
1384 }
1385 }
1386
1387 dev_dbg(rd->mcasp->dev,
1388 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1389 ri->min, ri->max, range.min, range.max, sbits, slots);
1390
1391 return snd_interval_refine(hw_param_interval(params, rule->var),
1392 &range);
1393 }
1394
1395 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1396 struct snd_pcm_hw_rule *rule)
1397 {
1398 struct davinci_mcasp_ruledata *rd = rule->private;
1399 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1400 struct snd_mask nfmt;
1401 int rate = params_rate(params);
1402 int slots = rd->mcasp->tdm_slots;
1403 int i, count = 0;
1404
1405 snd_mask_none(&nfmt);
1406
1407 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1408 if (snd_mask_test(fmt, i)) {
1409 uint sbits = snd_pcm_format_width(i);
1410 unsigned int sysclk_freq;
1411 int ppm;
1412
1413 if (rd->mcasp->auxclk_fs_ratio)
1414 sysclk_freq = rate *
1415 rd->mcasp->auxclk_fs_ratio;
1416 else
1417 sysclk_freq = rd->mcasp->sysclk_freq;
1418
1419 if (rd->mcasp->slot_width)
1420 sbits = rd->mcasp->slot_width;
1421
1422 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1423 sbits * slots * rate,
1424 false);
1425 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1426 snd_mask_set(&nfmt, i);
1427 count++;
1428 }
1429 }
1430 }
1431 dev_dbg(rd->mcasp->dev,
1432 "%d possible sample format for %d Hz and %d tdm slots\n",
1433 count, rate, slots);
1434
1435 return snd_mask_refine(fmt, &nfmt);
1436 }
1437
1438 static int davinci_mcasp_hw_rule_min_periodsize(
1439 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1440 {
1441 struct snd_interval *period_size = hw_param_interval(params,
1442 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1443 struct snd_interval frames;
1444
1445 snd_interval_any(&frames);
1446 frames.min = 64;
1447 frames.integer = 1;
1448
1449 return snd_interval_refine(period_size, &frames);
1450 }
1451
1452 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1453 struct snd_soc_dai *cpu_dai)
1454 {
1455 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1456 struct davinci_mcasp_ruledata *ruledata =
1457 &mcasp->ruledata[substream->stream];
1458 u32 max_channels = 0;
1459 int i, dir, ret;
1460 int tdm_slots = mcasp->tdm_slots;
1461
1462 /* Do not allow more then one stream per direction */
1463 if (mcasp->substreams[substream->stream])
1464 return -EBUSY;
1465
1466 mcasp->substreams[substream->stream] = substream;
1467
1468 if (mcasp->tdm_mask[substream->stream])
1469 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1470
1471 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1472 return 0;
1473
1474 /*
1475 * Limit the maximum allowed channels for the first stream:
1476 * number of serializers for the direction * tdm slots per serializer
1477 */
1478 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1479 dir = TX_MODE;
1480 else
1481 dir = RX_MODE;
1482
1483 for (i = 0; i < mcasp->num_serializer; i++) {
1484 if (mcasp->serial_dir[i] == dir)
1485 max_channels++;
1486 }
1487 ruledata->serializers = max_channels;
1488 ruledata->mcasp = mcasp;
1489 max_channels *= tdm_slots;
1490 /*
1491 * If the already active stream has less channels than the calculated
1492 * limit based on the seirializers * tdm_slots, and only one serializer
1493 * is in use we need to use that as a constraint for the second stream.
1494 * Otherwise (first stream or less allowed channels or more than one
1495 * serializer in use) we use the calculated constraint.
1496 */
1497 if (mcasp->channels && mcasp->channels < max_channels &&
1498 ruledata->serializers == 1)
1499 max_channels = mcasp->channels;
1500 /*
1501 * But we can always allow channels upto the amount of
1502 * the available tdm_slots.
1503 */
1504 if (max_channels < tdm_slots)
1505 max_channels = tdm_slots;
1506
1507 snd_pcm_hw_constraint_minmax(substream->runtime,
1508 SNDRV_PCM_HW_PARAM_CHANNELS,
1509 0, max_channels);
1510
1511 snd_pcm_hw_constraint_list(substream->runtime,
1512 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1513 &mcasp->chconstr[substream->stream]);
1514
1515 if (mcasp->max_format_width) {
1516 /*
1517 * Only allow formats which require same amount of bits on the
1518 * bus as the currently running stream
1519 */
1520 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1521 SNDRV_PCM_HW_PARAM_FORMAT,
1522 davinci_mcasp_hw_rule_format_width,
1523 ruledata,
1524 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1525 if (ret)
1526 return ret;
1527 }
1528 else if (mcasp->slot_width) {
1529 /* Only allow formats require <= slot_width bits on the bus */
1530 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1531 SNDRV_PCM_HW_PARAM_FORMAT,
1532 davinci_mcasp_hw_rule_slot_width,
1533 ruledata,
1534 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1535 if (ret)
1536 return ret;
1537 }
1538
1539 /*
1540 * If we rely on implicit BCLK divider setting we should
1541 * set constraints based on what we can provide.
1542 */
1543 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1544 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1545 SNDRV_PCM_HW_PARAM_RATE,
1546 davinci_mcasp_hw_rule_rate,
1547 ruledata,
1548 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1549 if (ret)
1550 return ret;
1551 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1552 SNDRV_PCM_HW_PARAM_FORMAT,
1553 davinci_mcasp_hw_rule_format,
1554 ruledata,
1555 SNDRV_PCM_HW_PARAM_RATE, -1);
1556 if (ret)
1557 return ret;
1558 }
1559
1560 snd_pcm_hw_rule_add(substream->runtime, 0,
1561 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1562 davinci_mcasp_hw_rule_min_periodsize, NULL,
1563 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1564
1565 return 0;
1566 }
1567
1568 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1569 struct snd_soc_dai *cpu_dai)
1570 {
1571 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1572
1573 mcasp->substreams[substream->stream] = NULL;
1574 mcasp->active_serializers[substream->stream] = 0;
1575
1576 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1577 return;
1578
1579 if (!cpu_dai->active) {
1580 mcasp->channels = 0;
1581 mcasp->max_format_width = 0;
1582 }
1583 }
1584
1585 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1586 .startup = davinci_mcasp_startup,
1587 .shutdown = davinci_mcasp_shutdown,
1588 .trigger = davinci_mcasp_trigger,
1589 .delay = davinci_mcasp_delay,
1590 .hw_params = davinci_mcasp_hw_params,
1591 .set_fmt = davinci_mcasp_set_dai_fmt,
1592 .set_clkdiv = davinci_mcasp_set_clkdiv,
1593 .set_sysclk = davinci_mcasp_set_sysclk,
1594 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1595 };
1596
1597 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1598 {
1599 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1600
1601 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1602 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1603
1604 return 0;
1605 }
1606
1607 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1608
1609 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1610 SNDRV_PCM_FMTBIT_U8 | \
1611 SNDRV_PCM_FMTBIT_S16_LE | \
1612 SNDRV_PCM_FMTBIT_U16_LE | \
1613 SNDRV_PCM_FMTBIT_S24_LE | \
1614 SNDRV_PCM_FMTBIT_U24_LE | \
1615 SNDRV_PCM_FMTBIT_S24_3LE | \
1616 SNDRV_PCM_FMTBIT_U24_3LE | \
1617 SNDRV_PCM_FMTBIT_S32_LE | \
1618 SNDRV_PCM_FMTBIT_U32_LE)
1619
1620 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1621 {
1622 .name = "davinci-mcasp.0",
1623 .probe = davinci_mcasp_dai_probe,
1624 .playback = {
1625 .channels_min = 1,
1626 .channels_max = 32 * 16,
1627 .rates = DAVINCI_MCASP_RATES,
1628 .formats = DAVINCI_MCASP_PCM_FMTS,
1629 },
1630 .capture = {
1631 .channels_min = 1,
1632 .channels_max = 32 * 16,
1633 .rates = DAVINCI_MCASP_RATES,
1634 .formats = DAVINCI_MCASP_PCM_FMTS,
1635 },
1636 .ops = &davinci_mcasp_dai_ops,
1637
1638 .symmetric_rates = 1,
1639 },
1640 {
1641 .name = "davinci-mcasp.1",
1642 .probe = davinci_mcasp_dai_probe,
1643 .playback = {
1644 .channels_min = 1,
1645 .channels_max = 384,
1646 .rates = DAVINCI_MCASP_RATES,
1647 .formats = DAVINCI_MCASP_PCM_FMTS,
1648 },
1649 .ops = &davinci_mcasp_dai_ops,
1650 },
1651
1652 };
1653
1654 static const struct snd_soc_component_driver davinci_mcasp_component = {
1655 .name = "davinci-mcasp",
1656 };
1657
1658 /* Some HW specific values and defaults. The rest is filled in from DT. */
1659 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1660 .tx_dma_offset = 0x400,
1661 .rx_dma_offset = 0x400,
1662 .version = MCASP_VERSION_1,
1663 };
1664
1665 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1666 .tx_dma_offset = 0x2000,
1667 .rx_dma_offset = 0x2000,
1668 .version = MCASP_VERSION_2,
1669 };
1670
1671 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1672 .tx_dma_offset = 0,
1673 .rx_dma_offset = 0,
1674 .version = MCASP_VERSION_3,
1675 };
1676
1677 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1678 /* The CFG port offset will be calculated if it is needed */
1679 .tx_dma_offset = 0,
1680 .rx_dma_offset = 0,
1681 .version = MCASP_VERSION_4,
1682 };
1683
1684 static const struct of_device_id mcasp_dt_ids[] = {
1685 {
1686 .compatible = "ti,dm646x-mcasp-audio",
1687 .data = &dm646x_mcasp_pdata,
1688 },
1689 {
1690 .compatible = "ti,da830-mcasp-audio",
1691 .data = &da830_mcasp_pdata,
1692 },
1693 {
1694 .compatible = "ti,am33xx-mcasp-audio",
1695 .data = &am33xx_mcasp_pdata,
1696 },
1697 {
1698 .compatible = "ti,dra7-mcasp-audio",
1699 .data = &dra7_mcasp_pdata,
1700 },
1701 { /* sentinel */ }
1702 };
1703 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1704
1705 static int mcasp_reparent_fck(struct platform_device *pdev)
1706 {
1707 struct device_node *node = pdev->dev.of_node;
1708 struct clk *gfclk, *parent_clk;
1709 const char *parent_name;
1710 int ret;
1711
1712 if (!node)
1713 return 0;
1714
1715 parent_name = of_get_property(node, "fck_parent", NULL);
1716 if (!parent_name)
1717 return 0;
1718
1719 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1720
1721 gfclk = clk_get(&pdev->dev, "fck");
1722 if (IS_ERR(gfclk)) {
1723 dev_err(&pdev->dev, "failed to get fck\n");
1724 return PTR_ERR(gfclk);
1725 }
1726
1727 parent_clk = clk_get(NULL, parent_name);
1728 if (IS_ERR(parent_clk)) {
1729 dev_err(&pdev->dev, "failed to get parent clock\n");
1730 ret = PTR_ERR(parent_clk);
1731 goto err1;
1732 }
1733
1734 ret = clk_set_parent(gfclk, parent_clk);
1735 if (ret) {
1736 dev_err(&pdev->dev, "failed to reparent fck\n");
1737 goto err2;
1738 }
1739
1740 err2:
1741 clk_put(parent_clk);
1742 err1:
1743 clk_put(gfclk);
1744 return ret;
1745 }
1746
1747 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1748 struct platform_device *pdev)
1749 {
1750 struct device_node *np = pdev->dev.of_node;
1751 struct davinci_mcasp_pdata *pdata = NULL;
1752 const struct of_device_id *match =
1753 of_match_device(mcasp_dt_ids, &pdev->dev);
1754 struct of_phandle_args dma_spec;
1755
1756 const u32 *of_serial_dir32;
1757 u32 val;
1758 int i, ret = 0;
1759
1760 if (pdev->dev.platform_data) {
1761 pdata = pdev->dev.platform_data;
1762 pdata->dismod = DISMOD_LOW;
1763 return pdata;
1764 } else if (match) {
1765 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1766 GFP_KERNEL);
1767 if (!pdata) {
1768 ret = -ENOMEM;
1769 return pdata;
1770 }
1771 } else {
1772 /* control shouldn't reach here. something is wrong */
1773 ret = -EINVAL;
1774 goto nodata;
1775 }
1776
1777 ret = of_property_read_u32(np, "op-mode", &val);
1778 if (ret >= 0)
1779 pdata->op_mode = val;
1780
1781 ret = of_property_read_u32(np, "tdm-slots", &val);
1782 if (ret >= 0) {
1783 if (val < 2 || val > 32) {
1784 dev_err(&pdev->dev,
1785 "tdm-slots must be in rage [2-32]\n");
1786 ret = -EINVAL;
1787 goto nodata;
1788 }
1789
1790 pdata->tdm_slots = val;
1791 }
1792
1793 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1794 val /= sizeof(u32);
1795 if (of_serial_dir32) {
1796 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1797 (sizeof(*of_serial_dir) * val),
1798 GFP_KERNEL);
1799 if (!of_serial_dir) {
1800 ret = -ENOMEM;
1801 goto nodata;
1802 }
1803
1804 for (i = 0; i < val; i++)
1805 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1806
1807 pdata->num_serializer = val;
1808 pdata->serial_dir = of_serial_dir;
1809 }
1810
1811 ret = of_property_match_string(np, "dma-names", "tx");
1812 if (ret < 0)
1813 goto nodata;
1814
1815 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1816 &dma_spec);
1817 if (ret < 0)
1818 goto nodata;
1819
1820 pdata->tx_dma_channel = dma_spec.args[0];
1821
1822 /* RX is not valid in DIT mode */
1823 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1824 ret = of_property_match_string(np, "dma-names", "rx");
1825 if (ret < 0)
1826 goto nodata;
1827
1828 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1829 &dma_spec);
1830 if (ret < 0)
1831 goto nodata;
1832
1833 pdata->rx_dma_channel = dma_spec.args[0];
1834 }
1835
1836 ret = of_property_read_u32(np, "tx-num-evt", &val);
1837 if (ret >= 0)
1838 pdata->txnumevt = val;
1839
1840 ret = of_property_read_u32(np, "rx-num-evt", &val);
1841 if (ret >= 0)
1842 pdata->rxnumevt = val;
1843
1844 ret = of_property_read_u32(np, "sram-size-playback", &val);
1845 if (ret >= 0)
1846 pdata->sram_size_playback = val;
1847
1848 ret = of_property_read_u32(np, "sram-size-capture", &val);
1849 if (ret >= 0)
1850 pdata->sram_size_capture = val;
1851
1852 ret = of_property_read_u32(np, "dismod", &val);
1853 if (ret >= 0) {
1854 if (val == 0 || val == 2 || val == 3) {
1855 pdata->dismod = DISMOD_VAL(val);
1856 } else {
1857 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1858 pdata->dismod = DISMOD_LOW;
1859 }
1860 } else {
1861 pdata->dismod = DISMOD_LOW;
1862 }
1863
1864 return pdata;
1865
1866 nodata:
1867 if (ret < 0) {
1868 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1869 ret);
1870 pdata = NULL;
1871 }
1872 return pdata;
1873 }
1874
1875 enum {
1876 PCM_EDMA,
1877 PCM_SDMA,
1878 };
1879 static const char *sdma_prefix = "ti,omap";
1880
1881 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1882 {
1883 struct dma_chan *chan;
1884 const char *tmp;
1885 int ret = PCM_EDMA;
1886
1887 if (!mcasp->dev->of_node)
1888 return PCM_EDMA;
1889
1890 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1891 chan = dma_request_chan(mcasp->dev, tmp);
1892 if (IS_ERR(chan)) {
1893 if (PTR_ERR(chan) != -EPROBE_DEFER)
1894 dev_err(mcasp->dev,
1895 "Can't verify DMA configuration (%ld)\n",
1896 PTR_ERR(chan));
1897 return PTR_ERR(chan);
1898 }
1899 if (WARN_ON(!chan->device || !chan->device->dev))
1900 return -EINVAL;
1901
1902 if (chan->device->dev->of_node)
1903 ret = of_property_read_string(chan->device->dev->of_node,
1904 "compatible", &tmp);
1905 else
1906 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1907
1908 dma_release_channel(chan);
1909 if (ret)
1910 return ret;
1911
1912 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1913 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1914 return PCM_SDMA;
1915
1916 return PCM_EDMA;
1917 }
1918
1919 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1920 {
1921 int i;
1922 u32 offset = 0;
1923
1924 if (pdata->version != MCASP_VERSION_4)
1925 return pdata->tx_dma_offset;
1926
1927 for (i = 0; i < pdata->num_serializer; i++) {
1928 if (pdata->serial_dir[i] == TX_MODE) {
1929 if (!offset) {
1930 offset = DAVINCI_MCASP_TXBUF_REG(i);
1931 } else {
1932 pr_err("%s: Only one serializer allowed!\n",
1933 __func__);
1934 break;
1935 }
1936 }
1937 }
1938
1939 return offset;
1940 }
1941
1942 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1943 {
1944 int i;
1945 u32 offset = 0;
1946
1947 if (pdata->version != MCASP_VERSION_4)
1948 return pdata->rx_dma_offset;
1949
1950 for (i = 0; i < pdata->num_serializer; i++) {
1951 if (pdata->serial_dir[i] == RX_MODE) {
1952 if (!offset) {
1953 offset = DAVINCI_MCASP_RXBUF_REG(i);
1954 } else {
1955 pr_err("%s: Only one serializer allowed!\n",
1956 __func__);
1957 break;
1958 }
1959 }
1960 }
1961
1962 return offset;
1963 }
1964
1965 #ifdef CONFIG_GPIOLIB
1966 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
1967 {
1968 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1969
1970 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
1971 mcasp->serial_dir[offset] != INACTIVE_MODE) {
1972 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
1973 return -EBUSY;
1974 }
1975
1976 /* Do not change the PIN yet */
1977
1978 return pm_runtime_get_sync(mcasp->dev);
1979 }
1980
1981 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
1982 {
1983 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1984
1985 /* Set the direction to input */
1986 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1987
1988 /* Set the pin as McASP pin */
1989 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1990
1991 pm_runtime_put_sync(mcasp->dev);
1992 }
1993
1994 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
1995 unsigned offset, int value)
1996 {
1997 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1998 u32 val;
1999
2000 if (value)
2001 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2002 else
2003 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2004
2005 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2006 if (!(val & BIT(offset))) {
2007 /* Set the pin as GPIO pin */
2008 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2009
2010 /* Set the direction to output */
2011 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2012 }
2013
2014 return 0;
2015 }
2016
2017 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
2018 int value)
2019 {
2020 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2021
2022 if (value)
2023 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2024 else
2025 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2026 }
2027
2028 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
2029 unsigned offset)
2030 {
2031 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2032 u32 val;
2033
2034 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2035 if (!(val & BIT(offset))) {
2036 /* Set the direction to input */
2037 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2038
2039 /* Set the pin as GPIO pin */
2040 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2041 }
2042
2043 return 0;
2044 }
2045
2046 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
2047 {
2048 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2049 u32 val;
2050
2051 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2052 if (val & BIT(offset))
2053 return 1;
2054
2055 return 0;
2056 }
2057
2058 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
2059 unsigned offset)
2060 {
2061 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2062 u32 val;
2063
2064 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2065 if (val & BIT(offset))
2066 return 0;
2067
2068 return 1;
2069 }
2070
2071 static const struct gpio_chip davinci_mcasp_template_chip = {
2072 .owner = THIS_MODULE,
2073 .request = davinci_mcasp_gpio_request,
2074 .free = davinci_mcasp_gpio_free,
2075 .direction_output = davinci_mcasp_gpio_direction_out,
2076 .set = davinci_mcasp_gpio_set,
2077 .direction_input = davinci_mcasp_gpio_direction_in,
2078 .get = davinci_mcasp_gpio_get,
2079 .get_direction = davinci_mcasp_gpio_get_direction,
2080 .base = -1,
2081 .ngpio = 32,
2082 };
2083
2084 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2085 {
2086 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
2087 return 0;
2088
2089 mcasp->gpio_chip = davinci_mcasp_template_chip;
2090 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2091 mcasp->gpio_chip.parent = mcasp->dev;
2092 #ifdef CONFIG_OF_GPIO
2093 mcasp->gpio_chip.of_node = mcasp->dev->of_node;
2094 #endif
2095
2096 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2097 }
2098
2099 #else /* CONFIG_GPIOLIB */
2100 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2101 {
2102 return 0;
2103 }
2104 #endif /* CONFIG_GPIOLIB */
2105
2106 static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
2107 {
2108 struct device_node *np = mcasp->dev->of_node;
2109 int ret;
2110 u32 val;
2111
2112 if (!np)
2113 return 0;
2114
2115 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val);
2116 if (ret >= 0)
2117 mcasp->auxclk_fs_ratio = val;
2118
2119 return 0;
2120 }
2121
2122 static int davinci_mcasp_probe(struct platform_device *pdev)
2123 {
2124 struct snd_dmaengine_dai_dma_data *dma_data;
2125 struct resource *mem, *res, *dat;
2126 struct davinci_mcasp_pdata *pdata;
2127 struct davinci_mcasp *mcasp;
2128 char *irq_name;
2129 int *dma;
2130 int irq;
2131 int ret;
2132
2133 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2134 dev_err(&pdev->dev, "No platform data supplied\n");
2135 return -EINVAL;
2136 }
2137
2138 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2139 GFP_KERNEL);
2140 if (!mcasp)
2141 return -ENOMEM;
2142
2143 pdata = davinci_mcasp_set_pdata_from_of(pdev);
2144 if (!pdata) {
2145 dev_err(&pdev->dev, "no platform data\n");
2146 return -EINVAL;
2147 }
2148
2149 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
2150 if (!mem) {
2151 dev_warn(mcasp->dev,
2152 "\"mpu\" mem resource not found, using index 0\n");
2153 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2154 if (!mem) {
2155 dev_err(&pdev->dev, "no mem resource?\n");
2156 return -ENODEV;
2157 }
2158 }
2159
2160 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2161 if (IS_ERR(mcasp->base))
2162 return PTR_ERR(mcasp->base);
2163
2164 pm_runtime_enable(&pdev->dev);
2165
2166 mcasp->op_mode = pdata->op_mode;
2167 /* sanity check for tdm slots parameter */
2168 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
2169 if (pdata->tdm_slots < 2) {
2170 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2171 pdata->tdm_slots);
2172 mcasp->tdm_slots = 2;
2173 } else if (pdata->tdm_slots > 32) {
2174 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2175 pdata->tdm_slots);
2176 mcasp->tdm_slots = 32;
2177 } else {
2178 mcasp->tdm_slots = pdata->tdm_slots;
2179 }
2180 }
2181
2182 mcasp->num_serializer = pdata->num_serializer;
2183 #ifdef CONFIG_PM
2184 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
2185 mcasp->num_serializer, sizeof(u32),
2186 GFP_KERNEL);
2187 if (!mcasp->context.xrsr_regs) {
2188 ret = -ENOMEM;
2189 goto err;
2190 }
2191 #endif
2192 mcasp->serial_dir = pdata->serial_dir;
2193 mcasp->version = pdata->version;
2194 mcasp->txnumevt = pdata->txnumevt;
2195 mcasp->rxnumevt = pdata->rxnumevt;
2196 mcasp->dismod = pdata->dismod;
2197
2198 mcasp->dev = &pdev->dev;
2199
2200 irq = platform_get_irq_byname(pdev, "common");
2201 if (irq >= 0) {
2202 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
2203 dev_name(&pdev->dev));
2204 if (!irq_name) {
2205 ret = -ENOMEM;
2206 goto err;
2207 }
2208 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2209 davinci_mcasp_common_irq_handler,
2210 IRQF_ONESHOT | IRQF_SHARED,
2211 irq_name, mcasp);
2212 if (ret) {
2213 dev_err(&pdev->dev, "common IRQ request failed\n");
2214 goto err;
2215 }
2216
2217 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2218 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2219 }
2220
2221 irq = platform_get_irq_byname(pdev, "rx");
2222 if (irq >= 0) {
2223 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
2224 dev_name(&pdev->dev));
2225 if (!irq_name) {
2226 ret = -ENOMEM;
2227 goto err;
2228 }
2229 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2230 davinci_mcasp_rx_irq_handler,
2231 IRQF_ONESHOT, irq_name, mcasp);
2232 if (ret) {
2233 dev_err(&pdev->dev, "RX IRQ request failed\n");
2234 goto err;
2235 }
2236
2237 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2238 }
2239
2240 irq = platform_get_irq_byname(pdev, "tx");
2241 if (irq >= 0) {
2242 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
2243 dev_name(&pdev->dev));
2244 if (!irq_name) {
2245 ret = -ENOMEM;
2246 goto err;
2247 }
2248 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2249 davinci_mcasp_tx_irq_handler,
2250 IRQF_ONESHOT, irq_name, mcasp);
2251 if (ret) {
2252 dev_err(&pdev->dev, "TX IRQ request failed\n");
2253 goto err;
2254 }
2255
2256 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2257 }
2258
2259 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
2260 if (dat)
2261 mcasp->dat_port = true;
2262
2263 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2264 if (dat)
2265 dma_data->addr = dat->start;
2266 else
2267 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
2268
2269 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
2270 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
2271 if (res)
2272 *dma = res->start;
2273 else
2274 *dma = pdata->tx_dma_channel;
2275
2276 /* dmaengine filter data for DT and non-DT boot */
2277 if (pdev->dev.of_node)
2278 dma_data->filter_data = "tx";
2279 else
2280 dma_data->filter_data = dma;
2281
2282 /* RX is not valid in DIT mode */
2283 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2284 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2285 if (dat)
2286 dma_data->addr = dat->start;
2287 else
2288 dma_data->addr =
2289 mem->start + davinci_mcasp_rxdma_offset(pdata);
2290
2291 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
2292 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2293 if (res)
2294 *dma = res->start;
2295 else
2296 *dma = pdata->rx_dma_channel;
2297
2298 /* dmaengine filter data for DT and non-DT boot */
2299 if (pdev->dev.of_node)
2300 dma_data->filter_data = "rx";
2301 else
2302 dma_data->filter_data = dma;
2303 }
2304
2305 if (mcasp->version < MCASP_VERSION_3) {
2306 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2307 /* dma_params->dma_addr is pointing to the data port address */
2308 mcasp->dat_port = true;
2309 } else {
2310 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2311 }
2312
2313 /* Allocate memory for long enough list for all possible
2314 * scenarios. Maximum number tdm slots is 32 and there cannot
2315 * be more serializers than given in the configuration. The
2316 * serializer directions could be taken into account, but it
2317 * would make code much more complex and save only couple of
2318 * bytes.
2319 */
2320 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2321 devm_kcalloc(mcasp->dev,
2322 32 + mcasp->num_serializer - 1,
2323 sizeof(unsigned int),
2324 GFP_KERNEL);
2325
2326 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2327 devm_kcalloc(mcasp->dev,
2328 32 + mcasp->num_serializer - 1,
2329 sizeof(unsigned int),
2330 GFP_KERNEL);
2331
2332 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2333 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2334 ret = -ENOMEM;
2335 goto err;
2336 }
2337
2338 ret = davinci_mcasp_set_ch_constraints(mcasp);
2339 if (ret)
2340 goto err;
2341
2342 dev_set_drvdata(&pdev->dev, mcasp);
2343
2344 mcasp_reparent_fck(pdev);
2345
2346 /* All PINS as McASP */
2347 pm_runtime_get_sync(mcasp->dev);
2348 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2349 pm_runtime_put(mcasp->dev);
2350
2351 ret = davinci_mcasp_init_gpiochip(mcasp);
2352 if (ret)
2353 goto err;
2354
2355 ret = davinci_mcasp_get_dt_params(mcasp);
2356 if (ret)
2357 return -EINVAL;
2358
2359 ret = devm_snd_soc_register_component(&pdev->dev,
2360 &davinci_mcasp_component,
2361 &davinci_mcasp_dai[pdata->op_mode], 1);
2362
2363 if (ret != 0)
2364 goto err;
2365
2366 ret = davinci_mcasp_get_dma_type(mcasp);
2367 switch (ret) {
2368 case PCM_EDMA:
2369 ret = edma_pcm_platform_register(&pdev->dev);
2370 break;
2371 case PCM_SDMA:
2372 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
2373 break;
2374 default:
2375 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2376 case -EPROBE_DEFER:
2377 goto err;
2378 break;
2379 }
2380
2381 if (ret) {
2382 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2383 goto err;
2384 }
2385
2386 return 0;
2387
2388 err:
2389 pm_runtime_disable(&pdev->dev);
2390 return ret;
2391 }
2392
2393 static int davinci_mcasp_remove(struct platform_device *pdev)
2394 {
2395 pm_runtime_disable(&pdev->dev);
2396
2397 return 0;
2398 }
2399
2400 #ifdef CONFIG_PM
2401 static int davinci_mcasp_runtime_suspend(struct device *dev)
2402 {
2403 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2404 struct davinci_mcasp_context *context = &mcasp->context;
2405 u32 reg;
2406 int i;
2407
2408 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2409 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2410
2411 if (mcasp->txnumevt) {
2412 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2413 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2414 }
2415 if (mcasp->rxnumevt) {
2416 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2417 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2418 }
2419
2420 for (i = 0; i < mcasp->num_serializer; i++)
2421 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2422 DAVINCI_MCASP_XRSRCTL_REG(i));
2423
2424 return 0;
2425 }
2426
2427 static int davinci_mcasp_runtime_resume(struct device *dev)
2428 {
2429 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2430 struct davinci_mcasp_context *context = &mcasp->context;
2431 u32 reg;
2432 int i;
2433
2434 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2435 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2436
2437 if (mcasp->txnumevt) {
2438 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2439 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2440 }
2441 if (mcasp->rxnumevt) {
2442 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2443 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2444 }
2445
2446 for (i = 0; i < mcasp->num_serializer; i++)
2447 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2448 context->xrsr_regs[i]);
2449
2450 return 0;
2451 }
2452
2453 #endif
2454
2455 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2456 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2457 davinci_mcasp_runtime_resume,
2458 NULL)
2459 };
2460
2461 static struct platform_driver davinci_mcasp_driver = {
2462 .probe = davinci_mcasp_probe,
2463 .remove = davinci_mcasp_remove,
2464 .driver = {
2465 .name = "davinci-mcasp",
2466 .pm = &davinci_mcasp_pm_ops,
2467 .of_match_table = mcasp_dt_ids,
2468 },
2469 };
2470
2471 module_platform_driver(davinci_mcasp_driver);
2472
2473 MODULE_AUTHOR("Steve Chen");
2474 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2475 MODULE_LICENSE("GPL");
Linux with added FPC-III support