tools/perf/pmu-events/arch/s390/cf_z196/extended.json

   1 [
   2         {
   3                 "Unit": "CPU-M-CF",
   4                 "EventCode": "128",
   5                 "EventName": "L1D_L2_SOURCED_WRITES",
   6                 "BriefDescription": "L1D L2 Sourced Writes",
   7                 "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from the Level-2 cache"
   8         },
   9         {
  10                 "Unit": "CPU-M-CF",
  11                 "EventCode": "129",
  12                 "EventName": "L1I_L2_SOURCED_WRITES",
  13                 "BriefDescription": "L1I L2 Sourced Writes",
  14                 "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 cache"
  15         },
  16         {
  17                 "Unit": "CPU-M-CF",
  18                 "EventCode": "130",
  19                 "EventName": "DTLB1_MISSES",
  20                 "BriefDescription": "DTLB1 Misses",
  21                 "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
  22         },
  23         {
  24                 "Unit": "CPU-M-CF",
  25                 "EventCode": "131",
  26                 "EventName": "ITLB1_MISSES",
  27                 "BriefDescription": "ITLB1 Misses",
  28                 "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
  29         },
  30         {
  31                 "Unit": "CPU-M-CF",
  32                 "EventCode": "133",
  33                 "EventName": "L2C_STORES_SENT",
  34                 "BriefDescription": "L2C Stores Sent",
  35                 "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
  36         },
  37         {
  38                 "Unit": "CPU-M-CF",
  39                 "EventCode": "134",
  40                 "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
  41                 "BriefDescription": "L1D Off-Book L3 Sourced Writes",
  42                 "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
  43         },
  44         {
  45                 "Unit": "CPU-M-CF",
  46                 "EventCode": "135",
  47                 "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
  48                 "BriefDescription": "L1D On-Book L4 Sourced Writes",
  49                 "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
  50         },
  51         {
  52                 "Unit": "CPU-M-CF",
  53                 "EventCode": "136",
  54                 "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
  55                 "BriefDescription": "L1I On-Book L4 Sourced Writes",
  56                 "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
  57         },
  58         {
  59                 "Unit": "CPU-M-CF",
  60                 "EventCode": "137",
  61                 "EventName": "L1D_RO_EXCL_WRITES",
  62                 "BriefDescription": "L1D Read-only Exclusive Writes",
  63                 "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
  64         },
  65         {
  66                 "Unit": "CPU-M-CF",
  67                 "EventCode": "138",
  68                 "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
  69                 "BriefDescription": "L1D Off-Book L4 Sourced Writes",
  70                 "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
  71         },
  72         {
  73                 "Unit": "CPU-M-CF",
  74                 "EventCode": "139",
  75                 "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
  76                 "BriefDescription": "L1I Off-Book L4 Sourced Writes",
  77                 "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
  78         },
  79         {
  80                 "Unit": "CPU-M-CF",
  81                 "EventCode": "140",
  82                 "EventName": "DTLB1_HPAGE_WRITES",
  83                 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
  84                 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
  85         },
  86         {
  87                 "Unit": "CPU-M-CF",
  88                 "EventCode": "141",
  89                 "EventName": "L1D_LMEM_SOURCED_WRITES",
  90                 "BriefDescription": "L1D Local Memory Sourced Writes",
  91                 "PublicDescription": "A directory write to the Level-1 D-Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
  92         },
  93         {
  94                 "Unit": "CPU-M-CF",
  95                 "EventCode": "142",
  96                 "EventName": "L1I_LMEM_SOURCED_WRITES",
  97                 "BriefDescription": "L1I Local Memory Sourced Writes",
  98                 "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
  99         },
 100         {
 101                 "Unit": "CPU-M-CF",
 102                 "EventCode": "143",
 103                 "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
 104                 "BriefDescription": "L1I Off-Book L3 Sourced Writes",
 105                 "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
 106         },
 107         {
 108                 "Unit": "CPU-M-CF",
 109                 "EventCode": "144",
 110                 "EventName": "DTLB1_WRITES",
 111                 "BriefDescription": "DTLB1 Writes",
 112                 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
 113         },
 114         {
 115                 "Unit": "CPU-M-CF",
 116                 "EventCode": "145",
 117                 "EventName": "ITLB1_WRITES",
 118                 "BriefDescription": "ITLB1 Writes",
 119                 "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
 120         },
 121         {
 122                 "Unit": "CPU-M-CF",
 123                 "EventCode": "146",
 124                 "EventName": "TLB2_PTE_WRITES",
 125                 "BriefDescription": "TLB2 PTE Writes",
 126                 "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
 127         },
 128         {
 129                 "Unit": "CPU-M-CF",
 130                 "EventCode": "147",
 131                 "EventName": "TLB2_CRSTE_HPAGE_WRITES",
 132                 "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
 133                 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
 134         },
 135         {
 136                 "Unit": "CPU-M-CF",
 137                 "EventCode": "148",
 138                 "EventName": "TLB2_CRSTE_WRITES",
 139                 "BriefDescription": "TLB2 CRSTE Writes",
 140                 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
 141         },
 142         {
 143                 "Unit": "CPU-M-CF",
 144                 "EventCode": "150",
 145                 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
 146                 "BriefDescription": "L1D On-Chip L3 Sourced Writes",
 147                 "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
 148         },
 149         {
 150                 "Unit": "CPU-M-CF",
 151                 "EventCode": "152",
 152                 "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
 153                 "BriefDescription": "L1D Off-Chip L3 Sourced Writes",
 154                 "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache"
 155         },
 156         {
 157                 "Unit": "CPU-M-CF",
 158                 "EventCode": "153",
 159                 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
 160                 "BriefDescription": "L1I On-Chip L3 Sourced Writes",
 161                 "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
 162         },
 163         {
 164                 "Unit": "CPU-M-CF",
 165                 "EventCode": "155",
 166                 "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
 167                 "BriefDescription": "L1I Off-Chip L3 Sourced Writes",
 168                 "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache"
 169         },
 170 ]