| blob | 162251037219841a360e05149709d44e39239953 |
1 [
2 {
3 "Unit": "CPU-M-CF",
4 "EventCode": "128",
5 "EventName": "DTLB1_MISSES",
6 "BriefDescription": "DTLB1 Misses",
7 "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
8 },
9 {
10 "Unit": "CPU-M-CF",
11 "EventCode": "129",
12 "EventName": "ITLB1_MISSES",
13 "BriefDescription": "ITLB1 Misses",
14 "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
15 },
16 {
17 "Unit": "CPU-M-CF",
18 "EventCode": "130",
19 "EventName": "L1D_L2I_SOURCED_WRITES",
20 "BriefDescription": "L1D L2I Sourced Writes",
21 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
22 },
23 {
24 "Unit": "CPU-M-CF",
25 "EventCode": "131",
26 "EventName": "L1I_L2I_SOURCED_WRITES",
27 "BriefDescription": "L1I L2I Sourced Writes",
28 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
29 },
30 {
31 "Unit": "CPU-M-CF",
32 "EventCode": "132",
33 "EventName": "L1D_L2D_SOURCED_WRITES",
34 "BriefDescription": "L1D L2D Sourced Writes",
35 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
36 },
37 {
38 "Unit": "CPU-M-CF",
39 "EventCode": "133",
40 "EventName": "DTLB1_WRITES",
41 "BriefDescription": "DTLB1 Writes",
42 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
43 },
44 {
45 "Unit": "CPU-M-CF",
46 "EventCode": "135",
47 "EventName": "L1D_LMEM_SOURCED_WRITES",
48 "BriefDescription": "L1D Local Memory Sourced Writes",
49 "PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
50 },
51 {
52 "Unit": "CPU-M-CF",
53 "EventCode": "137",
54 "EventName": "L1I_LMEM_SOURCED_WRITES",
55 "BriefDescription": "L1I Local Memory Sourced Writes",
56 "PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
57 },
58 {
59 "Unit": "CPU-M-CF",
60 "EventCode": "138",
61 "EventName": "L1D_RO_EXCL_WRITES",
62 "BriefDescription": "L1D Read-only Exclusive Writes",
63 "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
64 },
65 {
66 "Unit": "CPU-M-CF",
67 "EventCode": "139",
68 "EventName": "DTLB1_HPAGE_WRITES",
69 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
70 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
71 },
72 {
73 "Unit": "CPU-M-CF",
74 "EventCode": "140",
75 "EventName": "ITLB1_WRITES",
76 "BriefDescription": "ITLB1 Writes",
77 "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
78 },
79 {
80 "Unit": "CPU-M-CF",
81 "EventCode": "141",
82 "EventName": "TLB2_PTE_WRITES",
83 "BriefDescription": "TLB2 PTE Writes",
84 "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
85 },
86 {
87 "Unit": "CPU-M-CF",
88 "EventCode": "142",
89 "EventName": "TLB2_CRSTE_HPAGE_WRITES",
90 "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
91 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
92 },
93 {
94 "Unit": "CPU-M-CF",
95 "EventCode": "143",
96 "EventName": "TLB2_CRSTE_WRITES",
97 "BriefDescription": "TLB2 CRSTE Writes",
98 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
99 },
100 {
101 "Unit": "CPU-M-CF",
102 "EventCode": "144",
103 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
104 "BriefDescription": "L1D On-Chip L3 Sourced Writes",
105 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
106 },
107 {
108 "Unit": "CPU-M-CF",
109 "EventCode": "145",
110 "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
111 "BriefDescription": "L1D Off-Chip L3 Sourced Writes",
112 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
113 },
114 {
115 "Unit": "CPU-M-CF",
116 "EventCode": "146",
117 "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
118 "BriefDescription": "L1D Off-Book L3 Sourced Writes",
119 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
120 },
121 {
122 "Unit": "CPU-M-CF",
123 "EventCode": "147",
124 "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
125 "BriefDescription": "L1D On-Book L4 Sourced Writes",
126 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache"
127 },
128 {
129 "Unit": "CPU-M-CF",
130 "EventCode": "148",
131 "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
132 "BriefDescription": "L1D Off-Book L4 Sourced Writes",
133 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
134 },
135 {
136 "Unit": "CPU-M-CF",
137 "EventCode": "149",
138 "EventName": "TX_NC_TEND",
139 "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
140 "PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode"
141 },
142 {
143 "Unit": "CPU-M-CF",
144 "EventCode": "150",
145 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
146 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
147 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention"
148 },
149 {
150 "Unit": "CPU-M-CF",
151 "EventCode": "151",
152 "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
153 "BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
154 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
155 },
156 {
157 "Unit": "CPU-M-CF",
158 "EventCode": "152",
159 "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
160 "BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
161 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
162 },
163 {
164 "Unit": "CPU-M-CF",
165 "EventCode": "153",
166 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
167 "BriefDescription": "L1I On-Chip L3 Sourced Writes",
168 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
169 },
170 {
171 "Unit": "CPU-M-CF",
172 "EventCode": "154",
173 "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
174 "BriefDescription": "L1I Off-Chip L3 Sourced Writes",
175 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
176 },
177 {
178 "Unit": "CPU-M-CF",
179 "EventCode": "155",
180 "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
181 "BriefDescription": "L1I Off-Book L3 Sourced Writes",
182 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
183 },
184 {
185 "Unit": "CPU-M-CF",
186 "EventCode": "156",
187 "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
188 "BriefDescription": "L1I On-Book L4 Sourced Writes",
189 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache"
190 },
191 {
192 "Unit": "CPU-M-CF",
193 "EventCode": "157",
194 "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
195 "BriefDescription": "L1I Off-Book L4 Sourced Writes",
196 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
197 },
198 {
199 "Unit": "CPU-M-CF",
200 "EventCode": "158",
201 "EventName": "TX_C_TEND",
202 "BriefDescription": "Completed TEND instructions in constrained TX mode",
203 "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
204 },
205 {
206 "Unit": "CPU-M-CF",
207 "EventCode": "159",
208 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
209 "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
210 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
211 },
212 {
213 "Unit": "CPU-M-CF",
214 "EventCode": "160",
215 "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
216 "BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
217 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
218 },
219 {
220 "Unit": "CPU-M-CF",
221 "EventCode": "161",
222 "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
223 "BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
224 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
225 },
226 {
227 "Unit": "CPU-M-CF",
228 "EventCode": "177",
229 "EventName": "TX_NC_TABORT",
230 "BriefDescription": "Aborted transactions in non-constrained TX mode",
231 "PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode"
232 },
233 {
234 "Unit": "CPU-M-CF",
235 "EventCode": "178",
236 "EventName": "TX_C_TABORT_NO_SPECIAL",
237 "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
238 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
239 },
240 {
241 "Unit": "CPU-M-CF",
242 "EventCode": "179",
243 "EventName": "TX_C_TABORT_SPECIAL",
244 "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
245 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
246 },
247 ]