| blob | 778a541463eb6cabcee22804ad26701a7a9a0fb0 |
1 [
2 {
3 "EventCode": "0x28",
4 "UMask": "0x7",
5 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
6 "Counter": "0,1,2,3",
7 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
8 "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
9 "SampleAfterValue": "200003",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
11 },
12 {
13 "EventCode": "0x28",
14 "UMask": "0x18",
15 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
16 "Counter": "0,1,2,3",
17 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
18 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
19 "SampleAfterValue": "200003",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
21 },
22 {
23 "EventCode": "0x28",
24 "UMask": "0x20",
25 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
26 "Counter": "0,1,2,3",
27 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
28 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.",
29 "SampleAfterValue": "200003",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
31 },
32 {
33 "EventCode": "0x28",
34 "UMask": "0x40",
35 "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
36 "Counter": "0,1,2,3",
37 "EventName": "CORE_POWER.THROTTLE",
38 "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
39 "SampleAfterValue": "200003",
40 "CounterHTOff": "0,1,2,3,4,5,6,7"
41 },
42 {
43 "EventCode": "0x32",
44 "UMask": "0x1",
45 "BriefDescription": "Number of PREFETCHNTA instructions executed.",
46 "Counter": "0,1,2,3",
47 "EventName": "SW_PREFETCH_ACCESS.NTA",
48 "SampleAfterValue": "2000003",
49 "CounterHTOff": "0,1,2,3,4,5,6,7"
50 },
51 {
52 "EventCode": "0x32",
53 "UMask": "0x2",
54 "BriefDescription": "Number of PREFETCHT0 instructions executed.",
55 "Counter": "0,1,2,3",
56 "EventName": "SW_PREFETCH_ACCESS.T0",
57 "SampleAfterValue": "2000003",
58 "CounterHTOff": "0,1,2,3,4,5,6,7"
59 },
60 {
61 "EventCode": "0x32",
62 "UMask": "0x4",
63 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
64 "Counter": "0,1,2,3",
65 "EventName": "SW_PREFETCH_ACCESS.T1_T2",
66 "SampleAfterValue": "2000003",
67 "CounterHTOff": "0,1,2,3,4,5,6,7"
68 },
69 {
70 "EventCode": "0x32",
71 "UMask": "0x8",
72 "BriefDescription": "Number of PREFETCHW instructions executed.",
73 "Counter": "0,1,2,3",
74 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
75 "SampleAfterValue": "2000003",
76 "CounterHTOff": "0,1,2,3,4,5,6,7"
77 },
78 {
79 "EventCode": "0xCB",
80 "UMask": "0x1",
81 "BriefDescription": "Number of hardware interrupts received by the processor.",
82 "Counter": "0,1,2,3",
83 "EventName": "HW_INTERRUPTS.RECEIVED",
84 "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
85 "SampleAfterValue": "203",
86 "CounterHTOff": "0,1,2,3,4,5,6,7"
87 },
88 {
89 "EventCode": "0xEF",
90 "UMask": "0x1",
91 "Counter": "0,1,2,3",
92 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
93 "SampleAfterValue": "2000003",
94 "CounterHTOff": "0,1,2,3,4,5,6,7"
95 },
96 {
97 "EventCode": "0xEF",
98 "UMask": "0x2",
99 "Counter": "0,1,2,3",
100 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
101 "SampleAfterValue": "2000003",
102 "CounterHTOff": "0,1,2,3,4,5,6,7"
103 },
104 {
105 "EventCode": "0xEF",
106 "UMask": "0x4",
107 "Counter": "0,1,2,3",
108 "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
109 "SampleAfterValue": "2000003",
110 "CounterHTOff": "0,1,2,3,4,5,6,7"
111 },
112 {
113 "EventCode": "0xEF",
114 "UMask": "0x8",
115 "Counter": "0,1,2,3",
116 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
117 "SampleAfterValue": "2000003",
118 "CounterHTOff": "0,1,2,3,4,5,6,7"
119 },
120 {
121 "EventCode": "0xEF",
122 "UMask": "0x10",
123 "Counter": "0,1,2,3",
124 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
125 "SampleAfterValue": "2000003",
126 "CounterHTOff": "0,1,2,3,4,5,6,7"
127 },
128 {
129 "EventCode": "0xEF",
130 "UMask": "0x20",
131 "Counter": "0,1,2,3",
132 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
133 "SampleAfterValue": "2000003",
134 "CounterHTOff": "0,1,2,3,4,5,6,7"
135 },
136 {
137 "EventCode": "0xEF",
138 "UMask": "0x40",
139 "Counter": "0,1,2,3",
140 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
141 "SampleAfterValue": "2000003",
142 "CounterHTOff": "0,1,2,3,4,5,6,7"
143 },
144 {
145 "EventCode": "0xFE",
146 "UMask": "0x2",
147 "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
148 "Counter": "0,1,2,3",
149 "EventName": "IDI_MISC.WB_UPGRADE",
150 "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
151 "SampleAfterValue": "100003",
152 "CounterHTOff": "0,1,2,3,4,5,6,7"
153 },
154 {
155 "EventCode": "0xFE",
156 "UMask": "0x4",
157 "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
158 "Counter": "0,1,2,3",
159 "EventName": "IDI_MISC.WB_DOWNGRADE",
160 "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
161 "SampleAfterValue": "100003",
162 "CounterHTOff": "0,1,2,3,4,5,6,7"
163 }
164 ]