include/asm-ppc/io.h

   1 #ifdef __KERNEL__
   2 #ifndef _PPC_IO_H
   3 #define _PPC_IO_H
   4
   5 #include <linux/config.h>
   6 #include <linux/string.h>
   7 #include <linux/types.h>
   8
   9 #include <asm/page.h>
  10 #include <asm/byteorder.h>
  11 #include <asm/synch.h>
  12 #include <asm/mmu.h>
  13
  14 #define SIO_CONFIG_RA   0x398
  15 #define SIO_CONFIG_RD   0x399
  16
  17 #define SLOW_DOWN_IO
  18
  19 #define PMAC_ISA_MEM_BASE       0
  20 #define PMAC_PCI_DRAM_OFFSET    0
  21 #define CHRP_ISA_IO_BASE        0xf8000000
  22 #define CHRP_ISA_MEM_BASE       0xf7000000
  23 #define CHRP_PCI_DRAM_OFFSET    0
  24 #define PREP_ISA_IO_BASE        0x80000000
  25 #define PREP_ISA_MEM_BASE       0xc0000000
  26 #define PREP_PCI_DRAM_OFFSET    0x80000000
  27
  28 #if defined(CONFIG_4xx)
  29 #include <asm/ibm4xx.h>
  30 #elif defined(CONFIG_PPC_MPC52xx)
  31 #include <asm/mpc52xx.h>
  32 #elif defined(CONFIG_8xx)
  33 #include <asm/mpc8xx.h>
  34 #elif defined(CONFIG_8260)
  35 #include <asm/mpc8260.h>
  36 #elif defined(CONFIG_83xx)
  37 #include <asm/mpc83xx.h>
  38 #elif defined(CONFIG_85xx)
  39 #include <asm/mpc85xx.h>
  40 #elif defined(CONFIG_APUS)
  41 #define _IO_BASE        0
  42 #define _ISA_MEM_BASE   0
  43 #define PCI_DRAM_OFFSET 0
  44 #else /* Everyone else */
  45 #define _IO_BASE        isa_io_base
  46 #define _ISA_MEM_BASE   isa_mem_base
  47 #define PCI_DRAM_OFFSET pci_dram_offset
  48 #endif /* Platform-dependent I/O */
  49
  50 #define ___IO_BASE ((void __iomem *)_IO_BASE)
  51 extern unsigned long isa_io_base;
  52 extern unsigned long isa_mem_base;
  53 extern unsigned long pci_dram_offset;
  54
  55 /*
  56  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
  57  *
  58  * Read operations have additional twi & isync to make sure the read
  59  * is actually performed (i.e. the data has come back) before we start
  60  * executing any following instructions.
  61  */
  62 extern inline int in_8(const volatile unsigned char __iomem *addr)
  63 {
  64         int ret;
  65
  66         __asm__ __volatile__(
  67                 "lbz%U1%X1 %0,%1;\n"
  68                 "twi 0,%0,0;\n"
  69                 "isync" : "=r" (ret) : "m" (*addr));
  70         return ret;
  71 }
  72
  73 extern inline void out_8(volatile unsigned char __iomem *addr, int val)
  74 {
  75         __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
  76 }
  77
  78 extern inline int in_le16(const volatile unsigned short __iomem *addr)
  79 {
  80         int ret;
  81
  82         __asm__ __volatile__("lhbrx %0,0,%1;\n"
  83                              "twi 0,%0,0;\n"
  84                              "isync" : "=r" (ret) :
  85                               "r" (addr), "m" (*addr));
  86         return ret;
  87 }
  88
  89 extern inline int in_be16(const volatile unsigned short __iomem *addr)
  90 {
  91         int ret;
  92
  93         __asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
  94                              "twi 0,%0,0;\n"
  95                              "isync" : "=r" (ret) : "m" (*addr));
  96         return ret;
  97 }
  98
  99 extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
 100 {
 101         __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
 102                               "r" (val), "r" (addr));
 103 }
 104
 105 extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
 106 {
 107         __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 108 }
 109
 110 extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
 111 {
 112         unsigned ret;
 113
 114         __asm__ __volatile__("lwbrx %0,0,%1;\n"
 115                              "twi 0,%0,0;\n"
 116                              "isync" : "=r" (ret) :
 117                              "r" (addr), "m" (*addr));
 118         return ret;
 119 }
 120
 121 extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
 122 {
 123         unsigned ret;
 124
 125         __asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
 126                              "twi 0,%0,0;\n"
 127                              "isync" : "=r" (ret) : "m" (*addr));
 128         return ret;
 129 }
 130
 131 extern inline void out_le32(volatile unsigned __iomem *addr, int val)
 132 {
 133         __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
 134                              "r" (val), "r" (addr));
 135 }
 136
 137 extern inline void out_be32(volatile unsigned __iomem *addr, int val)
 138 {
 139         __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 140 }
 141 #if defined (CONFIG_8260_PCI9)
 142 #define readb(addr) in_8((volatile u8 *)(addr))
 143 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
 144 #else
 145 static inline __u8 readb(const volatile void __iomem *addr)
 146 {
 147         return in_8(addr);
 148 }
 149 static inline void writeb(__u8 b, volatile void __iomem *addr)
 150 {
 151         out_8(addr, b);
 152 }
 153 #endif
 154
 155 #if defined(CONFIG_APUS)
 156 static inline __u16 readw(const volatile void __iomem *addr)
 157 {
 158         return *(__force volatile __u16 *)(addr);
 159 }
 160 static inline __u32 readl(const volatile void __iomem *addr)
 161 {
 162         return *(__force volatile __u32 *)(addr);
 163 }
 164 static inline void writew(__u16 b, volatile void __iomem *addr)
 165 {
 166         *(__force volatile __u16 *)(addr) = b;
 167 }
 168 static inline void writel(__u32 b, volatile void __iomem *addr)
 169 {
 170         *(__force volatile __u32 *)(addr) = b;
 171 }
 172 #elif defined (CONFIG_8260_PCI9)
 173 /* Use macros if PCI9 workaround enabled */
 174 #define readw(addr) in_le16((volatile u16 *)(addr))
 175 #define readl(addr) in_le32((volatile u32 *)(addr))
 176 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
 177 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
 178 #else
 179 static inline __u16 readw(const volatile void __iomem *addr)
 180 {
 181         return in_le16(addr);
 182 }
 183 static inline __u32 readl(const volatile void __iomem *addr)
 184 {
 185         return in_le32(addr);
 186 }
 187 static inline void writew(__u16 b, volatile void __iomem *addr)
 188 {
 189         out_le16(addr, b);
 190 }
 191 static inline void writel(__u32 b, volatile void __iomem *addr)
 192 {
 193         out_le32(addr, b);
 194 }
 195 #endif /* CONFIG_APUS */
 196
 197 #define readb_relaxed(addr) readb(addr)
 198 #define readw_relaxed(addr) readw(addr)
 199 #define readl_relaxed(addr) readl(addr)
 200
 201 static inline __u8 __raw_readb(const volatile void __iomem *addr)
 202 {
 203         return *(__force volatile __u8 *)(addr);
 204 }
 205 static inline __u16 __raw_readw(const volatile void __iomem *addr)
 206 {
 207         return *(__force volatile __u16 *)(addr);
 208 }
 209 static inline __u32 __raw_readl(const volatile void __iomem *addr)
 210 {
 211         return *(__force volatile __u32 *)(addr);
 212 }
 213 static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
 214 {
 215         *(__force volatile __u8 *)(addr) = b;
 216 }
 217 static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
 218 {
 219         *(__force volatile __u16 *)(addr) = b;
 220 }
 221 static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
 222 {
 223         *(__force volatile __u32 *)(addr) = b;
 224 }
 225
 226 #define mmiowb()
 227
 228 /*
 229  * The insw/outsw/insl/outsl macros don't do byte-swapping.
 230  * They are only used in practice for transferring buffers which
 231  * are arrays of bytes, and byte-swapping is not appropriate in
 232  * that case.  - paulus
 233  */
 234 #define insb(port, buf, ns)     _insb((port)+___IO_BASE, (buf), (ns))
 235 #define outsb(port, buf, ns)    _outsb((port)+___IO_BASE, (buf), (ns))
 236 #define insw(port, buf, ns)     _insw_ns((port)+___IO_BASE, (buf), (ns))
 237 #define outsw(port, buf, ns)    _outsw_ns((port)+___IO_BASE, (buf), (ns))
 238 #define insl(port, buf, nl)     _insl_ns((port)+___IO_BASE, (buf), (nl))
 239 #define outsl(port, buf, nl)    _outsl_ns((port)+___IO_BASE, (buf), (nl))
 240
 241 /*
 242  * On powermacs and 8xx we will get a machine check exception
 243  * if we try to read data from a non-existent I/O port. Because
 244  * the machine check is an asynchronous exception, it isn't
 245  * well-defined which instruction SRR0 will point to when the
 246  * exception occurs.
 247  * With the sequence below (twi; isync; nop), we have found that
 248  * the machine check occurs on one of the three instructions on
 249  * all PPC implementations tested so far.  The twi and isync are
 250  * needed on the 601 (in fact twi; sync works too), the isync and
 251  * nop are needed on 604[e|r], and any of twi, sync or isync will
 252  * work on 603[e], 750, 74xx.
 253  * The twi creates an explicit data dependency on the returned
 254  * value which seems to be needed to make the 601 wait for the
 255  * load to finish.
 256  */
 257
 258 #define __do_in_asm(name, op)                           \
 259 extern __inline__ unsigned int name(unsigned int port)  \
 260 {                                                       \
 261         unsigned int x;                                 \
 262         __asm__ __volatile__(                           \
 263                 "0:"    op "    %0,0,%1\n"              \
 264                 "1:     twi     0,%0,0\n"               \
 265                 "2:     isync\n"                        \
 266                 "3:     nop\n"                          \
 267                 "4:\n"                                  \
 268                 ".section .fixup,\"ax\"\n"              \
 269                 "5:     li      %0,-1\n"                \
 270                 "       b       4b\n"                   \
 271                 ".previous\n"                           \
 272                 ".section __ex_table,\"a\"\n"           \
 273                 "       .align  2\n"                    \
 274                 "       .long   0b,5b\n"                \
 275                 "       .long   1b,5b\n"                \
 276                 "       .long   2b,5b\n"                \
 277                 "       .long   3b,5b\n"                \
 278                 ".previous"                             \
 279                 : "=&r" (x)                             \
 280                 : "r" (port + ___IO_BASE));             \
 281         return x;                                       \
 282 }
 283
 284 #define __do_out_asm(name, op)                          \
 285 extern __inline__ void name(unsigned int val, unsigned int port) \
 286 {                                                       \
 287         __asm__ __volatile__(                           \
 288                 "0:" op " %0,0,%1\n"                    \
 289                 "1:     sync\n"                         \
 290                 "2:\n"                                  \
 291                 ".section __ex_table,\"a\"\n"           \
 292                 "       .align  2\n"                    \
 293                 "       .long   0b,2b\n"                \
 294                 "       .long   1b,2b\n"                \
 295                 ".previous"                             \
 296                 : : "r" (val), "r" (port + ___IO_BASE));        \
 297 }
 298
 299 __do_out_asm(outb, "stbx")
 300 #ifdef CONFIG_APUS
 301 __do_in_asm(inb, "lbzx")
 302 __do_in_asm(inw, "lhz%U1%X1")
 303 __do_in_asm(inl, "lwz%U1%X1")
 304 __do_out_asm(outl,"stw%U0%X0")
 305 __do_out_asm(outw, "sth%U0%X0")
 306 #elif defined (CONFIG_8260_PCI9)
 307 /* in asm cannot be defined if PCI9 workaround is used */
 308 #define inb(port)               in_8((port)+___IO_BASE)
 309 #define inw(port)               in_le16((port)+___IO_BASE)
 310 #define inl(port)               in_le32((port)+___IO_BASE)
 311 __do_out_asm(outw, "sthbrx")
 312 __do_out_asm(outl, "stwbrx")
 313 #else
 314 __do_in_asm(inb, "lbzx")
 315 __do_in_asm(inw, "lhbrx")
 316 __do_in_asm(inl, "lwbrx")
 317 __do_out_asm(outw, "sthbrx")
 318 __do_out_asm(outl, "stwbrx")
 319
 320 #endif
 321
 322 #define inb_p(port)             inb((port))
 323 #define outb_p(val, port)       outb((val), (port))
 324 #define inw_p(port)             inw((port))
 325 #define outw_p(val, port)       outw((val), (port))
 326 #define inl_p(port)             inl((port))
 327 #define outl_p(val, port)       outl((val), (port))
 328
 329 extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
 330 extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
 331 extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
 332 extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
 333 extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
 334 extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
 335 extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
 336 extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
 337 extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
 338 extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
 339
 340 /*
 341  * The *_ns versions below don't do byte-swapping.
 342  * Neither do the standard versions now, these are just here
 343  * for older code.
 344  */
 345 #define insw_ns(port, buf, ns)  _insw_ns((port)+___IO_BASE, (buf), (ns))
 346 #define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
 347 #define insl_ns(port, buf, nl)  _insl_ns((port)+___IO_BASE, (buf), (nl))
 348 #define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
 349
 350
 351 #define IO_SPACE_LIMIT ~0
 352
 353 #if defined (CONFIG_8260_PCI9)
 354 #define memset_io(a,b,c)       memset((void *)(a),(b),(c))
 355 #define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
 356 #define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
 357 #else
 358 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 359 {
 360         memset((void __force *)addr, val, count);
 361 }
 362 static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
 363 {
 364         memcpy(dst, (void __force *) src, count);
 365 }
 366 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 367 {
 368         memcpy((void __force *) dst, src, count);
 369 }
 370 #endif
 371
 372 #define eth_io_copy_and_sum(a,b,c,d)            eth_copy_and_sum((a),(void __force *)(void __iomem *)(b),(c),(d))
 373
 374 /*
 375  * Map in an area of physical address space, for accessing
 376  * I/O devices etc.
 377  */
 378 extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
 379                        unsigned long flags);
 380 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 381 #ifdef CONFIG_44x
 382 extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
 383 #endif
 384 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 385 extern void iounmap(volatile void __iomem *addr);
 386 extern unsigned long iopa(unsigned long addr);
 387 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
 388 extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
 389                              unsigned int size, int flags);
 390
 391 /*
 392  * The PCI bus is inherently Little-Endian.  The PowerPC is being
 393  * run Big-Endian.  Thus all values which cross the [PCI] barrier
 394  * must be endian-adjusted.  Also, the local DRAM has a different
 395  * address from the PCI point of view, thus buffer addresses also
 396  * have to be modified [mapped] appropriately.
 397  */
 398 extern inline unsigned long virt_to_bus(volatile void * address)
 399 {
 400 #ifndef CONFIG_APUS
 401         if (address == (void *)0)
 402                 return 0;
 403         return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
 404 #else
 405         return iopa ((unsigned long) address);
 406 #endif
 407 }
 408
 409 extern inline void * bus_to_virt(unsigned long address)
 410 {
 411 #ifndef CONFIG_APUS
 412         if (address == 0)
 413                 return NULL;
 414         return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
 415 #else
 416         return (void*) mm_ptov (address);
 417 #endif
 418 }
 419
 420 /*
 421  * Change virtual addresses to physical addresses and vv, for
 422  * addresses in the area where the kernel has the RAM mapped.
 423  */
 424 extern inline unsigned long virt_to_phys(volatile void * address)
 425 {
 426 #ifndef CONFIG_APUS
 427         return (unsigned long) address - KERNELBASE;
 428 #else
 429         return iopa ((unsigned long) address);
 430 #endif
 431 }
 432
 433 extern inline void * phys_to_virt(unsigned long address)
 434 {
 435 #ifndef CONFIG_APUS
 436         return (void *) (address + KERNELBASE);
 437 #else
 438         return (void*) mm_ptov (address);
 439 #endif
 440 }
 441
 442 /*
 443  * Change "struct page" to physical address.
 444  */
 445 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 446 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 447
 448 /* Enforce in-order execution of data I/O.
 449  * No distinction between read/write on PPC; use eieio for all three.
 450  */
 451 #define iobarrier_rw() eieio()
 452 #define iobarrier_r()  eieio()
 453 #define iobarrier_w()  eieio()
 454
 455 static inline int check_signature(volatile void __iomem * io_addr,
 456         const unsigned char *signature, int length)
 457 {
 458         int retval = 0;
 459         do {
 460                 if (readb(io_addr) != *signature)
 461                         goto out;
 462                 io_addr++;
 463                 signature++;
 464                 length--;
 465         } while (length);
 466         retval = 1;
 467 out:
 468         return retval;
 469 }
 470
 471 /*
 472  * Here comes the ppc implementation of the IOMAP
 473  * interfaces.
 474  */
 475 static inline unsigned int ioread8(void __iomem *addr)
 476 {
 477         return readb(addr);
 478 }
 479
 480 static inline unsigned int ioread16(void __iomem *addr)
 481 {
 482         return readw(addr);
 483 }
 484
 485 static inline unsigned int ioread32(void __iomem *addr)
 486 {
 487         return readl(addr);
 488 }
 489
 490 static inline void iowrite8(u8 val, void __iomem *addr)
 491 {
 492         writeb(val, addr);
 493 }
 494
 495 static inline void iowrite16(u16 val, void __iomem *addr)
 496 {
 497         writew(val, addr);
 498 }
 499
 500 static inline void iowrite32(u32 val, void __iomem *addr)
 501 {
 502         writel(val, addr);
 503 }
 504
 505 static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
 506 {
 507         _insb(addr, dst, count);
 508 }
 509
 510 static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
 511 {
 512         _insw_ns(addr, dst, count);
 513 }
 514
 515 static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
 516 {
 517         _insl_ns(addr, dst, count);
 518 }
 519
 520 static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
 521 {
 522         _outsb(addr, src, count);
 523 }
 524
 525 static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
 526 {
 527         _outsw_ns(addr, src, count);
 528 }
 529
 530 static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
 531 {
 532         _outsl_ns(addr, src, count);
 533 }
 534
 535 /* Create a virtual mapping cookie for an IO port range */
 536 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 537 extern void ioport_unmap(void __iomem *);
 538
 539 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 540 struct pci_dev;
 541 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 542 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 543
 544 #endif /* _PPC_IO_H */
 545
 546 #ifdef CONFIG_8260_PCI9
 547 #include <asm/mpc8260_pci9.h>
 548 #endif
 549
 550 #ifdef CONFIG_NOT_COHERENT_CACHE
 551
 552 #define dma_cache_inv(_start,_size) \
 553         invalidate_dcache_range(_start, (_start + _size))
 554 #define dma_cache_wback(_start,_size) \
 555         clean_dcache_range(_start, (_start + _size))
 556 #define dma_cache_wback_inv(_start,_size) \
 557         flush_dcache_range(_start, (_start + _size))
 558
 559 #else
 560
 561 #define dma_cache_inv(_start,_size)             do { } while (0)
 562 #define dma_cache_wback(_start,_size)           do { } while (0)
 563 #define dma_cache_wback_inv(_start,_size)       do { } while (0)
 564
 565 #endif
 566
 567 /*
 568  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 569  * access
 570  */
 571 #define xlate_dev_mem_ptr(p)    __va(p)
 572
 573 /*
 574  * Convert a virtual cached pointer to an uncached pointer
 575  */
 576 #define xlate_dev_kmem_ptr(p)   p
 577
 578 #endif /* __KERNEL__ */