arch/alpha/kernel/time.c

   1 /*
   2  *  linux/arch/alpha/kernel/time.c
   3  *
   4  *  Copyright (C) 1991, 1992, 1995, 1999, 2000  Linus Torvalds
   5  *
   6  * This file contains the PC-specific time handling details:
   7  * reading the RTC at bootup, etc..
   8  * 1994-07-02    Alan Modra
   9  *      fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
  10  * 1995-03-26    Markus Kuhn
  11  *      fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
  12  *      precision CMOS clock update
  13  * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
  14  *              "A Kernel Model for Precision Timekeeping" by Dave Mills
  15  * 1997-01-09    Adrian Sun
  16  *      use interval timer if CONFIG_RTC=y
  17  * 1997-10-29    John Bowman (bowman@math.ualberta.ca)
  18  *      fixed tick loss calculation in timer_interrupt
  19  *      (round system clock to nearest tick instead of truncating)
  20  *      fixed algorithm in time_init for getting time from CMOS clock
  21  * 1999-04-16   Thorsten Kranzkowski (dl8bcu@gmx.net)
  22  *      fixed algorithm in do_gettimeofday() for calculating the precise time
  23  *      from processor cycle counter (now taking lost_ticks into account)
  24  * 2000-08-13   Jan-Benedict Glaw <jbglaw@lug-owl.de>
  25  *      Fixed time_init to be aware of epoches != 1900. This prevents
  26  *      booting up in 2048 for me;) Code is stolen from rtc.c.
  27  * 2003-06-03   R. Scott Bailey <scott.bailey@eds.com>
  28  *      Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
  29  */
  30 #include <linux/errno.h>
  31 #include <linux/module.h>
  32 #include <linux/sched.h>
  33 #include <linux/kernel.h>
  34 #include <linux/param.h>
  35 #include <linux/string.h>
  36 #include <linux/mm.h>
  37 #include <linux/delay.h>
  38 #include <linux/ioport.h>
  39 #include <linux/irq.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/init.h>
  42 #include <linux/bcd.h>
  43 #include <linux/profile.h>
  44 #include <linux/irq_work.h>
  45
  46 #include <asm/uaccess.h>
  47 #include <asm/io.h>
  48 #include <asm/hwrpb.h>
  49 #include <asm/rtc.h>
  50
  51 #include <linux/mc146818rtc.h>
  52 #include <linux/time.h>
  53 #include <linux/timex.h>
  54 #include <linux/clocksource.h>
  55
  56 #include "proto.h"
  57 #include "irq_impl.h"
  58
  59 static int set_rtc_mmss(unsigned long);
  60
  61 DEFINE_SPINLOCK(rtc_lock);
  62 EXPORT_SYMBOL(rtc_lock);
  63
  64 #define TICK_SIZE (tick_nsec / 1000)
  65
  66 /*
  67  * Shift amount by which scaled_ticks_per_cycle is scaled.  Shifting
  68  * by 48 gives us 16 bits for HZ while keeping the accuracy good even
  69  * for large CPU clock rates.
  70  */
  71 #define FIX_SHIFT       48
  72
  73 /* lump static variables together for more efficient access: */
  74 static struct {
  75         /* cycle counter last time it got invoked */
  76         __u32 last_time;
  77         /* ticks/cycle * 2^48 */
  78         unsigned long scaled_ticks_per_cycle;
  79         /* partial unused tick */
  80         unsigned long partial_tick;
  81 } state;
  82
  83 unsigned long est_cycle_freq;
  84
  85 #ifdef CONFIG_IRQ_WORK
  86
  87 DEFINE_PER_CPU(u8, irq_work_pending);
  88
  89 #define set_irq_work_pending_flag()  __get_cpu_var(irq_work_pending) = 1
  90 #define test_irq_work_pending()      __get_cpu_var(irq_work_pending)
  91 #define clear_irq_work_pending()     __get_cpu_var(irq_work_pending) = 0
  92
  93 void arch_irq_work_raise(void)
  94 {
  95         set_irq_work_pending_flag();
  96 }
  97
  98 #else  /* CONFIG_IRQ_WORK */
  99
 100 #define test_irq_work_pending()      0
 101 #define clear_irq_work_pending()
 102
 103 #endif /* CONFIG_IRQ_WORK */
 104
 105
 106 static inline __u32 rpcc(void)
 107 {
 108         return __builtin_alpha_rpcc();
 109 }
 110
 111 int update_persistent_clock(struct timespec now)
 112 {
 113         return set_rtc_mmss(now.tv_sec);
 114 }
 115
 116 void read_persistent_clock(struct timespec *ts)
 117 {
 118         unsigned int year, mon, day, hour, min, sec, epoch;
 119
 120         sec = CMOS_READ(RTC_SECONDS);
 121         min = CMOS_READ(RTC_MINUTES);
 122         hour = CMOS_READ(RTC_HOURS);
 123         day = CMOS_READ(RTC_DAY_OF_MONTH);
 124         mon = CMOS_READ(RTC_MONTH);
 125         year = CMOS_READ(RTC_YEAR);
 126
 127         if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 128                 sec = bcd2bin(sec);
 129                 min = bcd2bin(min);
 130                 hour = bcd2bin(hour);
 131                 day = bcd2bin(day);
 132                 mon = bcd2bin(mon);
 133                 year = bcd2bin(year);
 134         }
 135
 136         /* PC-like is standard; used for year >= 70 */
 137         epoch = 1900;
 138         if (year < 20)
 139                 epoch = 2000;
 140         else if (year >= 20 && year < 48)
 141                 /* NT epoch */
 142                 epoch = 1980;
 143         else if (year >= 48 && year < 70)
 144                 /* Digital UNIX epoch */
 145                 epoch = 1952;
 146
 147         printk(KERN_INFO "Using epoch = %d\n", epoch);
 148
 149         if ((year += epoch) < 1970)
 150                 year += 100;
 151
 152         ts->tv_sec = mktime(year, mon, day, hour, min, sec);
 153         ts->tv_nsec = 0;
 154 }
 155
 156
 157
 158 /*
 159  * timer_interrupt() needs to keep up the real-time clock,
 160  * as well as call the "xtime_update()" routine every clocktick
 161  */
 162 irqreturn_t timer_interrupt(int irq, void *dev)
 163 {
 164         unsigned long delta;
 165         __u32 now;
 166         long nticks;
 167
 168 #ifndef CONFIG_SMP
 169         /* Not SMP, do kernel PC profiling here.  */
 170         profile_tick(CPU_PROFILING);
 171 #endif
 172
 173         /*
 174          * Calculate how many ticks have passed since the last update,
 175          * including any previous partial leftover.  Save any resulting
 176          * fraction for the next pass.
 177          */
 178         now = rpcc();
 179         delta = now - state.last_time;
 180         state.last_time = now;
 181         delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
 182         state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
 183         nticks = delta >> FIX_SHIFT;
 184
 185         if (nticks)
 186                 xtime_update(nticks);
 187
 188         if (test_irq_work_pending()) {
 189                 clear_irq_work_pending();
 190                 irq_work_run();
 191         }
 192
 193 #ifndef CONFIG_SMP
 194         while (nticks--)
 195                 update_process_times(user_mode(get_irq_regs()));
 196 #endif
 197
 198         return IRQ_HANDLED;
 199 }
 200
 201 void __init
 202 common_init_rtc(void)
 203 {
 204         unsigned char x;
 205
 206         /* Reset periodic interrupt frequency.  */
 207         x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
 208         /* Test includes known working values on various platforms
 209            where 0x26 is wrong; we refuse to change those. */
 210         if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
 211                 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
 212                 CMOS_WRITE(0x26, RTC_FREQ_SELECT);
 213         }
 214
 215         /* Turn on periodic interrupts.  */
 216         x = CMOS_READ(RTC_CONTROL);
 217         if (!(x & RTC_PIE)) {
 218                 printk("Turning on RTC interrupts.\n");
 219                 x |= RTC_PIE;
 220                 x &= ~(RTC_AIE | RTC_UIE);
 221                 CMOS_WRITE(x, RTC_CONTROL);
 222         }
 223         (void) CMOS_READ(RTC_INTR_FLAGS);
 224
 225         outb(0x36, 0x43);       /* pit counter 0: system timer */
 226         outb(0x00, 0x40);
 227         outb(0x00, 0x40);
 228
 229         outb(0xb6, 0x43);       /* pit counter 2: speaker */
 230         outb(0x31, 0x42);
 231         outb(0x13, 0x42);
 232
 233         init_rtc_irq();
 234 }
 235
 236 unsigned int common_get_rtc_time(struct rtc_time *time)
 237 {
 238         return __get_rtc_time(time);
 239 }
 240
 241 int common_set_rtc_time(struct rtc_time *time)
 242 {
 243         return __set_rtc_time(time);
 244 }
 245
 246 /* Validate a computed cycle counter result against the known bounds for
 247    the given processor core.  There's too much brokenness in the way of
 248    timing hardware for any one method to work everywhere.  :-(
 249
 250    Return 0 if the result cannot be trusted, otherwise return the argument.  */
 251
 252 static unsigned long __init
 253 validate_cc_value(unsigned long cc)
 254 {
 255         static struct bounds {
 256                 unsigned int min, max;
 257         } cpu_hz[] __initdata = {
 258                 [EV3_CPU]    = {   50000000,  200000000 },      /* guess */
 259                 [EV4_CPU]    = {  100000000,  300000000 },
 260                 [LCA4_CPU]   = {  100000000,  300000000 },      /* guess */
 261                 [EV45_CPU]   = {  200000000,  300000000 },
 262                 [EV5_CPU]    = {  250000000,  433000000 },
 263                 [EV56_CPU]   = {  333000000,  667000000 },
 264                 [PCA56_CPU]  = {  400000000,  600000000 },      /* guess */
 265                 [PCA57_CPU]  = {  500000000,  600000000 },      /* guess */
 266                 [EV6_CPU]    = {  466000000,  600000000 },
 267                 [EV67_CPU]   = {  600000000,  750000000 },
 268                 [EV68AL_CPU] = {  750000000,  940000000 },
 269                 [EV68CB_CPU] = { 1000000000, 1333333333 },
 270                 /* None of the following are shipping as of 2001-11-01.  */
 271                 [EV68CX_CPU] = { 1000000000, 1700000000 },      /* guess */
 272                 [EV69_CPU]   = { 1000000000, 1700000000 },      /* guess */
 273                 [EV7_CPU]    = {  800000000, 1400000000 },      /* guess */
 274                 [EV79_CPU]   = { 1000000000, 2000000000 },      /* guess */
 275         };
 276
 277         /* Allow for some drift in the crystal.  10MHz is more than enough.  */
 278         const unsigned int deviation = 10000000;
 279
 280         struct percpu_struct *cpu;
 281         unsigned int index;
 282
 283         cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
 284         index = cpu->type & 0xffffffff;
 285
 286         /* If index out of bounds, no way to validate.  */
 287         if (index >= ARRAY_SIZE(cpu_hz))
 288                 return cc;
 289
 290         /* If index contains no data, no way to validate.  */
 291         if (cpu_hz[index].max == 0)
 292                 return cc;
 293
 294         if (cc < cpu_hz[index].min - deviation
 295             || cc > cpu_hz[index].max + deviation)
 296                 return 0;
 297
 298         return cc;
 299 }
 300
 301
 302 /*
 303  * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
 304  * arch/i386/time.c.
 305  */
 306
 307 #define CALIBRATE_LATCH 0xffff
 308 #define TIMEOUT_COUNT   0x100000
 309
 310 static unsigned long __init
 311 calibrate_cc_with_pit(void)
 312 {
 313         int cc, count = 0;
 314
 315         /* Set the Gate high, disable speaker */
 316         outb((inb(0x61) & ~0x02) | 0x01, 0x61);
 317
 318         /*
 319          * Now let's take care of CTC channel 2
 320          *
 321          * Set the Gate high, program CTC channel 2 for mode 0,
 322          * (interrupt on terminal count mode), binary count,
 323          * load 5 * LATCH count, (LSB and MSB) to begin countdown.
 324          */
 325         outb(0xb0, 0x43);               /* binary, mode 0, LSB/MSB, Ch 2 */
 326         outb(CALIBRATE_LATCH & 0xff, 0x42);     /* LSB of count */
 327         outb(CALIBRATE_LATCH >> 8, 0x42);       /* MSB of count */
 328
 329         cc = rpcc();
 330         do {
 331                 count++;
 332         } while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
 333         cc = rpcc() - cc;
 334
 335         /* Error: ECTCNEVERSET or ECPUTOOFAST.  */
 336         if (count <= 1 || count == TIMEOUT_COUNT)
 337                 return 0;
 338
 339         return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
 340 }
 341
 342 /* The Linux interpretation of the CMOS clock register contents:
 343    When the Update-In-Progress (UIP) flag goes from 1 to 0, the
 344    RTC registers show the second which has precisely just started.
 345    Let's hope other operating systems interpret the RTC the same way.  */
 346
 347 static unsigned long __init
 348 rpcc_after_update_in_progress(void)
 349 {
 350         do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
 351         do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
 352
 353         return rpcc();
 354 }
 355
 356 #ifndef CONFIG_SMP
 357 /* Until and unless we figure out how to get cpu cycle counters
 358    in sync and keep them there, we can't use the rpcc.  */
 359 static cycle_t read_rpcc(struct clocksource *cs)
 360 {
 361         cycle_t ret = (cycle_t)rpcc();
 362         return ret;
 363 }
 364
 365 static struct clocksource clocksource_rpcc = {
 366         .name                   = "rpcc",
 367         .rating                 = 300,
 368         .read                   = read_rpcc,
 369         .mask                   = CLOCKSOURCE_MASK(32),
 370         .flags                  = CLOCK_SOURCE_IS_CONTINUOUS
 371 };
 372
 373 static inline void register_rpcc_clocksource(long cycle_freq)
 374 {
 375         clocksource_register_hz(&clocksource_rpcc, cycle_freq);
 376 }
 377 #else /* !CONFIG_SMP */
 378 static inline void register_rpcc_clocksource(long cycle_freq)
 379 {
 380 }
 381 #endif /* !CONFIG_SMP */
 382
 383 void __init
 384 time_init(void)
 385 {
 386         unsigned int cc1, cc2;
 387         unsigned long cycle_freq, tolerance;
 388         long diff;
 389
 390         /* Calibrate CPU clock -- attempt #1.  */
 391         if (!est_cycle_freq)
 392                 est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
 393
 394         cc1 = rpcc();
 395
 396         /* Calibrate CPU clock -- attempt #2.  */
 397         if (!est_cycle_freq) {
 398                 cc1 = rpcc_after_update_in_progress();
 399                 cc2 = rpcc_after_update_in_progress();
 400                 est_cycle_freq = validate_cc_value(cc2 - cc1);
 401                 cc1 = cc2;
 402         }
 403
 404         cycle_freq = hwrpb->cycle_freq;
 405         if (est_cycle_freq) {
 406                 /* If the given value is within 250 PPM of what we calculated,
 407                    accept it.  Otherwise, use what we found.  */
 408                 tolerance = cycle_freq / 4000;
 409                 diff = cycle_freq - est_cycle_freq;
 410                 if (diff < 0)
 411                         diff = -diff;
 412                 if ((unsigned long)diff > tolerance) {
 413                         cycle_freq = est_cycle_freq;
 414                         printk("HWRPB cycle frequency bogus.  "
 415                                "Estimated %lu Hz\n", cycle_freq);
 416                 } else {
 417                         est_cycle_freq = 0;
 418                 }
 419         } else if (! validate_cc_value (cycle_freq)) {
 420                 printk("HWRPB cycle frequency bogus, "
 421                        "and unable to estimate a proper value!\n");
 422         }
 423
 424         /* From John Bowman <bowman@math.ualberta.ca>: allow the values
 425            to settle, as the Update-In-Progress bit going low isn't good
 426            enough on some hardware.  2ms is our guess; we haven't found
 427            bogomips yet, but this is close on a 500Mhz box.  */
 428         __delay(1000000);
 429
 430
 431         if (HZ > (1<<16)) {
 432                 extern void __you_loose (void);
 433                 __you_loose();
 434         }
 435
 436         register_rpcc_clocksource(cycle_freq);
 437
 438         state.last_time = cc1;
 439         state.scaled_ticks_per_cycle
 440                 = ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
 441         state.partial_tick = 0L;
 442
 443         /* Startup the timer source. */
 444         alpha_mv.init_rtc();
 445 }
 446
 447 /*
 448  * In order to set the CMOS clock precisely, set_rtc_mmss has to be
 449  * called 500 ms after the second nowtime has started, because when
 450  * nowtime is written into the registers of the CMOS clock, it will
 451  * jump to the next second precisely 500 ms later. Check the Motorola
 452  * MC146818A or Dallas DS12887 data sheet for details.
 453  *
 454  * BUG: This routine does not handle hour overflow properly; it just
 455  *      sets the minutes. Usually you won't notice until after reboot!
 456  */
 457
 458
 459 static int
 460 set_rtc_mmss(unsigned long nowtime)
 461 {
 462         int retval = 0;
 463         int real_seconds, real_minutes, cmos_minutes;
 464         unsigned char save_control, save_freq_select;
 465
 466         /* irq are locally disabled here */
 467         spin_lock(&rtc_lock);
 468         /* Tell the clock it's being set */
 469         save_control = CMOS_READ(RTC_CONTROL);
 470         CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
 471
 472         /* Stop and reset prescaler */
 473         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
 474         CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
 475
 476         cmos_minutes = CMOS_READ(RTC_MINUTES);
 477         if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
 478                 cmos_minutes = bcd2bin(cmos_minutes);
 479
 480         /*
 481          * since we're only adjusting minutes and seconds,
 482          * don't interfere with hour overflow. This avoids
 483          * messing with unknown time zones but requires your
 484          * RTC not to be off by more than 15 minutes
 485          */
 486         real_seconds = nowtime % 60;
 487         real_minutes = nowtime / 60;
 488         if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
 489                 /* correct for half hour time zone */
 490                 real_minutes += 30;
 491         }
 492         real_minutes %= 60;
 493
 494         if (abs(real_minutes - cmos_minutes) < 30) {
 495                 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 496                         real_seconds = bin2bcd(real_seconds);
 497                         real_minutes = bin2bcd(real_minutes);
 498                 }
 499                 CMOS_WRITE(real_seconds,RTC_SECONDS);
 500                 CMOS_WRITE(real_minutes,RTC_MINUTES);
 501         } else {
 502                 printk_once(KERN_NOTICE
 503                        "set_rtc_mmss: can't update from %d to %d\n",
 504                        cmos_minutes, real_minutes);
 505                 retval = -1;
 506         }
 507
 508         /* The following flags have to be released exactly in this order,
 509          * otherwise the DS12887 (popular MC146818A clone with integrated
 510          * battery and quartz) will not reset the oscillator and will not
 511          * update precisely 500 ms later. You won't find this mentioned in
 512          * the Dallas Semiconductor data sheets, but who believes data
 513          * sheets anyway ...                           -- Markus Kuhn
 514          */
 515         CMOS_WRITE(save_control, RTC_CONTROL);
 516         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
 517         spin_unlock(&rtc_lock);
 518
 519         return retval;
 520 }