| blob | 99e1ce978cf90df8f2a0bfd6b1612492cd76fed2 |
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_SUPPORTS_ATOMIC_RMW
9 select ARCH_WANT_IPC_PARSE_VERSION
10 select BUILDTIME_EXTABLE_SORT if MMU
11 select CLONE_BACKWARDS
12 select CPU_PM if (SUSPEND || CPU_IDLE)
13 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
14 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
15 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
16 select GENERIC_IDLE_POLL_SETUP
17 select GENERIC_IRQ_PROBE
18 select GENERIC_IRQ_SHOW
19 select GENERIC_PCI_IOMAP
20 select GENERIC_SCHED_CLOCK
21 select GENERIC_SMP_IDLE_THREAD
22 select GENERIC_STRNCPY_FROM_USER
23 select GENERIC_STRNLEN_USER
24 select HARDIRQS_SW_RESEND
25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_KGDB
27 select HAVE_ARCH_SECCOMP_FILTER
28 select HAVE_ARCH_TRACEHOOK
29 select HAVE_BPF_JIT
30 select HAVE_CONTEXT_TRACKING
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_DEBUG_KMEMLEAK
33 select HAVE_DMA_API_DEBUG
34 select HAVE_DMA_ATTRS
35 select HAVE_DMA_CONTIGUOUS if MMU
36 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
37 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
38 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
39 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
40 select HAVE_GENERIC_DMA_COHERENT
41 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
42 select HAVE_IDE if PCI || ISA || PCMCIA
43 select HAVE_IRQ_TIME_ACCOUNTING
44 select HAVE_KERNEL_GZIP
45 select HAVE_KERNEL_LZ4
46 select HAVE_KERNEL_LZMA
47 select HAVE_KERNEL_LZO
48 select HAVE_KERNEL_XZ
49 select HAVE_KPROBES if !XIP_KERNEL
50 select HAVE_KRETPROBES if (HAVE_KPROBES)
51 select HAVE_MEMBLOCK
52 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
53 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
54 select HAVE_PERF_EVENTS
55 select HAVE_REGS_AND_STACK_ACCESS_API
56 select HAVE_SYSCALL_TRACEPOINTS
57 select HAVE_UID16
58 select IRQ_FORCED_THREADING
59 select KTIME_SCALAR
60 select MODULES_USE_ELF_REL
61 select OLD_SIGACTION
62 select OLD_SIGSUSPEND3
63 select PERF_USE_VMALLOC
64 select RTC_LIB
65 select SYS_SUPPORTS_APM_EMULATION
66 # Above selects are sorted alphabetically; please add new ones
67 # according to that. Thanks.
68 help
69 The ARM series is a line of low-power-consumption RISC chip designs
70 licensed by ARM Ltd and targeted at embedded applications and
71 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
72 manufactured, but legacy ARM-based PC hardware remains popular in
73 Europe. There is an ARM Linux project with a web page at
74 <http://www.arm.linux.org.uk/>.
76 config ARM_HAS_SG_CHAIN
77 bool
79 config NEED_SG_DMA_LENGTH
80 bool
82 config ARM_DMA_USE_IOMMU
83 bool
84 select ARM_HAS_SG_CHAIN
85 select NEED_SG_DMA_LENGTH
87 if ARM_DMA_USE_IOMMU
89 config ARM_DMA_IOMMU_ALIGNMENT
90 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
91 range 4 9
92 default 8
93 help
94 DMA mapping framework by default aligns all buffers to the smallest
95 PAGE_SIZE order which is greater than or equal to the requested buffer
96 size. This works well for buffers up to a few hundreds kilobytes, but
97 for larger buffers it just a waste of address space. Drivers which has
98 relatively small addressing window (like 64Mib) might run out of
99 virtual space with just a few allocations.
101 With this parameter you can specify the maximum PAGE_SIZE order for
102 DMA IOMMU buffers. Larger buffers will be aligned only to this
103 specified order. The order is expressed as a power of two multiplied
104 by the PAGE_SIZE.
106 endif
108 config HAVE_PWM
109 bool
111 config MIGHT_HAVE_PCI
112 bool
114 config SYS_SUPPORTS_APM_EMULATION
115 bool
117 config HAVE_TCM
118 bool
119 select GENERIC_ALLOCATOR
121 config HAVE_PROC_CPU
122 bool
124 config NO_IOPORT
125 bool
127 config EISA
128 bool
129 ---help---
130 The Extended Industry Standard Architecture (EISA) bus was
131 developed as an open alternative to the IBM MicroChannel bus.
133 The EISA bus provided some of the features of the IBM MicroChannel
134 bus while maintaining backward compatibility with cards made for
135 the older ISA bus. The EISA bus saw limited use between 1988 and
136 1995 when it was made obsolete by the PCI bus.
138 Say Y here if you are building a kernel for an EISA-based machine.
140 Otherwise, say N.
142 config SBUS
143 bool
145 config STACKTRACE_SUPPORT
146 bool
147 default y
149 config HAVE_LATENCYTOP_SUPPORT
150 bool
151 depends on !SMP
152 default y
154 config LOCKDEP_SUPPORT
155 bool
156 default y
158 config TRACE_IRQFLAGS_SUPPORT
159 bool
160 default y
162 config RWSEM_GENERIC_SPINLOCK
163 bool
164 default y
166 config RWSEM_XCHGADD_ALGORITHM
167 bool
169 config ARCH_HAS_ILOG2_U32
170 bool
172 config ARCH_HAS_ILOG2_U64
173 bool
175 config ARCH_HAS_CPUFREQ
176 bool
177 help
178 Internal node to signify that the ARCH has CPUFREQ support
179 and that the relevant menu configurations are displayed for
180 it.
182 config ARCH_HAS_BANDGAP
183 bool
185 config GENERIC_HWEIGHT
186 bool
187 default y
189 config GENERIC_CALIBRATE_DELAY
190 bool
191 default y
193 config ARCH_MAY_HAVE_PC_FDC
194 bool
196 config ZONE_DMA
197 bool
199 config NEED_DMA_MAP_STATE
200 def_bool y
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
203 bool
205 config GENERIC_ISA_DMA
206 bool
208 config FIQ
209 bool
211 config NEED_RET_TO_USER
212 bool
214 config ARCH_MTD_XIP
215 bool
217 config VECTORS_BASE
218 hex
219 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220 default DRAM_BASE if REMAP_VECTORS_TO_RAM
221 default 0x00000000
222 help
223 The base address of exception vectors. This must be two pages
224 in size.
226 config ARM_PATCH_PHYS_VIRT
227 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 default y
229 depends on !XIP_KERNEL && MMU
230 depends on !ARCH_REALVIEW || !SPARSEMEM
231 help
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_GPIO_H
244 bool
245 help
246 Select this when mach/gpio.h is required to provide special
247 definitions for this platform. The need for mach/gpio.h should
248 be avoided when possible.
250 config NEED_MACH_IO_H
251 bool
252 help
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
258 bool
259 help
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
264 config PHYS_OFFSET
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
267 default DRAM_BASE if !MMU
268 help
269 Please provide the physical address corresponding to the
270 location of main memory in your system.
272 config GENERIC_BUG
273 def_bool y
274 depends on BUG
276 source "init/Kconfig"
278 source "kernel/Kconfig.freezer"
280 menu "System Type"
282 config MMU
283 bool "MMU-based Paged Memory Management Support"
284 default y
285 help
286 Select if you want MMU-based virtualised addressing space
287 support by paged memory management. If unsure, say 'Y'.
289 #
290 # The "ARM system type" choice list is ordered alphabetically by option
291 # text. Please add new entries in the option alphabetic order.
292 #
293 choice
294 prompt "ARM system type"
295 default ARCH_VERSATILE if !MMU
296 default ARCH_MULTIPLATFORM if MMU
298 config ARCH_MULTIPLATFORM
299 bool "Allow multiple platforms to be selected"
300 depends on MMU
301 select ARM_PATCH_PHYS_VIRT
302 select AUTO_ZRELADDR
303 select COMMON_CLK
304 select MULTI_IRQ_HANDLER
305 select SPARSE_IRQ
306 select USE_OF
308 config ARCH_INTEGRATOR
309 bool "ARM Ltd. Integrator family"
310 select ARCH_HAS_CPUFREQ
311 select ARM_AMBA
312 select COMMON_CLK
313 select COMMON_CLK_VERSATILE
314 select GENERIC_CLOCKEVENTS
315 select HAVE_TCM
316 select ICST
317 select MULTI_IRQ_HANDLER
318 select NEED_MACH_MEMORY_H
319 select PLAT_VERSATILE
320 select SPARSE_IRQ
321 select VERSATILE_FPGA_IRQ
322 help
323 Support for ARM's Integrator platform.
325 config ARCH_REALVIEW
326 bool "ARM Ltd. RealView family"
327 select ARCH_WANT_OPTIONAL_GPIOLIB
328 select ARM_AMBA
329 select ARM_TIMER_SP804
330 select COMMON_CLK
331 select COMMON_CLK_VERSATILE
332 select GENERIC_CLOCKEVENTS
333 select GPIO_PL061 if GPIOLIB
334 select ICST
335 select NEED_MACH_MEMORY_H
336 select PLAT_VERSATILE
337 select PLAT_VERSATILE_CLCD
338 help
339 This enables support for ARM Ltd RealView boards.
341 config ARCH_VERSATILE
342 bool "ARM Ltd. Versatile family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_AMBA
345 select ARM_TIMER_SP804
346 select ARM_VIC
347 select CLKDEV_LOOKUP
348 select GENERIC_CLOCKEVENTS
349 select HAVE_MACH_CLKDEV
350 select ICST
351 select PLAT_VERSATILE
352 select PLAT_VERSATILE_CLCD
353 select PLAT_VERSATILE_CLOCK
354 select VERSATILE_FPGA_IRQ
355 help
356 This enables support for ARM Ltd Versatile board.
358 config ARCH_AT91
359 bool "Atmel AT91"
360 select ARCH_REQUIRE_GPIOLIB
361 select CLKDEV_LOOKUP
362 select HAVE_CLK
363 select IRQ_DOMAIN
364 select NEED_MACH_GPIO_H
365 select NEED_MACH_IO_H if PCCARD
366 select PINCTRL
367 select PINCTRL_AT91 if USE_OF
368 help
369 This enables support for systems based on Atmel
370 AT91RM9200 and AT91SAM9* processors.
372 config ARCH_CLPS711X
373 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
374 select ARCH_REQUIRE_GPIOLIB
375 select AUTO_ZRELADDR
376 select CLKDEV_LOOKUP
377 select CLKSRC_MMIO
378 select COMMON_CLK
379 select CPU_ARM720T
380 select GENERIC_CLOCKEVENTS
381 select MFD_SYSCON
382 select MULTI_IRQ_HANDLER
383 select SPARSE_IRQ
384 help
385 Support for Cirrus Logic 711x/721x/731x based boards.
387 config ARCH_GEMINI
388 bool "Cortina Systems Gemini"
389 select ARCH_REQUIRE_GPIOLIB
390 select ARCH_USES_GETTIMEOFFSET
391 select CPU_FA526
392 select NEED_MACH_GPIO_H
393 help
394 Support for the Cortina Systems Gemini family SoCs
396 config ARCH_EBSA110
397 bool "EBSA-110"
398 select ARCH_USES_GETTIMEOFFSET
399 select CPU_SA110
400 select ISA
401 select NEED_MACH_IO_H
402 select NEED_MACH_MEMORY_H
403 select NO_IOPORT
404 help
405 This is an evaluation board for the StrongARM processor available
406 from Digital. It has limited hardware on-board, including an
407 Ethernet interface, two PCMCIA sockets, two serial ports and a
408 parallel port.
410 config ARCH_EP93XX
411 bool "EP93xx-based"
412 select ARCH_HAS_HOLES_MEMORYMODEL
413 select ARCH_REQUIRE_GPIOLIB
414 select ARCH_USES_GETTIMEOFFSET
415 select ARM_AMBA
416 select ARM_VIC
417 select CLKDEV_LOOKUP
418 select CPU_ARM920T
419 select NEED_MACH_MEMORY_H
420 help
421 This enables support for the Cirrus EP93xx series of CPUs.
423 config ARCH_FOOTBRIDGE
424 bool "FootBridge"
425 select CPU_SA110
426 select FOOTBRIDGE
427 select GENERIC_CLOCKEVENTS
428 select HAVE_IDE
429 select NEED_MACH_IO_H if !MMU
430 select NEED_MACH_MEMORY_H
431 help
432 Support for systems based on the DC21285 companion chip
433 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
435 config ARCH_NETX
436 bool "Hilscher NetX based"
437 select ARM_VIC
438 select CLKSRC_MMIO
439 select CPU_ARM926T
440 select GENERIC_CLOCKEVENTS
441 help
442 This enables support for systems based on the Hilscher NetX Soc
444 config ARCH_IOP13XX
445 bool "IOP13xx-based"
446 depends on MMU
447 select CPU_XSC3
448 select NEED_MACH_MEMORY_H
449 select NEED_RET_TO_USER
450 select PCI
451 select PLAT_IOP
452 select VMSPLIT_1G
453 help
454 Support for Intel's IOP13XX (XScale) family of processors.
456 config ARCH_IOP32X
457 bool "IOP32x-based"
458 depends on MMU
459 select ARCH_REQUIRE_GPIOLIB
460 select CPU_XSCALE
461 select NEED_MACH_GPIO_H
462 select NEED_RET_TO_USER
463 select PCI
464 select PLAT_IOP
465 help
466 Support for Intel's 80219 and IOP32X (XScale) family of
467 processors.
469 config ARCH_IOP33X
470 bool "IOP33x-based"
471 depends on MMU
472 select ARCH_REQUIRE_GPIOLIB
473 select CPU_XSCALE
474 select NEED_MACH_GPIO_H
475 select NEED_RET_TO_USER
476 select PCI
477 select PLAT_IOP
478 help
479 Support for Intel's IOP33X (XScale) family of processors.
481 config ARCH_IXP4XX
482 bool "IXP4xx-based"
483 depends on MMU
484 select ARCH_HAS_DMA_SET_COHERENT_MASK
485 select ARCH_REQUIRE_GPIOLIB
486 select CLKSRC_MMIO
487 select CPU_XSCALE
488 select DMABOUNCE if PCI
489 select GENERIC_CLOCKEVENTS
490 select MIGHT_HAVE_PCI
491 select NEED_MACH_IO_H
492 select USB_EHCI_BIG_ENDIAN_DESC
493 select USB_EHCI_BIG_ENDIAN_MMIO
494 help
495 Support for Intel's IXP4XX (XScale) family of processors.
497 config ARCH_DOVE
498 bool "Marvell Dove"
499 select ARCH_REQUIRE_GPIOLIB
500 select CPU_PJ4
501 select GENERIC_CLOCKEVENTS
502 select MIGHT_HAVE_PCI
503 select MVEBU_MBUS
504 select PINCTRL
505 select PINCTRL_DOVE
506 select PLAT_ORION_LEGACY
507 select USB_ARCH_HAS_EHCI
508 help
509 Support for the Marvell Dove SoC 88AP510
511 config ARCH_KIRKWOOD
512 bool "Marvell Kirkwood"
513 select ARCH_HAS_CPUFREQ
514 select ARCH_REQUIRE_GPIOLIB
515 select CPU_FEROCEON
516 select GENERIC_CLOCKEVENTS
517 select MVEBU_MBUS
518 select PCI
519 select PCI_QUIRKS
520 select PINCTRL
521 select PINCTRL_KIRKWOOD
522 select PLAT_ORION_LEGACY
523 help
524 Support for the following Marvell Kirkwood series SoCs:
525 88F6180, 88F6192 and 88F6281.
527 config ARCH_MV78XX0
528 bool "Marvell MV78xx0"
529 select ARCH_REQUIRE_GPIOLIB
530 select CPU_FEROCEON
531 select GENERIC_CLOCKEVENTS
532 select MVEBU_MBUS
533 select PCI
534 select PLAT_ORION_LEGACY
535 help
536 Support for the following Marvell MV78xx0 series SoCs:
537 MV781x0, MV782x0.
539 config ARCH_ORION5X
540 bool "Marvell Orion"
541 depends on MMU
542 select ARCH_REQUIRE_GPIOLIB
543 select CPU_FEROCEON
544 select GENERIC_CLOCKEVENTS
545 select MVEBU_MBUS
546 select PCI
547 select PLAT_ORION_LEGACY
548 help
549 Support for the following Marvell Orion 5x series SoCs:
550 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
551 Orion-2 (5281), Orion-1-90 (6183).
553 config ARCH_MMP
554 bool "Marvell PXA168/910/MMP2"
555 depends on MMU
556 select ARCH_REQUIRE_GPIOLIB
557 select CLKDEV_LOOKUP
558 select GENERIC_ALLOCATOR
559 select GENERIC_CLOCKEVENTS
560 select GPIO_PXA
561 select IRQ_DOMAIN
562 select MULTI_IRQ_HANDLER
563 select NEED_MACH_GPIO_H
564 select PINCTRL
565 select PLAT_PXA
566 select SPARSE_IRQ
567 help
568 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
570 config ARCH_KS8695
571 bool "Micrel/Kendin KS8695"
572 select ARCH_REQUIRE_GPIOLIB
573 select CLKSRC_MMIO
574 select CPU_ARM922T
575 select GENERIC_CLOCKEVENTS
576 select NEED_MACH_MEMORY_H
577 help
578 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
579 System-on-Chip devices.
581 config ARCH_W90X900
582 bool "Nuvoton W90X900 CPU"
583 select ARCH_REQUIRE_GPIOLIB
584 select CLKDEV_LOOKUP
585 select CLKSRC_MMIO
586 select CPU_ARM926T
587 select GENERIC_CLOCKEVENTS
588 help
589 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
590 At present, the w90x900 has been renamed nuc900, regarding
591 the ARM series product line, you can login the following
592 link address to know more.
594 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
595 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
597 config ARCH_LPC32XX
598 bool "NXP LPC32XX"
599 select ARCH_REQUIRE_GPIOLIB
600 select ARM_AMBA
601 select CLKDEV_LOOKUP
602 select CLKSRC_MMIO
603 select CPU_ARM926T
604 select GENERIC_CLOCKEVENTS
605 select HAVE_IDE
606 select HAVE_PWM
607 select USB_ARCH_HAS_OHCI
608 select USE_OF
609 help
610 Support for the NXP LPC32XX family of processors
612 config ARCH_PXA
613 bool "PXA2xx/PXA3xx-based"
614 depends on MMU
615 select ARCH_HAS_CPUFREQ
616 select ARCH_MTD_XIP
617 select ARCH_REQUIRE_GPIOLIB
618 select ARM_CPU_SUSPEND if PM
619 select AUTO_ZRELADDR
620 select CLKDEV_LOOKUP
621 select CLKSRC_MMIO
622 select GENERIC_CLOCKEVENTS
623 select GPIO_PXA
624 select HAVE_IDE
625 select MULTI_IRQ_HANDLER
626 select NEED_MACH_GPIO_H
627 select PLAT_PXA
628 select SPARSE_IRQ
629 help
630 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
632 config ARCH_MSM
633 bool "Qualcomm MSM"
634 select ARCH_REQUIRE_GPIOLIB
635 select CLKDEV_LOOKUP
636 select CLKSRC_OF if OF
637 select COMMON_CLK
638 select GENERIC_CLOCKEVENTS
639 help
640 Support for Qualcomm MSM/QSD based systems. This runs on the
641 apps processor of the MSM/QSD and depends on a shared memory
642 interface to the modem processor which runs the baseband
643 stack and controls some vital subsystems
644 (clock and power control, etc).
646 config ARCH_SHMOBILE
647 bool "Renesas SH-Mobile / R-Mobile"
648 select ARM_PATCH_PHYS_VIRT
649 select CLKDEV_LOOKUP
650 select GENERIC_CLOCKEVENTS
651 select HAVE_ARM_SCU if SMP
652 select HAVE_ARM_TWD if SMP
653 select HAVE_CLK
654 select HAVE_MACH_CLKDEV
655 select HAVE_SMP
656 select MIGHT_HAVE_CACHE_L2X0
657 select MULTI_IRQ_HANDLER
658 select NO_IOPORT
659 select PINCTRL
660 select PM_GENERIC_DOMAINS if PM
661 select SPARSE_IRQ
662 help
663 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
665 config ARCH_RPC
666 bool "RiscPC"
667 select ARCH_ACORN
668 select ARCH_MAY_HAVE_PC_FDC
669 select ARCH_SPARSEMEM_ENABLE
670 select ARCH_USES_GETTIMEOFFSET
671 select FIQ
672 select HAVE_IDE
673 select HAVE_PATA_PLATFORM
674 select ISA_DMA_API
675 select NEED_MACH_IO_H
676 select NEED_MACH_MEMORY_H
677 select NO_IOPORT
678 select VIRT_TO_BUS
679 help
680 On the Acorn Risc-PC, Linux can support the internal IDE disk and
681 CD-ROM interface, serial and parallel port, and the floppy drive.
683 config ARCH_SA1100
684 bool "SA1100-based"
685 select ARCH_HAS_CPUFREQ
686 select ARCH_MTD_XIP
687 select ARCH_REQUIRE_GPIOLIB
688 select ARCH_SPARSEMEM_ENABLE
689 select CLKDEV_LOOKUP
690 select CLKSRC_MMIO
691 select CPU_FREQ
692 select CPU_SA1100
693 select GENERIC_CLOCKEVENTS
694 select HAVE_IDE
695 select ISA
696 select NEED_MACH_GPIO_H
697 select NEED_MACH_MEMORY_H
698 select SPARSE_IRQ
699 help
700 Support for StrongARM 11x0 based boards.
702 config ARCH_S3C24XX
703 bool "Samsung S3C24XX SoCs"
704 select ARCH_HAS_CPUFREQ
705 select ARCH_REQUIRE_GPIOLIB
706 select CLKDEV_LOOKUP
707 select CLKSRC_SAMSUNG_PWM
708 select GENERIC_CLOCKEVENTS
709 select GPIO_SAMSUNG
710 select HAVE_CLK
711 select HAVE_S3C2410_I2C if I2C
712 select HAVE_S3C2410_WATCHDOG if WATCHDOG
713 select HAVE_S3C_RTC if RTC_CLASS
714 select MULTI_IRQ_HANDLER
715 select NEED_MACH_GPIO_H
716 select NEED_MACH_IO_H
717 select SAMSUNG_ATAGS
718 help
719 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
720 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
721 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
722 Samsung SMDK2410 development board (and derivatives).
724 config ARCH_S3C64XX
725 bool "Samsung S3C64XX"
726 select ARCH_HAS_CPUFREQ
727 select ARCH_REQUIRE_GPIOLIB
728 select ARM_VIC
729 select CLKDEV_LOOKUP
730 select CLKSRC_SAMSUNG_PWM
731 select CPU_V6
732 select GENERIC_CLOCKEVENTS
733 select GPIO_SAMSUNG
734 select HAVE_CLK
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 select HAVE_TCM
738 select NEED_MACH_GPIO_H
739 select NO_IOPORT
740 select PLAT_SAMSUNG
741 select S3C_DEV_NAND
742 select S3C_GPIO_TRACK
743 select SAMSUNG_ATAGS
744 select SAMSUNG_CLKSRC
745 select SAMSUNG_GPIOLIB_4BIT
746 select SAMSUNG_WDT_RESET
747 select USB_ARCH_HAS_OHCI
748 help
749 Samsung S3C64XX series based systems
751 config ARCH_S5P64X0
752 bool "Samsung S5P6440 S5P6450"
753 select CLKDEV_LOOKUP
754 select CLKSRC_SAMSUNG_PWM
755 select CPU_V6
756 select GENERIC_CLOCKEVENTS
757 select GPIO_SAMSUNG
758 select HAVE_CLK
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
761 select HAVE_S3C_RTC if RTC_CLASS
762 select NEED_MACH_GPIO_H
763 select SAMSUNG_ATAGS
764 select SAMSUNG_WDT_RESET
765 help
766 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
767 SMDK6450.
769 config ARCH_S5PC100
770 bool "Samsung S5PC100"
771 select ARCH_REQUIRE_GPIOLIB
772 select CLKDEV_LOOKUP
773 select CLKSRC_SAMSUNG_PWM
774 select CPU_V7
775 select GENERIC_CLOCKEVENTS
776 select GPIO_SAMSUNG
777 select HAVE_CLK
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H
782 select SAMSUNG_ATAGS
783 select SAMSUNG_WDT_RESET
784 help
785 Samsung S5PC100 series based systems
787 config ARCH_S5PV210
788 bool "Samsung S5PV210/S5PC110"
789 select ARCH_HAS_CPUFREQ
790 select ARCH_HAS_HOLES_MEMORYMODEL
791 select ARCH_SPARSEMEM_ENABLE
792 select CLKDEV_LOOKUP
793 select CLKSRC_SAMSUNG_PWM
794 select CPU_V7
795 select GENERIC_CLOCKEVENTS
796 select GPIO_SAMSUNG
797 select HAVE_CLK
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select HAVE_S3C_RTC if RTC_CLASS
801 select NEED_MACH_GPIO_H
802 select NEED_MACH_MEMORY_H
803 select SAMSUNG_ATAGS
804 help
805 Samsung S5PV210/S5PC110 series based systems
807 config ARCH_EXYNOS
808 bool "Samsung EXYNOS"
809 select ARCH_HAS_CPUFREQ
810 select ARCH_HAS_HOLES_MEMORYMODEL
811 select ARCH_REQUIRE_GPIOLIB
812 select ARCH_SPARSEMEM_ENABLE
813 select ARM_GIC
814 select CLKDEV_LOOKUP
815 select COMMON_CLK
816 select CPU_V7
817 select GENERIC_CLOCKEVENTS
818 select HAVE_CLK
819 select HAVE_S3C2410_I2C if I2C
820 select HAVE_S3C2410_WATCHDOG if WATCHDOG
821 select HAVE_S3C_RTC if RTC_CLASS
822 select NEED_MACH_MEMORY_H
823 select SPARSE_IRQ
824 select USE_OF
825 help
826 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
828 config ARCH_SHARK
829 bool "Shark"
830 select ARCH_USES_GETTIMEOFFSET
831 select CPU_SA110
832 select ISA
833 select ISA_DMA
834 select NEED_MACH_MEMORY_H
835 select PCI
836 select VIRT_TO_BUS
837 select ZONE_DMA
838 help
839 Support for the StrongARM based Digital DNARD machine, also known
840 as "Shark" (<http://www.shark-linux.de/shark.html>).
842 config ARCH_DAVINCI
843 bool "TI DaVinci"
844 select ARCH_HAS_HOLES_MEMORYMODEL
845 select ARCH_REQUIRE_GPIOLIB
846 select CLKDEV_LOOKUP
847 select GENERIC_ALLOCATOR
848 select GENERIC_CLOCKEVENTS
849 select GENERIC_IRQ_CHIP
850 select HAVE_IDE
851 select NEED_MACH_GPIO_H
852 select TI_PRIV_EDMA
853 select USE_OF
854 select ZONE_DMA
855 help
856 Support for TI's DaVinci platform.
858 config ARCH_OMAP1
859 bool "TI OMAP1"
860 depends on MMU
861 select ARCH_HAS_CPUFREQ
862 select ARCH_HAS_HOLES_MEMORYMODEL
863 select ARCH_OMAP
864 select ARCH_REQUIRE_GPIOLIB
865 select CLKDEV_LOOKUP
866 select CLKSRC_MMIO
867 select GENERIC_CLOCKEVENTS
868 select GENERIC_IRQ_CHIP
869 select HAVE_CLK
870 select HAVE_IDE
871 select IRQ_DOMAIN
872 select NEED_MACH_IO_H if PCCARD
873 select NEED_MACH_MEMORY_H
874 help
875 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
877 endchoice
879 menu "Multiple platform selection"
880 depends on ARCH_MULTIPLATFORM
882 comment "CPU Core family selection"
884 config ARCH_MULTI_V4T
885 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
886 depends on !ARCH_MULTI_V6_V7
887 select ARCH_MULTI_V4_V5
888 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
889 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
890 CPU_ARM925T || CPU_ARM940T)
892 config ARCH_MULTI_V5
893 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
894 depends on !ARCH_MULTI_V6_V7
895 select ARCH_MULTI_V4_V5
896 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
897 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
898 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
900 config ARCH_MULTI_V4_V5
901 bool
903 config ARCH_MULTI_V6
904 bool "ARMv6 based platforms (ARM11)"
905 select ARCH_MULTI_V6_V7
906 select CPU_V6
908 config ARCH_MULTI_V7
909 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
910 default y
911 select ARCH_MULTI_V6_V7
912 select CPU_V7
914 config ARCH_MULTI_V6_V7
915 bool
917 config ARCH_MULTI_CPU_AUTO
918 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
919 select ARCH_MULTI_V5
921 endmenu
923 #
924 # This is sorted alphabetically by mach-* pathname. However, plat-*
925 # Kconfigs may be included either alphabetically (according to the
926 # plat- suffix) or along side the corresponding mach-* source.
927 #
928 source "arch/arm/mach-mvebu/Kconfig"
930 source "arch/arm/mach-at91/Kconfig"
932 source "arch/arm/mach-bcm/Kconfig"
934 source "arch/arm/mach-bcm2835/Kconfig"
936 source "arch/arm/mach-clps711x/Kconfig"
938 source "arch/arm/mach-cns3xxx/Kconfig"
940 source "arch/arm/mach-davinci/Kconfig"
942 source "arch/arm/mach-dove/Kconfig"
944 source "arch/arm/mach-ep93xx/Kconfig"
946 source "arch/arm/mach-footbridge/Kconfig"
948 source "arch/arm/mach-gemini/Kconfig"
950 source "arch/arm/mach-highbank/Kconfig"
952 source "arch/arm/mach-integrator/Kconfig"
954 source "arch/arm/mach-iop32x/Kconfig"
956 source "arch/arm/mach-iop33x/Kconfig"
958 source "arch/arm/mach-iop13xx/Kconfig"
960 source "arch/arm/mach-ixp4xx/Kconfig"
962 source "arch/arm/mach-keystone/Kconfig"
964 source "arch/arm/mach-kirkwood/Kconfig"
966 source "arch/arm/mach-ks8695/Kconfig"
968 source "arch/arm/mach-msm/Kconfig"
970 source "arch/arm/mach-mv78xx0/Kconfig"
972 source "arch/arm/mach-imx/Kconfig"
974 source "arch/arm/mach-mxs/Kconfig"
976 source "arch/arm/mach-netx/Kconfig"
978 source "arch/arm/mach-nomadik/Kconfig"
980 source "arch/arm/mach-nspire/Kconfig"
982 source "arch/arm/plat-omap/Kconfig"
984 source "arch/arm/mach-omap1/Kconfig"
986 source "arch/arm/mach-omap2/Kconfig"
988 source "arch/arm/mach-orion5x/Kconfig"
990 source "arch/arm/mach-picoxcell/Kconfig"
992 source "arch/arm/mach-pxa/Kconfig"
993 source "arch/arm/plat-pxa/Kconfig"
995 source "arch/arm/mach-mmp/Kconfig"
997 source "arch/arm/mach-realview/Kconfig"
999 source "arch/arm/mach-rockchip/Kconfig"
1001 source "arch/arm/mach-sa1100/Kconfig"
1003 source "arch/arm/plat-samsung/Kconfig"
1005 source "arch/arm/mach-socfpga/Kconfig"
1007 source "arch/arm/mach-spear/Kconfig"
1009 source "arch/arm/mach-sti/Kconfig"
1011 source "arch/arm/mach-s3c24xx/Kconfig"
1013 if ARCH_S3C64XX
1014 source "arch/arm/mach-s3c64xx/Kconfig"
1015 endif
1017 source "arch/arm/mach-s5p64x0/Kconfig"
1019 source "arch/arm/mach-s5pc100/Kconfig"
1021 source "arch/arm/mach-s5pv210/Kconfig"
1023 source "arch/arm/mach-exynos/Kconfig"
1025 source "arch/arm/mach-shmobile/Kconfig"
1027 source "arch/arm/mach-sunxi/Kconfig"
1029 source "arch/arm/mach-prima2/Kconfig"
1031 source "arch/arm/mach-tegra/Kconfig"
1033 source "arch/arm/mach-u300/Kconfig"
1035 source "arch/arm/mach-ux500/Kconfig"
1037 source "arch/arm/mach-versatile/Kconfig"
1039 source "arch/arm/mach-vexpress/Kconfig"
1040 source "arch/arm/plat-versatile/Kconfig"
1042 source "arch/arm/mach-virt/Kconfig"
1044 source "arch/arm/mach-vt8500/Kconfig"
1046 source "arch/arm/mach-w90x900/Kconfig"
1048 source "arch/arm/mach-zynq/Kconfig"
1050 # Definitions to make life easier
1051 config ARCH_ACORN
1052 bool
1054 config PLAT_IOP
1055 bool
1056 select GENERIC_CLOCKEVENTS
1058 config PLAT_ORION
1059 bool
1060 select CLKSRC_MMIO
1061 select COMMON_CLK
1062 select GENERIC_IRQ_CHIP
1063 select IRQ_DOMAIN
1065 config PLAT_ORION_LEGACY
1066 bool
1067 select PLAT_ORION
1069 config PLAT_PXA
1070 bool
1072 config PLAT_VERSATILE
1073 bool
1075 config ARM_TIMER_SP804
1076 bool
1077 select CLKSRC_MMIO
1078 select CLKSRC_OF if OF
1080 source arch/arm/mm/Kconfig
1082 config ARM_NR_BANKS
1083 int
1084 default 16 if ARCH_EP93XX
1085 default 8
1087 config IWMMXT
1088 bool "Enable iWMMXt support" if !CPU_PJ4
1089 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1090 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1091 help
1092 Enable support for iWMMXt context switching at run time if
1093 running on a CPU that supports it.
1095 config XSCALE_PMU
1096 bool
1097 depends on CPU_XSCALE
1098 default y
1100 config MULTI_IRQ_HANDLER
1101 bool
1102 help
1103 Allow each machine to specify it's own IRQ handler at run time.
1105 if !MMU
1106 source "arch/arm/Kconfig-nommu"
1107 endif
1109 config PJ4B_ERRATA_4742
1110 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1111 depends on CPU_PJ4B && MACH_ARMADA_370
1112 default y
1113 help
1114 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1115 Event (WFE) IDLE states, a specific timing sensitivity exists between
1116 the retiring WFI/WFE instructions and the newly issued subsequent
1117 instructions. This sensitivity can result in a CPU hang scenario.
1118 Workaround:
1119 The software must insert either a Data Synchronization Barrier (DSB)
1120 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1121 instruction
1123 config ARM_ERRATA_326103
1124 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1125 depends on CPU_V6
1126 help
1127 Executing a SWP instruction to read-only memory does not set bit 11
1128 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1129 treat the access as a read, preventing a COW from occurring and
1130 causing the faulting task to livelock.
1132 config ARM_ERRATA_411920
1133 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1134 depends on CPU_V6 || CPU_V6K
1135 help
1136 Invalidation of the Instruction Cache operation can
1137 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1138 It does not affect the MPCore. This option enables the ARM Ltd.
1139 recommended workaround.
1141 config ARM_ERRATA_430973
1142 bool "ARM errata: Stale prediction on replaced interworking branch"
1143 depends on CPU_V7
1144 help
1145 This option enables the workaround for the 430973 Cortex-A8
1146 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1147 interworking branch is replaced with another code sequence at the
1148 same virtual address, whether due to self-modifying code or virtual
1149 to physical address re-mapping, Cortex-A8 does not recover from the
1150 stale interworking branch prediction. This results in Cortex-A8
1151 executing the new code sequence in the incorrect ARM or Thumb state.
1152 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1153 and also flushes the branch target cache at every context switch.
1154 Note that setting specific bits in the ACTLR register may not be
1155 available in non-secure mode.
1157 config ARM_ERRATA_458693
1158 bool "ARM errata: Processor deadlock when a false hazard is created"
1159 depends on CPU_V7
1160 depends on !ARCH_MULTIPLATFORM
1161 help
1162 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1163 erratum. For very specific sequences of memory operations, it is
1164 possible for a hazard condition intended for a cache line to instead
1165 be incorrectly associated with a different cache line. This false
1166 hazard might then cause a processor deadlock. The workaround enables
1167 the L1 caching of the NEON accesses and disables the PLD instruction
1168 in the ACTLR register. Note that setting specific bits in the ACTLR
1169 register may not be available in non-secure mode.
1171 config ARM_ERRATA_460075
1172 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1173 depends on CPU_V7
1174 depends on !ARCH_MULTIPLATFORM
1175 help
1176 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1177 erratum. Any asynchronous access to the L2 cache may encounter a
1178 situation in which recent store transactions to the L2 cache are lost
1179 and overwritten with stale memory contents from external memory. The
1180 workaround disables the write-allocate mode for the L2 cache via the
1181 ACTLR register. Note that setting specific bits in the ACTLR register
1182 may not be available in non-secure mode.
1184 config ARM_ERRATA_742230
1185 bool "ARM errata: DMB operation may be faulty"
1186 depends on CPU_V7 && SMP
1187 depends on !ARCH_MULTIPLATFORM
1188 help
1189 This option enables the workaround for the 742230 Cortex-A9
1190 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1191 between two write operations may not ensure the correct visibility
1192 ordering of the two writes. This workaround sets a specific bit in
1193 the diagnostic register of the Cortex-A9 which causes the DMB
1194 instruction to behave as a DSB, ensuring the correct behaviour of
1195 the two writes.
1197 config ARM_ERRATA_742231
1198 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1199 depends on CPU_V7 && SMP
1200 depends on !ARCH_MULTIPLATFORM
1201 help
1202 This option enables the workaround for the 742231 Cortex-A9
1203 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1204 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1205 accessing some data located in the same cache line, may get corrupted
1206 data due to bad handling of the address hazard when the line gets
1207 replaced from one of the CPUs at the same time as another CPU is
1208 accessing it. This workaround sets specific bits in the diagnostic
1209 register of the Cortex-A9 which reduces the linefill issuing
1210 capabilities of the processor.
1212 config PL310_ERRATA_588369
1213 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1214 depends on CACHE_L2X0
1215 help
1216 The PL310 L2 cache controller implements three types of Clean &
1217 Invalidate maintenance operations: by Physical Address
1218 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1219 They are architecturally defined to behave as the execution of a
1220 clean operation followed immediately by an invalidate operation,
1221 both performing to the same memory location. This functionality
1222 is not correctly implemented in PL310 as clean lines are not
1223 invalidated as a result of these operations.
1225 config ARM_ERRATA_643719
1226 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1227 depends on CPU_V7 && SMP
1228 help
1229 This option enables the workaround for the 643719 Cortex-A9 (prior to
1230 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1231 register returns zero when it should return one. The workaround
1232 corrects this value, ensuring cache maintenance operations which use
1233 it behave as intended and avoiding data corruption.
1235 config ARM_ERRATA_720789
1236 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1237 depends on CPU_V7
1238 help
1239 This option enables the workaround for the 720789 Cortex-A9 (prior to
1240 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1241 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1242 As a consequence of this erratum, some TLB entries which should be
1243 invalidated are not, resulting in an incoherency in the system page
1244 tables. The workaround changes the TLB flushing routines to invalidate
1245 entries regardless of the ASID.
1247 config PL310_ERRATA_727915
1248 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1249 depends on CACHE_L2X0
1250 help
1251 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1252 operation (offset 0x7FC). This operation runs in background so that
1253 PL310 can handle normal accesses while it is in progress. Under very
1254 rare circumstances, due to this erratum, write data can be lost when
1255 PL310 treats a cacheable write transaction during a Clean &
1256 Invalidate by Way operation.
1258 config ARM_ERRATA_743622
1259 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1260 depends on CPU_V7
1261 depends on !ARCH_MULTIPLATFORM
1262 help
1263 This option enables the workaround for the 743622 Cortex-A9
1264 (r2p*) erratum. Under very rare conditions, a faulty
1265 optimisation in the Cortex-A9 Store Buffer may lead to data
1266 corruption. This workaround sets a specific bit in the diagnostic
1267 register of the Cortex-A9 which disables the Store Buffer
1268 optimisation, preventing the defect from occurring. This has no
1269 visible impact on the overall performance or power consumption of the
1270 processor.
1272 config ARM_ERRATA_751472
1273 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1274 depends on CPU_V7
1275 depends on !ARCH_MULTIPLATFORM
1276 help
1277 This option enables the workaround for the 751472 Cortex-A9 (prior
1278 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1279 completion of a following broadcasted operation if the second
1280 operation is received by a CPU before the ICIALLUIS has completed,
1281 potentially leading to corrupted entries in the cache or TLB.
1283 config PL310_ERRATA_753970
1284 bool "PL310 errata: cache sync operation may be faulty"
1285 depends on CACHE_PL310
1286 help
1287 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1289 Under some condition the effect of cache sync operation on
1290 the store buffer still remains when the operation completes.
1291 This means that the store buffer is always asked to drain and
1292 this prevents it from merging any further writes. The workaround
1293 is to replace the normal offset of cache sync operation (0x730)
1294 by another offset targeting an unmapped PL310 register 0x740.
1295 This has the same effect as the cache sync operation: store buffer
1296 drain and waiting for all buffers empty.
1298 config ARM_ERRATA_754322
1299 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1300 depends on CPU_V7
1301 help
1302 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1303 r3p*) erratum. A speculative memory access may cause a page table walk
1304 which starts prior to an ASID switch but completes afterwards. This
1305 can populate the micro-TLB with a stale entry which may be hit with
1306 the new ASID. This workaround places two dsb instructions in the mm
1307 switching code so that no page table walks can cross the ASID switch.
1309 config ARM_ERRATA_754327
1310 bool "ARM errata: no automatic Store Buffer drain"
1311 depends on CPU_V7 && SMP
1312 help
1313 This option enables the workaround for the 754327 Cortex-A9 (prior to
1314 r2p0) erratum. The Store Buffer does not have any automatic draining
1315 mechanism and therefore a livelock may occur if an external agent
1316 continuously polls a memory location waiting to observe an update.
1317 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1318 written polling loops from denying visibility of updates to memory.
1320 config ARM_ERRATA_364296
1321 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1322 depends on CPU_V6
1323 help
1324 This options enables the workaround for the 364296 ARM1136
1325 r0p2 erratum (possible cache data corruption with
1326 hit-under-miss enabled). It sets the undocumented bit 31 in
1327 the auxiliary control register and the FI bit in the control
1328 register, thus disabling hit-under-miss without putting the
1329 processor into full low interrupt latency mode. ARM11MPCore
1330 is not affected.
1332 config ARM_ERRATA_764369
1333 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1334 depends on CPU_V7 && SMP
1335 help
1336 This option enables the workaround for erratum 764369
1337 affecting Cortex-A9 MPCore with two or more processors (all
1338 current revisions). Under certain timing circumstances, a data
1339 cache line maintenance operation by MVA targeting an Inner
1340 Shareable memory region may fail to proceed up to either the
1341 Point of Coherency or to the Point of Unification of the
1342 system. This workaround adds a DSB instruction before the
1343 relevant cache maintenance functions and sets a specific bit
1344 in the diagnostic control register of the SCU.
1346 config PL310_ERRATA_769419
1347 bool "PL310 errata: no automatic Store Buffer drain"
1348 depends on CACHE_L2X0
1349 help
1350 On revisions of the PL310 prior to r3p2, the Store Buffer does
1351 not automatically drain. This can cause normal, non-cacheable
1352 writes to be retained when the memory system is idle, leading
1353 to suboptimal I/O performance for drivers using coherent DMA.
1354 This option adds a write barrier to the cpu_idle loop so that,
1355 on systems with an outer cache, the store buffer is drained
1356 explicitly.
1358 config ARM_ERRATA_775420
1359 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1360 depends on CPU_V7
1361 help
1362 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1363 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1364 operation aborts with MMU exception, it might cause the processor
1365 to deadlock. This workaround puts DSB before executing ISB if
1366 an abort may occur on cache maintenance.
1368 config ARM_ERRATA_798181
1369 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1370 depends on CPU_V7 && SMP
1371 help
1372 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1373 adequately shooting down all use of the old entries. This
1374 option enables the Linux kernel workaround for this erratum
1375 which sends an IPI to the CPUs that are running the same ASID
1376 as the one being invalidated.
1378 config ARM_ERRATA_773022
1379 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1380 depends on CPU_V7
1381 help
1382 This option enables the workaround for the 773022 Cortex-A15
1383 (up to r0p4) erratum. In certain rare sequences of code, the
1384 loop buffer may deliver incorrect instructions. This
1385 workaround disables the loop buffer to avoid the erratum.
1387 endmenu
1389 source "arch/arm/common/Kconfig"
1391 menu "Bus support"
1393 config ARM_AMBA
1394 bool
1396 config ISA
1397 bool
1398 help
1399 Find out whether you have ISA slots on your motherboard. ISA is the
1400 name of a bus system, i.e. the way the CPU talks to the other stuff
1401 inside your box. Other bus systems are PCI, EISA, MicroChannel
1402 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1403 newer boards don't support it. If you have ISA, say Y, otherwise N.
1405 # Select ISA DMA controller support
1406 config ISA_DMA
1407 bool
1408 select ISA_DMA_API
1410 # Select ISA DMA interface
1411 config ISA_DMA_API
1412 bool
1414 config PCI
1415 bool "PCI support" if MIGHT_HAVE_PCI
1416 help
1417 Find out whether you have a PCI motherboard. PCI is the name of a
1418 bus system, i.e. the way the CPU talks to the other stuff inside
1419 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1420 VESA. If you have PCI, say Y, otherwise N.
1422 config PCI_DOMAINS
1423 bool
1424 depends on PCI
1426 config PCI_NANOENGINE
1427 bool "BSE nanoEngine PCI support"
1428 depends on SA1100_NANOENGINE
1429 help
1430 Enable PCI on the BSE nanoEngine board.
1432 config PCI_SYSCALL
1433 def_bool PCI
1435 # Select the host bridge type
1436 config PCI_HOST_VIA82C505
1437 bool
1438 depends on PCI && ARCH_SHARK
1439 default y
1441 config PCI_HOST_ITE8152
1442 bool
1443 depends on PCI && MACH_ARMCORE
1444 default y
1445 select DMABOUNCE
1447 source "drivers/pci/Kconfig"
1448 source "drivers/pci/pcie/Kconfig"
1450 source "drivers/pcmcia/Kconfig"
1452 endmenu
1454 menu "Kernel Features"
1456 config HAVE_SMP
1457 bool
1458 help
1459 This option should be selected by machines which have an SMP-
1460 capable CPU.
1462 The only effect of this option is to make the SMP-related
1463 options available to the user for configuration.
1465 config SMP
1466 bool "Symmetric Multi-Processing"
1467 depends on CPU_V6K || CPU_V7
1468 depends on GENERIC_CLOCKEVENTS
1469 depends on HAVE_SMP
1470 depends on MMU || ARM_MPU
1471 select USE_GENERIC_SMP_HELPERS
1472 help
1473 This enables support for systems with more than one CPU. If you have
1474 a system with only one CPU, like most personal computers, say N. If
1475 you have a system with more than one CPU, say Y.
1477 If you say N here, the kernel will run on single and multiprocessor
1478 machines, but will use only one CPU of a multiprocessor machine. If
1479 you say Y here, the kernel will run on many, but not all, single
1480 processor machines. On a single processor machine, the kernel will
1481 run faster if you say N here.
1483 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1484 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1485 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1487 If you don't know what to do here, say N.
1489 config SMP_ON_UP
1490 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1491 depends on SMP && !XIP_KERNEL && MMU
1492 default y
1493 help
1494 SMP kernels contain instructions which fail on non-SMP processors.
1495 Enabling this option allows the kernel to modify itself to make
1496 these instructions safe. Disabling it allows about 1K of space
1497 savings.
1499 If you don't know what to do here, say Y.
1501 config ARM_CPU_TOPOLOGY
1502 bool "Support cpu topology definition"
1503 depends on SMP && CPU_V7
1504 default y
1505 help
1506 Support ARM cpu topology definition. The MPIDR register defines
1507 affinity between processors which is then used to describe the cpu
1508 topology of an ARM System.
1510 config SCHED_MC
1511 bool "Multi-core scheduler support"
1512 depends on ARM_CPU_TOPOLOGY
1513 help
1514 Multi-core scheduler support improves the CPU scheduler's decision
1515 making when dealing with multi-core CPU chips at a cost of slightly
1516 increased overhead in some places. If unsure say N here.
1518 config SCHED_SMT
1519 bool "SMT scheduler support"
1520 depends on ARM_CPU_TOPOLOGY
1521 help
1522 Improves the CPU scheduler's decision making when dealing with
1523 MultiThreading at a cost of slightly increased overhead in some
1524 places. If unsure say N here.
1526 config HAVE_ARM_SCU
1527 bool
1528 help
1529 This option enables support for the ARM system coherency unit
1531 config HAVE_ARM_ARCH_TIMER
1532 bool "Architected timer support"
1533 depends on CPU_V7
1534 select ARM_ARCH_TIMER
1535 help
1536 This option enables support for the ARM architected timer
1538 config HAVE_ARM_TWD
1539 bool
1540 depends on SMP
1541 select CLKSRC_OF if OF
1542 help
1543 This options enables support for the ARM timer and watchdog unit
1545 config MCPM
1546 bool "Multi-Cluster Power Management"
1547 depends on CPU_V7 && SMP
1548 help
1549 This option provides the common power management infrastructure
1550 for (multi-)cluster based systems, such as big.LITTLE based
1551 systems.
1553 choice
1554 prompt "Memory split"
1555 default VMSPLIT_3G
1556 help
1557 Select the desired split between kernel and user memory.
1559 If you are not absolutely sure what you are doing, leave this
1560 option alone!
1562 config VMSPLIT_3G
1563 bool "3G/1G user/kernel split"
1564 config VMSPLIT_2G
1565 bool "2G/2G user/kernel split"
1566 config VMSPLIT_1G
1567 bool "1G/3G user/kernel split"
1568 endchoice
1570 config PAGE_OFFSET
1571 hex
1572 default 0x40000000 if VMSPLIT_1G
1573 default 0x80000000 if VMSPLIT_2G
1574 default 0xC0000000
1576 config NR_CPUS
1577 int "Maximum number of CPUs (2-32)"
1578 range 2 32
1579 depends on SMP
1580 default "4"
1582 config HOTPLUG_CPU
1583 bool "Support for hot-pluggable CPUs"
1584 depends on SMP
1585 help
1586 Say Y here to experiment with turning CPUs off and on. CPUs
1587 can be controlled through /sys/devices/system/cpu.
1589 config ARM_PSCI
1590 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1591 depends on CPU_V7
1592 help
1593 Say Y here if you want Linux to communicate with system firmware
1594 implementing the PSCI specification for CPU-centric power
1595 management operations described in ARM document number ARM DEN
1596 0022A ("Power State Coordination Interface System Software on
1597 ARM processors").
1599 # The GPIO number here must be sorted by descending number. In case of
1600 # a multiplatform kernel, we just want the highest value required by the
1601 # selected platforms.
1602 config ARCH_NR_GPIO
1603 int
1604 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1605 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1606 default 392 if ARCH_U8500
1607 default 352 if ARCH_VT8500
1608 default 288 if ARCH_SUNXI
1609 default 264 if MACH_H4700
1610 default 0
1611 help
1612 Maximum number of GPIOs in the system.
1614 If unsure, leave the default value.
1616 source kernel/Kconfig.preempt
1618 config HZ_FIXED
1619 int
1620 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1621 ARCH_S5PV210 || ARCH_EXYNOS4
1622 default AT91_TIMER_HZ if ARCH_AT91
1623 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1624 default 0
1626 choice
1627 depends on HZ_FIXED = 0
1628 prompt "Timer frequency"
1630 config HZ_100
1631 bool "100 Hz"
1633 config HZ_200
1634 bool "200 Hz"
1636 config HZ_250
1637 bool "250 Hz"
1639 config HZ_300
1640 bool "300 Hz"
1642 config HZ_500
1643 bool "500 Hz"
1645 config HZ_1000
1646 bool "1000 Hz"
1648 endchoice
1650 config HZ
1651 int
1652 default HZ_FIXED if HZ_FIXED != 0
1653 default 100 if HZ_100
1654 default 200 if HZ_200
1655 default 250 if HZ_250
1656 default 300 if HZ_300
1657 default 500 if HZ_500
1658 default 1000
1660 config SCHED_HRTICK
1661 def_bool HIGH_RES_TIMERS
1663 config SCHED_HRTICK
1664 def_bool HIGH_RES_TIMERS
1666 config THUMB2_KERNEL
1667 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1668 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1669 default y if CPU_THUMBONLY
1670 select AEABI
1671 select ARM_ASM_UNIFIED
1672 select ARM_UNWIND
1673 help
1674 By enabling this option, the kernel will be compiled in
1675 Thumb-2 mode. A compiler/assembler that understand the unified
1676 ARM-Thumb syntax is needed.
1678 If unsure, say N.
1680 config THUMB2_AVOID_R_ARM_THM_JUMP11
1681 bool "Work around buggy Thumb-2 short branch relocations in gas"
1682 depends on THUMB2_KERNEL && MODULES
1683 default y
1684 help
1685 Various binutils versions can resolve Thumb-2 branches to
1686 locally-defined, preemptible global symbols as short-range "b.n"
1687 branch instructions.
1689 This is a problem, because there's no guarantee the final
1690 destination of the symbol, or any candidate locations for a
1691 trampoline, are within range of the branch. For this reason, the
1692 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1693 relocation in modules at all, and it makes little sense to add
1694 support.
1696 The symptom is that the kernel fails with an "unsupported
1697 relocation" error when loading some modules.
1699 Until fixed tools are available, passing
1700 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1701 code which hits this problem, at the cost of a bit of extra runtime
1702 stack usage in some cases.
1704 The problem is described in more detail at:
1705 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1707 Only Thumb-2 kernels are affected.
1709 Unless you are sure your tools don't have this problem, say Y.
1711 config ARM_ASM_UNIFIED
1712 bool
1714 config AEABI
1715 bool "Use the ARM EABI to compile the kernel"
1716 help
1717 This option allows for the kernel to be compiled using the latest
1718 ARM ABI (aka EABI). This is only useful if you are using a user
1719 space environment that is also compiled with EABI.
1721 Since there are major incompatibilities between the legacy ABI and
1722 EABI, especially with regard to structure member alignment, this
1723 option also changes the kernel syscall calling convention to
1724 disambiguate both ABIs and allow for backward compatibility support
1725 (selected with CONFIG_OABI_COMPAT).
1727 To use this you need GCC version 4.0.0 or later.
1729 config OABI_COMPAT
1730 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1731 depends on AEABI && !THUMB2_KERNEL
1732 default y
1733 help
1734 This option preserves the old syscall interface along with the
1735 new (ARM EABI) one. It also provides a compatibility layer to
1736 intercept syscalls that have structure arguments which layout
1737 in memory differs between the legacy ABI and the new ARM EABI
1738 (only for non "thumb" binaries). This option adds a tiny
1739 overhead to all syscalls and produces a slightly larger kernel.
1740 If you know you'll be using only pure EABI user space then you
1741 can say N here. If this option is not selected and you attempt
1742 to execute a legacy ABI binary then the result will be
1743 UNPREDICTABLE (in fact it can be predicted that it won't work
1744 at all). If in doubt say Y.
1746 config ARCH_HAS_HOLES_MEMORYMODEL
1747 bool
1749 config ARCH_SPARSEMEM_ENABLE
1750 bool
1752 config ARCH_SPARSEMEM_DEFAULT
1753 def_bool ARCH_SPARSEMEM_ENABLE
1755 config ARCH_SELECT_MEMORY_MODEL
1756 def_bool ARCH_SPARSEMEM_ENABLE
1758 config HAVE_ARCH_PFN_VALID
1759 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1761 config HIGHMEM
1762 bool "High Memory Support"
1763 depends on MMU
1764 help
1765 The address space of ARM processors is only 4 Gigabytes large
1766 and it has to accommodate user address space, kernel address
1767 space as well as some memory mapped IO. That means that, if you
1768 have a large amount of physical memory and/or IO, not all of the
1769 memory can be "permanently mapped" by the kernel. The physical
1770 memory that is not permanently mapped is called "high memory".
1772 Depending on the selected kernel/user memory split, minimum
1773 vmalloc space and actual amount of RAM, you may not need this
1774 option which should result in a slightly faster kernel.
1776 If unsure, say n.
1778 config HIGHPTE
1779 bool "Allocate 2nd-level pagetables from highmem"
1780 depends on HIGHMEM
1782 config HW_PERF_EVENTS
1783 bool "Enable hardware performance counter support for perf events"
1784 depends on PERF_EVENTS
1785 default y
1786 help
1787 Enable hardware performance counter support for perf events. If
1788 disabled, perf events will use software events only.
1790 config SYS_SUPPORTS_HUGETLBFS
1791 def_bool y
1792 depends on ARM_LPAE
1794 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1795 def_bool y
1796 depends on ARM_LPAE
1798 config ARCH_WANT_GENERAL_HUGETLB
1799 def_bool y
1801 source "mm/Kconfig"
1803 config FORCE_MAX_ZONEORDER
1804 int "Maximum zone order" if ARCH_SHMOBILE
1805 range 11 64 if ARCH_SHMOBILE
1806 default "12" if SOC_AM33XX
1807 default "9" if SA1111
1808 default "11"
1809 help
1810 The kernel memory allocator divides physically contiguous memory
1811 blocks into "zones", where each zone is a power of two number of
1812 pages. This option selects the largest power of two that the kernel
1813 keeps in the memory allocator. If you need to allocate very large
1814 blocks of physically contiguous memory, then you may need to
1815 increase this value.
1817 This config option is actually maximum order plus one. For example,
1818 a value of 11 means that the largest free memory block is 2^10 pages.
1820 config ALIGNMENT_TRAP
1821 bool
1822 depends on CPU_CP15_MMU
1823 default y if !ARCH_EBSA110
1824 select HAVE_PROC_CPU if PROC_FS
1825 help
1826 ARM processors cannot fetch/store information which is not
1827 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1828 address divisible by 4. On 32-bit ARM processors, these non-aligned
1829 fetch/store instructions will be emulated in software if you say
1830 here, which has a severe performance impact. This is necessary for
1831 correct operation of some network protocols. With an IP-only
1832 configuration it is safe to say N, otherwise say Y.
1834 config UACCESS_WITH_MEMCPY
1835 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1836 depends on MMU
1837 default y if CPU_FEROCEON
1838 help
1839 Implement faster copy_to_user and clear_user methods for CPU
1840 cores where a 8-word STM instruction give significantly higher
1841 memory write throughput than a sequence of individual 32bit stores.
1843 A possible side effect is a slight increase in scheduling latency
1844 between threads sharing the same address space if they invoke
1845 such copy operations with large buffers.
1847 However, if the CPU data cache is using a write-allocate mode,
1848 this option is unlikely to provide any performance gain.
1850 config SECCOMP
1851 bool
1852 prompt "Enable seccomp to safely compute untrusted bytecode"
1853 ---help---
1854 This kernel feature is useful for number crunching applications
1855 that may need to compute untrusted bytecode during their
1856 execution. By using pipes or other transports made available to
1857 the process as file descriptors supporting the read/write
1858 syscalls, it's possible to isolate those applications in
1859 their own address space using seccomp. Once seccomp is
1860 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1861 and the task is only allowed to execute a few safe syscalls
1862 defined by each seccomp mode.
1864 config CC_STACKPROTECTOR
1865 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1866 help
1867 This option turns on the -fstack-protector GCC feature. This
1868 feature puts, at the beginning of functions, a canary value on
1869 the stack just before the return address, and validates
1870 the value just before actually returning. Stack based buffer
1871 overflows (that need to overwrite this return address) now also
1872 overwrite the canary, which gets detected and the attack is then
1873 neutralized via a kernel panic.
1874 This feature requires gcc version 4.2 or above.
1876 config XEN_DOM0
1877 def_bool y
1878 depends on XEN
1880 config XEN
1881 bool "Xen guest support on ARM (EXPERIMENTAL)"
1882 depends on ARM && AEABI && OF
1883 depends on CPU_V7 && !CPU_V6
1884 depends on !GENERIC_ATOMIC64
1885 select ARM_PSCI
1886 help
1887 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1889 endmenu
1891 menu "Boot options"
1893 config USE_OF
1894 bool "Flattened Device Tree support"
1895 select IRQ_DOMAIN
1896 select OF
1897 select OF_EARLY_FLATTREE
1898 help
1899 Include support for flattened device tree machine descriptions.
1901 config ATAGS
1902 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1903 default y
1904 help
1905 This is the traditional way of passing data to the kernel at boot
1906 time. If you are solely relying on the flattened device tree (or
1907 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1908 to remove ATAGS support from your kernel binary. If unsure,
1909 leave this to y.
1911 config DEPRECATED_PARAM_STRUCT
1912 bool "Provide old way to pass kernel parameters"
1913 depends on ATAGS
1914 help
1915 This was deprecated in 2001 and announced to live on for 5 years.
1916 Some old boot loaders still use this way.
1918 # Compressed boot loader in ROM. Yes, we really want to ask about
1919 # TEXT and BSS so we preserve their values in the config files.
1920 config ZBOOT_ROM_TEXT
1921 hex "Compressed ROM boot loader base address"
1922 default "0"
1923 help
1924 The physical address at which the ROM-able zImage is to be
1925 placed in the target. Platforms which normally make use of
1926 ROM-able zImage formats normally set this to a suitable
1927 value in their defconfig file.
1929 If ZBOOT_ROM is not enabled, this has no effect.
1931 config ZBOOT_ROM_BSS
1932 hex "Compressed ROM boot loader BSS address"
1933 default "0"
1934 help
1935 The base address of an area of read/write memory in the target
1936 for the ROM-able zImage which must be available while the
1937 decompressor is running. It must be large enough to hold the
1938 entire decompressed kernel plus an additional 128 KiB.
1939 Platforms which normally make use of ROM-able zImage formats
1940 normally set this to a suitable value in their defconfig file.
1942 If ZBOOT_ROM is not enabled, this has no effect.
1944 config ZBOOT_ROM
1945 bool "Compressed boot loader in ROM/flash"
1946 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1947 help
1948 Say Y here if you intend to execute your compressed kernel image
1949 (zImage) directly from ROM or flash. If unsure, say N.
1951 choice
1952 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1953 depends on ZBOOT_ROM && ARCH_SH7372
1954 default ZBOOT_ROM_NONE
1955 help
1956 Include experimental SD/MMC loading code in the ROM-able zImage.
1957 With this enabled it is possible to write the ROM-able zImage
1958 kernel image to an MMC or SD card and boot the kernel straight
1959 from the reset vector. At reset the processor Mask ROM will load
1960 the first part of the ROM-able zImage which in turn loads the
1961 rest the kernel image to RAM.
1963 config ZBOOT_ROM_NONE
1964 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1965 help
1966 Do not load image from SD or MMC
1968 config ZBOOT_ROM_MMCIF
1969 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1970 help
1971 Load image from MMCIF hardware block.
1973 config ZBOOT_ROM_SH_MOBILE_SDHI
1974 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1975 help
1976 Load image from SDHI hardware block
1978 endchoice
1980 config ARM_APPENDED_DTB
1981 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1982 depends on OF && !ZBOOT_ROM
1983 help
1984 With this option, the boot code will look for a device tree binary
1985 (DTB) appended to zImage
1986 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1988 This is meant as a backward compatibility convenience for those
1989 systems with a bootloader that can't be upgraded to accommodate
1990 the documented boot protocol using a device tree.
1992 Beware that there is very little in terms of protection against
1993 this option being confused by leftover garbage in memory that might
1994 look like a DTB header after a reboot if no actual DTB is appended
1995 to zImage. Do not leave this option active in a production kernel
1996 if you don't intend to always append a DTB. Proper passing of the
1997 location into r2 of a bootloader provided DTB is always preferable
1998 to this option.
2000 config ARM_ATAG_DTB_COMPAT
2001 bool "Supplement the appended DTB with traditional ATAG information"
2002 depends on ARM_APPENDED_DTB
2003 help
2004 Some old bootloaders can't be updated to a DTB capable one, yet
2005 they provide ATAGs with memory configuration, the ramdisk address,
2006 the kernel cmdline string, etc. Such information is dynamically
2007 provided by the bootloader and can't always be stored in a static
2008 DTB. To allow a device tree enabled kernel to be used with such
2009 bootloaders, this option allows zImage to extract the information
2010 from the ATAG list and store it at run time into the appended DTB.
2012 choice
2013 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2014 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2016 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2017 bool "Use bootloader kernel arguments if available"
2018 help
2019 Uses the command-line options passed by the boot loader instead of
2020 the device tree bootargs property. If the boot loader doesn't provide
2021 any, the device tree bootargs property will be used.
2023 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2024 bool "Extend with bootloader kernel arguments"
2025 help
2026 The command-line arguments provided by the boot loader will be
2027 appended to the the device tree bootargs property.
2029 endchoice
2031 config CMDLINE
2032 string "Default kernel command string"
2033 default ""
2034 help
2035 On some architectures (EBSA110 and CATS), there is currently no way
2036 for the boot loader to pass arguments to the kernel. For these
2037 architectures, you should supply some command-line options at build
2038 time by entering them here. As a minimum, you should specify the
2039 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2041 choice
2042 prompt "Kernel command line type" if CMDLINE != ""
2043 default CMDLINE_FROM_BOOTLOADER
2044 depends on ATAGS
2046 config CMDLINE_FROM_BOOTLOADER
2047 bool "Use bootloader kernel arguments if available"
2048 help
2049 Uses the command-line options passed by the boot loader. If
2050 the boot loader doesn't provide any, the default kernel command
2051 string provided in CMDLINE will be used.
2053 config CMDLINE_EXTEND
2054 bool "Extend bootloader kernel arguments"
2055 help
2056 The command-line arguments provided by the boot loader will be
2057 appended to the default kernel command string.
2059 config CMDLINE_FORCE
2060 bool "Always use the default kernel command string"
2061 help
2062 Always use the default kernel command string, even if the boot
2063 loader passes other arguments to the kernel.
2064 This is useful if you cannot or don't want to change the
2065 command-line options your boot loader passes to the kernel.
2066 endchoice
2068 config XIP_KERNEL
2069 bool "Kernel Execute-In-Place from ROM"
2070 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2071 help
2072 Execute-In-Place allows the kernel to run from non-volatile storage
2073 directly addressable by the CPU, such as NOR flash. This saves RAM
2074 space since the text section of the kernel is not loaded from flash
2075 to RAM. Read-write sections, such as the data section and stack,
2076 are still copied to RAM. The XIP kernel is not compressed since
2077 it has to run directly from flash, so it will take more space to
2078 store it. The flash address used to link the kernel object files,
2079 and for storing it, is configuration dependent. Therefore, if you
2080 say Y here, you must know the proper physical address where to
2081 store the kernel image depending on your own flash memory usage.
2083 Also note that the make target becomes "make xipImage" rather than
2084 "make zImage" or "make Image". The final kernel binary to put in
2085 ROM memory will be arch/arm/boot/xipImage.
2087 If unsure, say N.
2089 config XIP_PHYS_ADDR
2090 hex "XIP Kernel Physical Location"
2091 depends on XIP_KERNEL
2092 default "0x00080000"
2093 help
2094 This is the physical address in your flash memory the kernel will
2095 be linked for and stored to. This address is dependent on your
2096 own flash usage.
2098 config KEXEC
2099 bool "Kexec system call (EXPERIMENTAL)"
2100 depends on (!SMP || PM_SLEEP_SMP)
2101 help
2102 kexec is a system call that implements the ability to shutdown your
2103 current kernel, and to start another kernel. It is like a reboot
2104 but it is independent of the system firmware. And like a reboot
2105 you can start any kernel with it, not just Linux.
2107 It is an ongoing process to be certain the hardware in a machine
2108 is properly shutdown, so do not be surprised if this code does not
2109 initially work for you.
2111 config ATAGS_PROC
2112 bool "Export atags in procfs"
2113 depends on ATAGS && KEXEC
2114 default y
2115 help
2116 Should the atags used to boot the kernel be exported in an "atags"
2117 file in procfs. Useful with kexec.
2119 config CRASH_DUMP
2120 bool "Build kdump crash kernel (EXPERIMENTAL)"
2121 help
2122 Generate crash dump after being started by kexec. This should
2123 be normally only set in special crash dump kernels which are
2124 loaded in the main kernel with kexec-tools into a specially
2125 reserved region and then later executed after a crash by
2126 kdump/kexec. The crash dump kernel must be compiled to a
2127 memory address not used by the main kernel
2129 For more details see Documentation/kdump/kdump.txt
2131 config AUTO_ZRELADDR
2132 bool "Auto calculation of the decompressed kernel image address"
2133 depends on !ZBOOT_ROM
2134 help
2135 ZRELADDR is the physical address where the decompressed kernel
2136 image will be placed. If AUTO_ZRELADDR is selected, the address
2137 will be determined at run-time by masking the current IP with
2138 0xf8000000. This assumes the zImage being placed in the first 128MB
2139 from start of memory.
2141 endmenu
2143 menu "CPU Power Management"
2145 if ARCH_HAS_CPUFREQ
2146 source "drivers/cpufreq/Kconfig"
2147 endif
2149 source "drivers/cpuidle/Kconfig"
2151 endmenu
2153 menu "Floating point emulation"
2155 comment "At least one emulation must be selected"
2157 config FPE_NWFPE
2158 bool "NWFPE math emulation"
2159 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2160 ---help---
2161 Say Y to include the NWFPE floating point emulator in the kernel.
2162 This is necessary to run most binaries. Linux does not currently
2163 support floating point hardware so you need to say Y here even if
2164 your machine has an FPA or floating point co-processor podule.
2166 You may say N here if you are going to load the Acorn FPEmulator
2167 early in the bootup.
2169 config FPE_NWFPE_XP
2170 bool "Support extended precision"
2171 depends on FPE_NWFPE
2172 help
2173 Say Y to include 80-bit support in the kernel floating-point
2174 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2175 Note that gcc does not generate 80-bit operations by default,
2176 so in most cases this option only enlarges the size of the
2177 floating point emulator without any good reason.
2179 You almost surely want to say N here.
2181 config FPE_FASTFPE
2182 bool "FastFPE math emulation (EXPERIMENTAL)"
2183 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2184 ---help---
2185 Say Y here to include the FAST floating point emulator in the kernel.
2186 This is an experimental much faster emulator which now also has full
2187 precision for the mantissa. It does not support any exceptions.
2188 It is very simple, and approximately 3-6 times faster than NWFPE.
2190 It should be sufficient for most programs. It may be not suitable
2191 for scientific calculations, but you have to check this for yourself.
2192 If you do not feel you need a faster FP emulation you should better
2193 choose NWFPE.
2195 config VFP
2196 bool "VFP-format floating point maths"
2197 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2198 help
2199 Say Y to include VFP support code in the kernel. This is needed
2200 if your hardware includes a VFP unit.
2202 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2203 release notes and additional status information.
2205 Say N if your target does not have VFP hardware.
2207 config VFPv3
2208 bool
2209 depends on VFP
2210 default y if CPU_V7
2212 config NEON
2213 bool "Advanced SIMD (NEON) Extension support"
2214 depends on VFPv3 && CPU_V7
2215 help
2216 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2217 Extension.
2219 config KERNEL_MODE_NEON
2220 bool "Support for NEON in kernel mode"
2221 depends on NEON && AEABI
2222 help
2223 Say Y to include support for NEON in kernel mode.
2225 endmenu
2227 menu "Userspace binary formats"
2229 source "fs/Kconfig.binfmt"
2231 config ARTHUR
2232 tristate "RISC OS personality"
2233 depends on !AEABI
2234 help
2235 Say Y here to include the kernel code necessary if you want to run
2236 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2237 experimental; if this sounds frightening, say N and sleep in peace.
2238 You can also say M here to compile this support as a module (which
2239 will be called arthur).
2241 endmenu
2243 menu "Power management options"
2245 source "kernel/power/Kconfig"
2247 config ARCH_SUSPEND_POSSIBLE
2248 depends on !ARCH_S5PC100
2249 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2250 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2251 def_bool y
2253 config ARM_CPU_SUSPEND
2254 def_bool PM_SLEEP
2256 endmenu
2258 source "net/Kconfig"
2260 source "drivers/Kconfig"
2262 source "fs/Kconfig"
2264 source "arch/arm/Kconfig.debug"
2266 source "security/Kconfig"
2268 source "crypto/Kconfig"
2270 source "lib/Kconfig"
2272 source "arch/arm/kvm/Kconfig"