2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
18 * Note that these macros must not contain any code which is not
19 * 100% relocatable. Any attempt to do so will result in a crash.
20 * Please select one of the following when turning on debugging.
24 #if defined(CONFIG_DEBUG_ICEDCC)
26 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
27 .macro loadsp, rb, tmp
30 mcr p14, 0, \ch, c0, c5, 0
32 #elif defined(CONFIG_CPU_XSCALE)
33 .macro loadsp, rb, tmp
36 mcr p14, 0, \ch, c8, c0, 0
39 .macro loadsp, rb, tmp
42 mcr p14, 0, \ch, c1, c0, 0
48 #include CONFIG_DEBUG_LL_INCLUDE
54 #if defined(CONFIG_ARCH_SA1100)
55 .macro loadsp, rb, tmp
56 mov \rb, #0x80000000 @ physical base address
57 #ifdef CONFIG_DEBUG_LL_SER3
58 add \rb, \rb, #0x00050000 @ Ser3
60 add \rb, \rb, #0x00010000 @ Ser1
63 #elif defined(CONFIG_ARCH_S3C24XX)
64 .macro loadsp, rb, tmp
66 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
69 .macro loadsp, rb, tmp
87 .macro debug_reloc_start
90 kphex r6, 8 /* processor id */
92 kphex r7, 8 /* architecture id */
93 #ifdef CONFIG_CPU_CP15
95 mrc p15, 0, r0, c1, c0
96 kphex r0, 8 /* control reg */
99 kphex r5, 8 /* decompressed kernel start */
101 kphex r9, 8 /* decompressed kernel end */
103 kphex r4, 8 /* kernel execution address */
108 .macro debug_reloc_end
110 kphex r5, 8 /* end of kernel */
113 bl memdump /* dump 256 bytes at start of kernel */
117 .section ".start", #alloc, #execinstr
119 * sort out different calling conventions
122 .arm @ Always enter in ARM state
124 .type start,#function
130 THUMB( adr r12, BSYM(1f) )
133 .word 0x016f2818 @ Magic numbers to help the loader
134 .word start @ absolute load/run zImage address
135 .word _edata @ zImage end address
139 #ifdef CONFIG_ARM_VIRT_EXT
140 bl __hyp_stub_install @ get into SVC mode, reversibly
142 mov r7, r1 @ save architecture ID
143 mov r8, r2 @ save atags pointer
146 * Booting from Angel - need to enter SVC mode and disable
147 * FIQs/IRQs (numeric definitions from angel arm.h source).
148 * We only do this if we were in user mode on entry.
150 mrs r2, cpsr @ get current mode
151 tst r2, #3 @ not user?
153 mov r0, #0x17 @ angel_SWIreason_EnterSVC
154 ARM( swi 0x123456 ) @ angel_SWI_ARM
155 THUMB( svc 0xab ) @ angel_SWI_THUMB
157 safe_svcmode_maskall r0
158 msr spsr_cxsf, r9 @ Save the CPU boot mode in
161 * Note that some cache flushing and other stuff may
162 * be needed here - is there an Angel SWI call for this?
166 * some architecture specific code can be inserted
167 * by the linker here, but it should preserve r7, r8, and r9.
172 #ifdef CONFIG_AUTO_ZRELADDR
173 @ determine final kernel image address
175 and r4, r4, #0xf8000000
176 add r4, r4, #TEXT_OFFSET
182 * Set up a page table only if it won't overwrite ourself.
183 * That means r4 < pc && r4 - 16k page directory > &_end.
184 * Given that r4 > &_end is most unfrequent, we add a rough
185 * additional 1MB of room for a possible appended DTB.
192 orrcc r4, r4, #1 @ remember we skipped cache_on
196 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
200 * We might be running at a different address. We need
201 * to fix up various pointers.
203 sub r0, r0, r1 @ calculate the delta offset
204 add r6, r6, r0 @ _edata
205 add r10, r10, r0 @ inflated kernel size location
208 * The kernel build system appends the size of the
209 * decompressed kernel at the end of the compressed data
210 * in little-endian form.
214 orr r9, r9, lr, lsl #8
217 orr r9, r9, lr, lsl #16
218 orr r9, r9, r10, lsl #24
220 #ifndef CONFIG_ZBOOT_ROM
221 /* malloc space is above the relocated stack (64k max) */
223 add r10, sp, #0x10000
226 * With ZBOOT_ROM the bss/stack is non relocatable,
227 * but someone could still run this code from RAM,
228 * in which case our reference is _edata.
233 mov r5, #0 @ init dtb size to 0
234 #ifdef CONFIG_ARM_APPENDED_DTB
239 * r4 = final kernel address (possibly with LSB set)
240 * r5 = appended dtb size (still unknown)
242 * r7 = architecture ID
243 * r8 = atags/device tree pointer
244 * r9 = size of decompressed image
245 * r10 = end of this image, including bss/stack/malloc space if non XIP
250 * if there are device trees (dtb) appended to zImage, advance r10 so that the
251 * dtb data will get relocated along with the kernel if necessary.
256 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
261 bne dtb_check_done @ not found
263 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
265 * OK... Let's do some funky business here.
266 * If we do have a DTB appended to zImage, and we do have
267 * an ATAG list around, we want the later to be translated
268 * and folded into the former here. To be on the safe side,
269 * let's temporarily move the stack away into the malloc
270 * area. No GOT fixup has occurred yet, but none of the
271 * code we're about to call uses any global variable.
274 stmfd sp!, {r0-r3, ip, lr}
281 * If returned value is 1, there is no ATAG at the location
282 * pointed by r8. Try the typical 0x100 offset from start
283 * of RAM and hope for the best.
286 sub r0, r4, #TEXT_OFFSET
293 ldmfd sp!, {r0-r3, ip, lr}
297 mov r8, r6 @ use the appended device tree
300 * Make sure that the DTB doesn't end up in the final
301 * kernel's .bss area. To do so, we adjust the decompressed
302 * kernel size to compensate if that .bss size is larger
303 * than the relocated code.
305 ldr r5, =_kernel_bss_size
306 adr r1, wont_overwrite
311 /* Get the dtb's size */
314 /* convert r5 (dtb size) to little endian */
315 eor r1, r5, r5, ror #16
316 bic r1, r1, #0x00ff0000
318 eor r5, r5, r1, lsr #8
321 /* preserve 64-bit alignment */
325 /* relocate some pointers past the appended dtb */
333 * Check to see if we will overwrite ourselves.
334 * r4 = final kernel address (possibly with LSB set)
335 * r9 = size of decompressed image
336 * r10 = end of this image, including bss/stack/malloc space if non XIP
338 * r4 - 16k page directory >= r10 -> OK
339 * r4 + image length <= address of wont_overwrite -> OK
340 * Note: the possible LSB in r4 is harmless here.
346 adr r9, wont_overwrite
351 * Relocate ourselves past the end of the decompressed kernel.
353 * r10 = end of the decompressed kernel
354 * Because we always copy ahead, we need to do it from the end and go
355 * backward in case the source and destination overlap.
358 * Bump to the next 256-byte boundary with the size of
359 * the relocation code added. This avoids overwriting
360 * ourself when the offset is small.
362 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
365 /* Get start of code we want to copy and align it down. */
369 /* Relocate the hyp vector base if necessary */
370 #ifdef CONFIG_ARM_VIRT_EXT
372 and r0, r0, #MODE_MASK
383 sub r9, r6, r5 @ size to copy
384 add r9, r9, #31 @ rounded up to a multiple
385 bic r9, r9, #31 @ ... of 32 bytes
389 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
391 stmdb r9!, {r0 - r3, r10 - r12, lr}
394 /* Preserve offset to relocated code. */
397 #ifndef CONFIG_ZBOOT_ROM
398 /* cache_clean_flush may use the stack, so relocate it */
403 bleq cache_clean_flush
405 adr r0, BSYM(restart)
411 * If delta is zero, we are running at the address we were linked at.
415 * r4 = kernel execution address (possibly with LSB set)
416 * r5 = appended dtb size (0 if not present)
417 * r7 = architecture ID
429 #ifndef CONFIG_ZBOOT_ROM
431 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
432 * we need to fix up pointers into the BSS region.
433 * Note that the stack pointer has already been fixed up.
439 * Relocate all entries in the GOT table.
440 * Bump bss entries to _edata + dtb size
442 1: ldr r1, [r11, #0] @ relocate entries in the GOT
443 add r1, r1, r0 @ This fixes up C references
444 cmp r1, r2 @ if entry >= bss_start &&
445 cmphs r3, r1 @ bss_end > entry
446 addhi r1, r1, r5 @ entry += dtb size
447 str r1, [r11], #4 @ next entry
451 /* bump our bss pointers too */
458 * Relocate entries in the GOT table. We only relocate
459 * the entries that are outside the (relocated) BSS region.
461 1: ldr r1, [r11, #0] @ relocate entries in the GOT
462 cmp r1, r2 @ entry < bss_start ||
463 cmphs r3, r1 @ _end < entry
464 addlo r1, r1, r0 @ table. This fixes up the
465 str r1, [r11], #4 @ C references.
470 not_relocated: mov r0, #0
471 1: str r0, [r2], #4 @ clear bss
479 * Did we skip the cache setup earlier?
480 * That is indicated by the LSB in r4.
488 * The C runtime environment should now be setup sufficiently.
489 * Set up some pointers, and start decompressing.
490 * r4 = kernel execution address
491 * r7 = architecture ID
495 mov r1, sp @ malloc space above stack
496 add r2, sp, #0x10000 @ 64k max
501 mov r1, r7 @ restore architecture number
502 mov r2, r8 @ restore atags pointer
504 #ifdef CONFIG_ARM_VIRT_EXT
505 mrs r0, spsr @ Get saved CPU boot mode
506 and r0, r0, #MODE_MASK
507 cmp r0, #HYP_MODE @ if not booted in HYP mode...
508 bne __enter_kernel @ boot kernel directly
510 adr r12, .L__hyp_reentry_vectors_offset
515 __HVC(0) @ otherwise bounce to hyp mode
517 b . @ should never be reached
520 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
528 .word __bss_start @ r2
531 .word input_data_end - 4 @ r10 (inflated size location)
532 .word _got_start @ r11
534 .word .L_user_stack_end @ sp
535 .word _end - restart + 16384 + 1024*1024
538 #ifdef CONFIG_ARCH_RPC
540 params: ldr r0, =0x10000100 @ params_phys for RPC
547 * Turn on the cache. We need to setup some page tables so that we
548 * can have both the I and D caches on.
550 * We place the page tables 16k down from the kernel execution address,
551 * and we hope that nothing else is using it. If we're using it, we
555 * r4 = kernel execution address
556 * r7 = architecture number
559 * r0, r1, r2, r3, r9, r10, r12 corrupted
560 * This routine must preserve:
564 cache_on: mov r3, #8 @ cache_on function
568 * Initialize the highest priority protection region, PR7
569 * to cover all 32bit address and cacheable and bufferable.
571 __armv4_mpu_cache_on:
572 mov r0, #0x3f @ 4G, the whole
573 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
574 mcr p15, 0, r0, c6, c7, 1
577 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
578 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
579 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
582 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
583 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
586 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
587 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
588 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
589 mrc p15, 0, r0, c1, c0, 0 @ read control reg
590 @ ...I .... ..D. WC.M
591 orr r0, r0, #0x002d @ .... .... ..1. 11.1
592 orr r0, r0, #0x1000 @ ...1 .... .... ....
594 mcr p15, 0, r0, c1, c0, 0 @ write control reg
597 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
598 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
601 __armv3_mpu_cache_on:
602 mov r0, #0x3f @ 4G, the whole
603 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
606 mcr p15, 0, r0, c2, c0, 0 @ cache on
607 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
610 mcr p15, 0, r0, c5, c0, 0 @ access permission
613 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
615 * ?? ARMv3 MMU does not allow reading the control register,
616 * does this really work on ARMv3 MPU?
618 mrc p15, 0, r0, c1, c0, 0 @ read control reg
619 @ .... .... .... WC.M
620 orr r0, r0, #0x000d @ .... .... .... 11.1
621 /* ?? this overwrites the value constructed above? */
623 mcr p15, 0, r0, c1, c0, 0 @ write control reg
625 /* ?? invalidate for the second time? */
626 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
629 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
635 __setup_mmu: sub r3, r4, #16384 @ Page directory size
636 bic r3, r3, #0xff @ Align the pointer
639 * Initialise the page tables, turning on the cacheable and bufferable
640 * bits for the RAM area only.
644 mov r9, r9, lsl #18 @ start of RAM
645 add r10, r9, #0x10000000 @ a reasonable RAM size
646 mov r1, #0x12 @ XN|U + section mapping
647 orr r1, r1, #3 << 10 @ AP=11
649 1: cmp r1, r9 @ if virt > start of RAM
650 cmphs r10, r1 @ && end of RAM > virt
651 bic r1, r1, #0x1c @ clear XN|U + C + B
652 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
653 orrhs r1, r1, r6 @ set RAM section settings
654 str r1, [r0], #4 @ 1:1 mapping
659 * If ever we are running from Flash, then we surely want the cache
660 * to be enabled also for our execution instance... We map 2MB of it
661 * so there is no map overlap problem for up to 1 MB compressed kernel.
662 * If the execution is in RAM then we would only be duplicating the above.
664 orr r1, r6, #0x04 @ ensure B is set for this
668 orr r1, r1, r2, lsl #20
669 add r0, r3, r2, lsl #2
676 @ Enable unaligned access on v6, to allow better code generation
677 @ for the decompressor C code:
678 __armv6_mmu_cache_on:
679 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
680 bic r0, r0, #2 @ A (no unaligned access fault)
681 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
682 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
683 b __armv4_mmu_cache_on
685 __arm926ejs_mmu_cache_on:
686 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
687 mov r0, #4 @ put dcache in WT mode
688 mcr p15, 7, r0, c15, c0, 0
691 __armv4_mmu_cache_on:
694 mov r6, #CB_BITS | 0x12 @ U
697 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
698 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
699 mrc p15, 0, r0, c1, c0, 0 @ read control reg
700 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
702 #ifdef CONFIG_CPU_ENDIAN_BE8
703 orr r0, r0, #1 << 25 @ big-endian page tables
705 bl __common_mmu_cache_on
707 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
711 __armv7_mmu_cache_on:
714 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
716 movne r6, #CB_BITS | 0x02 @ !XN
719 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
721 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
723 mrc p15, 0, r0, c1, c0, 0 @ read control reg
724 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
725 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
726 orr r0, r0, #0x003c @ write buffer
727 bic r0, r0, #2 @ A (no unaligned access fault)
728 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
729 @ (needed for ARM1176)
731 #ifdef CONFIG_CPU_ENDIAN_BE8
732 orr r0, r0, #1 << 25 @ big-endian page tables
734 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
735 orrne r0, r0, #1 @ MMU enabled
736 movne r1, #0xfffffffd @ domain 0 = client
737 bic r6, r6, #1 << 31 @ 32-bit translation system
738 bic r6, r6, #3 << 0 @ use only ttbr0
739 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
740 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
741 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
743 mcr p15, 0, r0, c7, c5, 4 @ ISB
744 mcr p15, 0, r0, c1, c0, 0 @ load control register
745 mrc p15, 0, r0, c1, c0, 0 @ and read it back
747 mcr p15, 0, r0, c7, c5, 4 @ ISB
752 mov r6, #CB_BITS | 0x12 @ U
755 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
756 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
757 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
758 mrc p15, 0, r0, c1, c0, 0 @ read control reg
759 orr r0, r0, #0x1000 @ I-cache enable
760 bl __common_mmu_cache_on
762 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
765 __common_mmu_cache_on:
766 #ifndef CONFIG_THUMB2_KERNEL
768 orr r0, r0, #0x000d @ Write buffer, mmu
771 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
772 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
774 .align 5 @ cache line aligned
775 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
776 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
777 sub pc, lr, r0, lsr #32 @ properly flush pipeline
780 #define PROC_ENTRY_SIZE (4*5)
783 * Here follow the relocatable cache support functions for the
784 * various processors. This is a generic hook for locating an
785 * entry and jumping to an instruction at the specified offset
786 * from the start of the block. Please note this is all position
796 call_cache_fn: adr r12, proc_types
797 #ifdef CONFIG_CPU_CP15
798 mrc p15, 0, r9, c0, c0 @ get processor ID
800 ldr r9, =CONFIG_PROCESSOR_ID
802 1: ldr r1, [r12, #0] @ get value
803 ldr r2, [r12, #4] @ get mask
804 eor r1, r1, r9 @ (real ^ match)
806 ARM( addeq pc, r12, r3 ) @ call cache function
807 THUMB( addeq r12, r3 )
808 THUMB( moveq pc, r12 ) @ call cache function
809 add r12, r12, #PROC_ENTRY_SIZE
813 * Table for cache operations. This is basically:
816 * - 'cache on' method instruction
817 * - 'cache off' method instruction
818 * - 'cache flush' method instruction
820 * We match an entry using: ((real_id ^ match) & mask) == 0
822 * Writethrough caches generally only need 'on' and 'off'
823 * methods. Writeback caches _must_ have the flush method
827 .type proc_types,#object
829 .word 0x41000000 @ old ARM ID
838 .word 0x41007000 @ ARM7/710
847 .word 0x41807200 @ ARM720T (writethrough)
849 W(b) __armv4_mmu_cache_on
850 W(b) __armv4_mmu_cache_off
854 .word 0x41007400 @ ARM74x
856 W(b) __armv3_mpu_cache_on
857 W(b) __armv3_mpu_cache_off
858 W(b) __armv3_mpu_cache_flush
860 .word 0x41009400 @ ARM94x
862 W(b) __armv4_mpu_cache_on
863 W(b) __armv4_mpu_cache_off
864 W(b) __armv4_mpu_cache_flush
866 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
868 W(b) __arm926ejs_mmu_cache_on
869 W(b) __armv4_mmu_cache_off
870 W(b) __armv5tej_mmu_cache_flush
872 .word 0x00007000 @ ARM7 IDs
881 @ Everything from here on will be the new ID system.
883 .word 0x4401a100 @ sa110 / sa1100
885 W(b) __armv4_mmu_cache_on
886 W(b) __armv4_mmu_cache_off
887 W(b) __armv4_mmu_cache_flush
889 .word 0x6901b110 @ sa1110
891 W(b) __armv4_mmu_cache_on
892 W(b) __armv4_mmu_cache_off
893 W(b) __armv4_mmu_cache_flush
896 .word 0xffffff00 @ PXA9xx
897 W(b) __armv4_mmu_cache_on
898 W(b) __armv4_mmu_cache_off
899 W(b) __armv4_mmu_cache_flush
901 .word 0x56158000 @ PXA168
903 W(b) __armv4_mmu_cache_on
904 W(b) __armv4_mmu_cache_off
905 W(b) __armv5tej_mmu_cache_flush
907 .word 0x56050000 @ Feroceon
909 W(b) __armv4_mmu_cache_on
910 W(b) __armv4_mmu_cache_off
911 W(b) __armv5tej_mmu_cache_flush
913 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
914 /* this conflicts with the standard ARMv5TE entry */
915 .long 0x41009260 @ Old Feroceon
917 b __armv4_mmu_cache_on
918 b __armv4_mmu_cache_off
919 b __armv5tej_mmu_cache_flush
922 .word 0x66015261 @ FA526
924 W(b) __fa526_cache_on
925 W(b) __armv4_mmu_cache_off
926 W(b) __fa526_cache_flush
928 @ These match on the architecture ID
930 .word 0x00020000 @ ARMv4T
932 W(b) __armv4_mmu_cache_on
933 W(b) __armv4_mmu_cache_off
934 W(b) __armv4_mmu_cache_flush
936 .word 0x00050000 @ ARMv5TE
938 W(b) __armv4_mmu_cache_on
939 W(b) __armv4_mmu_cache_off
940 W(b) __armv4_mmu_cache_flush
942 .word 0x00060000 @ ARMv5TEJ
944 W(b) __armv4_mmu_cache_on
945 W(b) __armv4_mmu_cache_off
946 W(b) __armv5tej_mmu_cache_flush
948 .word 0x0007b000 @ ARMv6
950 W(b) __armv6_mmu_cache_on
951 W(b) __armv4_mmu_cache_off
952 W(b) __armv6_mmu_cache_flush
954 .word 0x000f0000 @ new CPU Id
956 W(b) __armv7_mmu_cache_on
957 W(b) __armv7_mmu_cache_off
958 W(b) __armv7_mmu_cache_flush
960 .word 0 @ unrecognised type
969 .size proc_types, . - proc_types
972 * If you get a "non-constant expression in ".if" statement"
973 * error from the assembler on this line, check that you have
974 * not accidentally written a "b" instruction where you should
977 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
978 .error "The size of one or more proc_types entries is wrong."
982 * Turn off the Cache and MMU. ARMv3 does not support
983 * reading the control register, but ARMv4 does.
986 * r0, r1, r2, r3, r9, r12 corrupted
987 * This routine must preserve:
991 cache_off: mov r3, #12 @ cache_off function
994 __armv4_mpu_cache_off:
995 mrc p15, 0, r0, c1, c0
997 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
999 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1000 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1001 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1004 __armv3_mpu_cache_off:
1005 mrc p15, 0, r0, c1, c0
1007 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1009 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1012 __armv4_mmu_cache_off:
1014 mrc p15, 0, r0, c1, c0
1016 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1018 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1019 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1023 __armv7_mmu_cache_off:
1024 mrc p15, 0, r0, c1, c0
1030 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1032 bl __armv7_mmu_cache_flush
1035 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1037 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1038 mcr p15, 0, r0, c7, c10, 4 @ DSB
1039 mcr p15, 0, r0, c7, c5, 4 @ ISB
1043 * Clean and flush the cache to maintain consistency.
1046 * r1, r2, r3, r9, r10, r11, r12 corrupted
1047 * This routine must preserve:
1055 __armv4_mpu_cache_flush:
1058 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1059 mov r1, #7 << 5 @ 8 segments
1060 1: orr r3, r1, #63 << 26 @ 64 entries
1061 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1062 subs r3, r3, #1 << 26
1063 bcs 2b @ entries 63 to 0
1064 subs r1, r1, #1 << 5
1065 bcs 1b @ segments 7 to 0
1068 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1069 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1072 __fa526_cache_flush:
1074 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1075 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1076 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1079 __armv6_mmu_cache_flush:
1081 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1082 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1083 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1084 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1087 __armv7_mmu_cache_flush:
1088 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1089 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1092 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1095 mcr p15, 0, r10, c7, c10, 5 @ DMB
1096 stmfd sp!, {r0-r7, r9-r11}
1097 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1098 ands r3, r0, #0x7000000 @ extract loc from clidr
1099 mov r3, r3, lsr #23 @ left align loc bit field
1100 beq finished @ if loc is 0, then no need to clean
1101 mov r10, #0 @ start clean at cache level 0
1103 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1104 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1105 and r1, r1, #7 @ mask of the bits for current cache only
1106 cmp r1, #2 @ see what cache we have at this level
1107 blt skip @ skip if no cache, or just i-cache
1108 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1109 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1110 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1111 and r2, r1, #7 @ extract the length of the cache lines
1112 add r2, r2, #4 @ add 4 (line length offset)
1114 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1115 clz r5, r4 @ find bit position of way size increment
1117 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1119 mov r9, r4 @ create working copy of max way size
1121 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1122 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1123 THUMB( lsl r6, r9, r5 )
1124 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1125 THUMB( lsl r6, r7, r2 )
1126 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1127 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1128 subs r9, r9, #1 @ decrement the way
1130 subs r7, r7, #1 @ decrement the index
1133 add r10, r10, #2 @ increment cache number
1137 ldmfd sp!, {r0-r7, r9-r11}
1138 mov r10, #0 @ swith back to cache level 0
1139 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1141 mcr p15, 0, r10, c7, c10, 4 @ DSB
1142 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1143 mcr p15, 0, r10, c7, c10, 4 @ DSB
1144 mcr p15, 0, r10, c7, c5, 4 @ ISB
1147 __armv5tej_mmu_cache_flush:
1148 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1150 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1151 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1154 __armv4_mmu_cache_flush:
1155 mov r2, #64*1024 @ default: 32K dcache size (*2)
1156 mov r11, #32 @ default: 32 byte line size
1157 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1158 teq r3, r9 @ cache ID register present?
1163 mov r2, r2, lsl r1 @ base dcache size *2
1164 tst r3, #1 << 14 @ test M bit
1165 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1169 mov r11, r11, lsl r3 @ cache line size in bytes
1172 bic r1, r1, #63 @ align to longest cache line
1175 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1176 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1177 THUMB( add r1, r1, r11 )
1181 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1182 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1183 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1186 __armv3_mmu_cache_flush:
1187 __armv3_mpu_cache_flush:
1189 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1193 * Various debugging routines for printing hex characters and
1194 * memory, which again must be relocatable.
1198 .type phexbuf,#object
1200 .size phexbuf, . - phexbuf
1202 @ phex corrupts {r0, r1, r2, r3}
1203 phex: adr r3, phexbuf
1217 @ puts corrupts {r0, r1, r2, r3}
1219 1: ldrb r2, [r0], #1
1232 @ putc corrupts {r0, r1, r2, r3}
1239 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1240 memdump: mov r12, r0
1243 2: mov r0, r11, lsl #2
1251 ldr r0, [r12, r11, lsl #2]
1271 #ifdef CONFIG_ARM_VIRT_EXT
1273 __hyp_reentry_vectors:
1279 W(b) __enter_kernel @ hyp
1282 #endif /* CONFIG_ARM_VIRT_EXT */
1285 mov r0, #0 @ must be 0
1286 ARM( mov pc, r4 ) @ call kernel
1287 THUMB( bx r4 ) @ entry point is always ARM
1292 .section ".stack", "aw", %nobits
1293 .L_user_stack: .space 4096