| blob | 6a1117e481b1ebebeac1a7cad047b29092877da3 |
1 /*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include "exynos5.dtsi"
21 #include "exynos5250-pinctrl.dtsi"
23 #include <dt-bindings/clk/exynos-audss-clk.h>
25 / {
26 compatible = "samsung,exynos5250";
28 aliases {
29 spi0 = &spi_0;
30 spi1 = &spi_1;
31 spi2 = &spi_2;
32 gsc0 = &gsc_0;
33 gsc1 = &gsc_1;
34 gsc2 = &gsc_2;
35 gsc3 = &gsc_3;
36 mshc0 = &dwmmc_0;
37 mshc1 = &dwmmc_1;
38 mshc2 = &dwmmc_2;
39 mshc3 = &dwmmc_3;
40 i2c0 = &i2c_0;
41 i2c1 = &i2c_1;
42 i2c2 = &i2c_2;
43 i2c3 = &i2c_3;
44 i2c4 = &i2c_4;
45 i2c5 = &i2c_5;
46 i2c6 = &i2c_6;
47 i2c7 = &i2c_7;
48 i2c8 = &i2c_8;
49 pinctrl0 = &pinctrl_0;
50 pinctrl1 = &pinctrl_1;
51 pinctrl2 = &pinctrl_2;
52 pinctrl3 = &pinctrl_3;
53 };
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
59 cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0>;
63 };
64 cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 };
69 };
71 pd_gsc: gsc-power-domain@10044000 {
72 compatible = "samsung,exynos4210-pd";
73 reg = <0x10044000 0x20>;
74 };
76 pd_mfc: mfc-power-domain@10044040 {
77 compatible = "samsung,exynos4210-pd";
78 reg = <0x10044040 0x20>;
79 };
81 clock: clock-controller@10010000 {
82 compatible = "samsung,exynos5250-clock";
83 reg = <0x10010000 0x30000>;
84 #clock-cells = <1>;
85 };
87 clock_audss: audss-clock-controller@3810000 {
88 compatible = "samsung,exynos5250-audss-clock";
89 reg = <0x03810000 0x0C>;
90 #clock-cells = <1>;
91 };
93 timer {
94 compatible = "arm,armv7-timer";
95 interrupts = <1 13 0xf08>,
96 <1 14 0xf08>,
97 <1 11 0xf08>,
98 <1 10 0xf08>;
99 /* Unfortunately we need this since some versions of U-Boot
100 * on Exynos don't set the CNTFRQ register, so we need the
101 * value from DT.
102 */
103 clock-frequency = <24000000>;
104 };
106 mct@101C0000 {
107 compatible = "samsung,exynos4210-mct";
108 reg = <0x101C0000 0x800>;
109 interrupt-controller;
110 #interrups-cells = <2>;
111 interrupt-parent = <&mct_map>;
112 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
113 <4 0>, <5 0>;
114 clocks = <&clock 1>, <&clock 335>;
115 clock-names = "fin_pll", "mct";
117 mct_map: mct-map {
118 #interrupt-cells = <2>;
119 #address-cells = <0>;
120 #size-cells = <0>;
121 interrupt-map = <0x0 0 &combiner 23 3>,
122 <0x1 0 &combiner 23 4>,
123 <0x2 0 &combiner 25 2>,
124 <0x3 0 &combiner 25 3>,
125 <0x4 0 &gic 0 120 0>,
126 <0x5 0 &gic 0 121 0>;
127 };
128 };
130 pmu {
131 compatible = "arm,cortex-a15-pmu";
132 interrupt-parent = <&combiner>;
133 interrupts = <1 2>, <22 4>;
134 };
136 pinctrl_0: pinctrl@11400000 {
137 compatible = "samsung,exynos5250-pinctrl";
138 reg = <0x11400000 0x1000>;
139 interrupts = <0 46 0>;
141 wakup_eint: wakeup-interrupt-controller {
142 compatible = "samsung,exynos4210-wakeup-eint";
143 interrupt-parent = <&gic>;
144 interrupts = <0 32 0>;
145 };
146 };
148 pinctrl_1: pinctrl@13400000 {
149 compatible = "samsung,exynos5250-pinctrl";
150 reg = <0x13400000 0x1000>;
151 interrupts = <0 45 0>;
152 };
154 pinctrl_2: pinctrl@10d10000 {
155 compatible = "samsung,exynos5250-pinctrl";
156 reg = <0x10d10000 0x1000>;
157 interrupts = <0 50 0>;
158 };
160 pinctrl_3: pinctrl@03860000 {
161 compatible = "samsung,exynos5250-pinctrl";
162 reg = <0x03860000 0x1000>;
163 interrupts = <0 47 0>;
164 };
166 watchdog {
167 clocks = <&clock 336>;
168 clock-names = "watchdog";
169 };
171 g2d@10850000 {
172 compatible = "samsung,exynos5250-g2d";
173 reg = <0x10850000 0x1000>;
174 interrupts = <0 91 0>;
175 clocks = <&clock 345>;
176 clock-names = "fimg2d";
177 };
179 codec@11000000 {
180 compatible = "samsung,mfc-v6";
181 reg = <0x11000000 0x10000>;
182 interrupts = <0 96 0>;
183 samsung,power-domain = <&pd_mfc>;
184 clocks = <&clock 266>;
185 clock-names = "mfc";
186 };
188 rtc@101E0000 {
189 clocks = <&clock 337>;
190 clock-names = "rtc";
191 status = "okay";
192 };
194 tmu@10060000 {
195 compatible = "samsung,exynos5250-tmu";
196 reg = <0x10060000 0x100>;
197 interrupts = <0 65 0>;
198 clocks = <&clock 338>;
199 clock-names = "tmu_apbif";
200 };
202 serial@12C00000 {
203 clocks = <&clock 289>, <&clock 146>;
204 clock-names = "uart", "clk_uart_baud0";
205 };
207 serial@12C10000 {
208 clocks = <&clock 290>, <&clock 147>;
209 clock-names = "uart", "clk_uart_baud0";
210 };
212 serial@12C20000 {
213 clocks = <&clock 291>, <&clock 148>;
214 clock-names = "uart", "clk_uart_baud0";
215 };
217 serial@12C30000 {
218 clocks = <&clock 292>, <&clock 149>;
219 clock-names = "uart", "clk_uart_baud0";
220 };
222 sata@122F0000 {
223 compatible = "samsung,exynos5-sata-ahci";
224 reg = <0x122F0000 0x1ff>;
225 interrupts = <0 115 0>;
226 clocks = <&clock 277>, <&clock 143>;
227 clock-names = "sata", "sclk_sata";
228 };
230 sata-phy@12170000 {
231 compatible = "samsung,exynos5-sata-phy";
232 reg = <0x12170000 0x1ff>;
233 };
235 i2c_0: i2c@12C60000 {
236 compatible = "samsung,s3c2440-i2c";
237 reg = <0x12C60000 0x100>;
238 interrupts = <0 56 0>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 clocks = <&clock 294>;
242 clock-names = "i2c";
243 pinctrl-names = "default";
244 pinctrl-0 = <&i2c0_bus>;
245 };
247 i2c_1: i2c@12C70000 {
248 compatible = "samsung,s3c2440-i2c";
249 reg = <0x12C70000 0x100>;
250 interrupts = <0 57 0>;
251 #address-cells = <1>;
252 #size-cells = <0>;
253 clocks = <&clock 295>;
254 clock-names = "i2c";
255 pinctrl-names = "default";
256 pinctrl-0 = <&i2c1_bus>;
257 };
259 i2c_2: i2c@12C80000 {
260 compatible = "samsung,s3c2440-i2c";
261 reg = <0x12C80000 0x100>;
262 interrupts = <0 58 0>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 clocks = <&clock 296>;
266 clock-names = "i2c";
267 pinctrl-names = "default";
268 pinctrl-0 = <&i2c2_bus>;
269 };
271 i2c_3: i2c@12C90000 {
272 compatible = "samsung,s3c2440-i2c";
273 reg = <0x12C90000 0x100>;
274 interrupts = <0 59 0>;
275 #address-cells = <1>;
276 #size-cells = <0>;
277 clocks = <&clock 297>;
278 clock-names = "i2c";
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c3_bus>;
281 };
283 i2c_4: i2c@12CA0000 {
284 compatible = "samsung,s3c2440-i2c";
285 reg = <0x12CA0000 0x100>;
286 interrupts = <0 60 0>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 clocks = <&clock 298>;
290 clock-names = "i2c";
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c4_bus>;
293 };
295 i2c_5: i2c@12CB0000 {
296 compatible = "samsung,s3c2440-i2c";
297 reg = <0x12CB0000 0x100>;
298 interrupts = <0 61 0>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 clocks = <&clock 299>;
302 clock-names = "i2c";
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c5_bus>;
305 };
307 i2c_6: i2c@12CC0000 {
308 compatible = "samsung,s3c2440-i2c";
309 reg = <0x12CC0000 0x100>;
310 interrupts = <0 62 0>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 clocks = <&clock 300>;
314 clock-names = "i2c";
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c6_bus>;
317 };
319 i2c_7: i2c@12CD0000 {
320 compatible = "samsung,s3c2440-i2c";
321 reg = <0x12CD0000 0x100>;
322 interrupts = <0 63 0>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 clocks = <&clock 301>;
326 clock-names = "i2c";
327 pinctrl-names = "default";
328 pinctrl-0 = <&i2c7_bus>;
329 };
331 i2c_8: i2c@12CE0000 {
332 compatible = "samsung,s3c2440-hdmiphy-i2c";
333 reg = <0x12CE0000 0x1000>;
334 interrupts = <0 64 0>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 clocks = <&clock 302>;
338 clock-names = "i2c";
339 };
341 i2c@121D0000 {
342 compatible = "samsung,exynos5-sata-phy-i2c";
343 reg = <0x121D0000 0x100>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clocks = <&clock 288>;
347 clock-names = "i2c";
348 };
350 spi_0: spi@12d20000 {
351 compatible = "samsung,exynos4210-spi";
352 reg = <0x12d20000 0x100>;
353 interrupts = <0 66 0>;
354 dmas = <&pdma0 5
355 &pdma0 4>;
356 dma-names = "tx", "rx";
357 #address-cells = <1>;
358 #size-cells = <0>;
359 clocks = <&clock 304>, <&clock 154>;
360 clock-names = "spi", "spi_busclk0";
361 pinctrl-names = "default";
362 pinctrl-0 = <&spi0_bus>;
363 };
365 spi_1: spi@12d30000 {
366 compatible = "samsung,exynos4210-spi";
367 reg = <0x12d30000 0x100>;
368 interrupts = <0 67 0>;
369 dmas = <&pdma1 5
370 &pdma1 4>;
371 dma-names = "tx", "rx";
372 #address-cells = <1>;
373 #size-cells = <0>;
374 clocks = <&clock 305>, <&clock 155>;
375 clock-names = "spi", "spi_busclk0";
376 pinctrl-names = "default";
377 pinctrl-0 = <&spi1_bus>;
378 };
380 spi_2: spi@12d40000 {
381 compatible = "samsung,exynos4210-spi";
382 reg = <0x12d40000 0x100>;
383 interrupts = <0 68 0>;
384 dmas = <&pdma0 7
385 &pdma0 6>;
386 dma-names = "tx", "rx";
387 #address-cells = <1>;
388 #size-cells = <0>;
389 clocks = <&clock 306>, <&clock 156>;
390 clock-names = "spi", "spi_busclk0";
391 pinctrl-names = "default";
392 pinctrl-0 = <&spi2_bus>;
393 };
395 dwmmc_0: dwmmc0@12200000 {
396 reg = <0x12200000 0x1000>;
397 clocks = <&clock 280>, <&clock 139>;
398 clock-names = "biu", "ciu";
399 };
401 dwmmc_1: dwmmc1@12210000 {
402 reg = <0x12210000 0x1000>;
403 clocks = <&clock 281>, <&clock 140>;
404 clock-names = "biu", "ciu";
405 };
407 dwmmc_2: dwmmc2@12220000 {
408 reg = <0x12220000 0x1000>;
409 clocks = <&clock 282>, <&clock 141>;
410 clock-names = "biu", "ciu";
411 };
413 dwmmc_3: dwmmc3@12230000 {
414 compatible = "samsung,exynos5250-dw-mshc";
415 reg = <0x12230000 0x1000>;
416 interrupts = <0 78 0>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 clocks = <&clock 283>, <&clock 142>;
420 clock-names = "biu", "ciu";
421 };
423 i2s0: i2s@03830000 {
424 compatible = "samsung,s5pv210-i2s";
425 reg = <0x03830000 0x100>;
426 dmas = <&pdma0 10
427 &pdma0 9
428 &pdma0 8>;
429 dma-names = "tx", "rx", "tx-sec";
430 clocks = <&clock_audss EXYNOS_I2S_BUS>,
431 <&clock_audss EXYNOS_I2S_BUS>,
432 <&clock_audss EXYNOS_SCLK_I2S>;
433 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
434 samsung,idma-addr = <0x03000000>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2s0_bus>;
437 };
439 i2s1: i2s@12D60000 {
440 compatible = "samsung,s3c6410-i2s";
441 reg = <0x12D60000 0x100>;
442 dmas = <&pdma1 12
443 &pdma1 11>;
444 dma-names = "tx", "rx";
445 clocks = <&clock 307>, <&clock 157>;
446 clock-names = "iis", "i2s_opclk0";
447 pinctrl-names = "default";
448 pinctrl-0 = <&i2s1_bus>;
449 };
451 i2s2: i2s@12D70000 {
452 compatible = "samsung,s3c6410-i2s";
453 reg = <0x12D70000 0x100>;
454 dmas = <&pdma0 12
455 &pdma0 11>;
456 dma-names = "tx", "rx";
457 clocks = <&clock 308>, <&clock 158>;
458 clock-names = "iis", "i2s_opclk0";
459 pinctrl-names = "default";
460 pinctrl-0 = <&i2s2_bus>;
461 };
463 usb@12000000 {
464 compatible = "samsung,exynos5250-dwusb3";
465 clocks = <&clock 286>;
466 clock-names = "usbdrd30";
467 #address-cells = <1>;
468 #size-cells = <1>;
469 ranges;
471 dwc3 {
472 compatible = "synopsys,dwc3";
473 reg = <0x12000000 0x10000>;
474 interrupts = <0 72 0>;
475 usb-phy = <&usb2_phy &usb3_phy>;
476 };
477 };
479 usb3_phy: usbphy@12100000 {
480 compatible = "samsung,exynos5250-usb3phy";
481 reg = <0x12100000 0x100>;
482 clocks = <&clock 1>, <&clock 286>;
483 clock-names = "ext_xtal", "usbdrd30";
484 #address-cells = <1>;
485 #size-cells = <1>;
486 ranges;
488 usbphy-sys {
489 reg = <0x10040704 0x8>;
490 };
491 };
493 usb@12110000 {
494 compatible = "samsung,exynos4210-ehci";
495 reg = <0x12110000 0x100>;
496 interrupts = <0 71 0>;
498 clocks = <&clock 285>;
499 clock-names = "usbhost";
500 };
502 usb@12120000 {
503 compatible = "samsung,exynos4210-ohci";
504 reg = <0x12120000 0x100>;
505 interrupts = <0 71 0>;
507 clocks = <&clock 285>;
508 clock-names = "usbhost";
509 };
511 usb2_phy: usbphy@12130000 {
512 compatible = "samsung,exynos5250-usb2phy";
513 reg = <0x12130000 0x100>;
514 clocks = <&clock 1>, <&clock 285>;
515 clock-names = "ext_xtal", "usbhost";
516 #address-cells = <1>;
517 #size-cells = <1>;
518 ranges;
520 usbphy-sys {
521 reg = <0x10040704 0x8>,
522 <0x10050230 0x4>;
523 };
524 };
526 amba {
527 #address-cells = <1>;
528 #size-cells = <1>;
529 compatible = "arm,amba-bus";
530 interrupt-parent = <&gic>;
531 ranges;
533 pdma0: pdma@121A0000 {
534 compatible = "arm,pl330", "arm,primecell";
535 reg = <0x121A0000 0x1000>;
536 interrupts = <0 34 0>;
537 clocks = <&clock 275>;
538 clock-names = "apb_pclk";
539 #dma-cells = <1>;
540 #dma-channels = <8>;
541 #dma-requests = <32>;
542 };
544 pdma1: pdma@121B0000 {
545 compatible = "arm,pl330", "arm,primecell";
546 reg = <0x121B0000 0x1000>;
547 interrupts = <0 35 0>;
548 clocks = <&clock 276>;
549 clock-names = "apb_pclk";
550 #dma-cells = <1>;
551 #dma-channels = <8>;
552 #dma-requests = <32>;
553 };
555 mdma0: mdma@10800000 {
556 compatible = "arm,pl330", "arm,primecell";
557 reg = <0x10800000 0x1000>;
558 interrupts = <0 33 0>;
559 clocks = <&clock 346>;
560 clock-names = "apb_pclk";
561 #dma-cells = <1>;
562 #dma-channels = <8>;
563 #dma-requests = <1>;
564 };
566 mdma1: mdma@11C10000 {
567 compatible = "arm,pl330", "arm,primecell";
568 reg = <0x11C10000 0x1000>;
569 interrupts = <0 124 0>;
570 clocks = <&clock 271>;
571 clock-names = "apb_pclk";
572 #dma-cells = <1>;
573 #dma-channels = <8>;
574 #dma-requests = <1>;
575 };
576 };
578 gsc_0: gsc@13e00000 {
579 compatible = "samsung,exynos5-gsc";
580 reg = <0x13e00000 0x1000>;
581 interrupts = <0 85 0>;
582 samsung,power-domain = <&pd_gsc>;
583 clocks = <&clock 256>;
584 clock-names = "gscl";
585 };
587 gsc_1: gsc@13e10000 {
588 compatible = "samsung,exynos5-gsc";
589 reg = <0x13e10000 0x1000>;
590 interrupts = <0 86 0>;
591 samsung,power-domain = <&pd_gsc>;
592 clocks = <&clock 257>;
593 clock-names = "gscl";
594 };
596 gsc_2: gsc@13e20000 {
597 compatible = "samsung,exynos5-gsc";
598 reg = <0x13e20000 0x1000>;
599 interrupts = <0 87 0>;
600 samsung,power-domain = <&pd_gsc>;
601 clocks = <&clock 258>;
602 clock-names = "gscl";
603 };
605 gsc_3: gsc@13e30000 {
606 compatible = "samsung,exynos5-gsc";
607 reg = <0x13e30000 0x1000>;
608 interrupts = <0 88 0>;
609 samsung,power-domain = <&pd_gsc>;
610 clocks = <&clock 259>;
611 clock-names = "gscl";
612 };
614 hdmi {
615 compatible = "samsung,exynos4212-hdmi";
616 reg = <0x14530000 0x70000>;
617 interrupts = <0 95 0>;
618 clocks = <&clock 333>, <&clock 136>, <&clock 137>,
619 <&clock 333>, <&clock 333>;
620 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
621 "sclk_hdmiphy", "hdmiphy";
622 };
624 mixer {
625 compatible = "samsung,exynos5250-mixer";
626 reg = <0x14450000 0x10000>;
627 interrupts = <0 94 0>;
628 };
630 dp_phy: video-phy@10040720 {
631 compatible = "samsung,exynos5250-dp-video-phy";
632 reg = <0x10040720 4>;
633 #phy-cells = <0>;
634 };
636 dp-controller@145B0000 {
637 clocks = <&clock 342>;
638 clock-names = "dp";
639 phys = <&dp_phy>;
640 phy-names = "dp";
641 };
643 fimd@14400000 {
644 clocks = <&clock 133>, <&clock 339>;
645 clock-names = "sclk_fimd", "fimd";
646 };
648 adc: adc@12D10000 {
649 compatible = "samsung,exynos-adc-v1";
650 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
651 interrupts = <0 106 0>;
652 clocks = <&clock 303>;
653 clock-names = "adc";
654 #io-channel-cells = <1>;
655 io-channel-ranges;
656 status = "disabled";
657 };
658 };