| blob | c07aea4f66cba8ba4c9b694af6d4e1b25be3228d |
1 /*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
12 #include "skeleton.dtsi"
14 / {
15 aliases {
16 gpio0 = &gpio1;
17 gpio1 = &gpio2;
18 gpio2 = &gpio3;
19 gpio3 = &gpio4;
20 gpio4 = &gpio5;
21 gpio5 = &gpio6;
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 serial4 = &uart5;
29 serial5 = &uart6;
30 spi0 = &cspi1;
31 spi1 = &cspi2;
32 spi2 = &cspi3;
33 ethernet0 = &fec;
34 };
36 aitc: aitc-interrupt-controller@e0000000 {
37 compatible = "fsl,imx27-aitc", "fsl,avic";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 reg = <0x10040000 0x1000>;
41 };
43 clocks {
44 #address-cells = <1>;
45 #size-cells = <0>;
47 osc26m {
48 compatible = "fsl,imx-osc26m", "fixed-clock";
49 clock-frequency = <26000000>;
50 };
51 };
53 cpus {
54 #size-cells = <0>;
55 #address-cells = <1>;
57 cpu: cpu@0 {
58 device_type = "cpu";
59 compatible = "arm,arm926ej-s";
60 operating-points = <
61 /* kHz uV */
62 266000 1300000
63 399000 1450000
64 >;
65 clock-latency = <62500>;
66 clocks = <&clks 18>;
67 voltage-tolerance = <5>;
68 };
69 };
71 soc {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "simple-bus";
75 interrupt-parent = <&aitc>;
76 ranges;
78 aipi@10000000 { /* AIPI1 */
79 compatible = "fsl,aipi-bus", "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x10000000 0x20000>;
83 ranges;
85 dma: dma@10001000 {
86 compatible = "fsl,imx27-dma";
87 reg = <0x10001000 0x1000>;
88 interrupts = <32>;
89 clocks = <&clks 50>, <&clks 70>;
90 clock-names = "ipg", "ahb";
91 #dma-cells = <1>;
92 #dma-channels = <16>;
93 };
95 wdog: wdog@10002000 {
96 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
97 reg = <0x10002000 0x1000>;
98 interrupts = <27>;
99 clocks = <&clks 74>;
100 };
102 gpt1: timer@10003000 {
103 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
104 reg = <0x10003000 0x1000>;
105 interrupts = <26>;
106 clocks = <&clks 46>, <&clks 61>;
107 clock-names = "ipg", "per";
108 };
110 gpt2: timer@10004000 {
111 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
112 reg = <0x10004000 0x1000>;
113 interrupts = <25>;
114 clocks = <&clks 45>, <&clks 61>;
115 clock-names = "ipg", "per";
116 };
118 gpt3: timer@10005000 {
119 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
120 reg = <0x10005000 0x1000>;
121 interrupts = <24>;
122 clocks = <&clks 44>, <&clks 61>;
123 clock-names = "ipg", "per";
124 };
126 pwm: pwm@10006000 {
127 compatible = "fsl,imx27-pwm";
128 reg = <0x10006000 0x1000>;
129 interrupts = <23>;
130 clocks = <&clks 34>, <&clks 61>;
131 clock-names = "ipg", "per";
132 };
134 kpp: kpp@10008000 {
135 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
136 reg = <0x10008000 0x1000>;
137 interrupts = <21>;
138 clocks = <&clks 37>;
139 status = "disabled";
140 };
142 owire: owire@10009000 {
143 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
144 reg = <0x10009000 0x1000>;
145 clocks = <&clks 35>;
146 status = "disabled";
147 };
149 uart1: serial@1000a000 {
150 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
151 reg = <0x1000a000 0x1000>;
152 interrupts = <20>;
153 clocks = <&clks 81>, <&clks 61>;
154 clock-names = "ipg", "per";
155 status = "disabled";
156 };
158 uart2: serial@1000b000 {
159 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
160 reg = <0x1000b000 0x1000>;
161 interrupts = <19>;
162 clocks = <&clks 80>, <&clks 61>;
163 clock-names = "ipg", "per";
164 status = "disabled";
165 };
167 uart3: serial@1000c000 {
168 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
169 reg = <0x1000c000 0x1000>;
170 interrupts = <18>;
171 clocks = <&clks 79>, <&clks 61>;
172 clock-names = "ipg", "per";
173 status = "disabled";
174 };
176 uart4: serial@1000d000 {
177 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
178 reg = <0x1000d000 0x1000>;
179 interrupts = <17>;
180 clocks = <&clks 78>, <&clks 61>;
181 clock-names = "ipg", "per";
182 status = "disabled";
183 };
185 cspi1: cspi@1000e000 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "fsl,imx27-cspi";
189 reg = <0x1000e000 0x1000>;
190 interrupts = <16>;
191 clocks = <&clks 53>, <&clks 60>;
192 clock-names = "ipg", "per";
193 status = "disabled";
194 };
196 cspi2: cspi@1000f000 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx27-cspi";
200 reg = <0x1000f000 0x1000>;
201 interrupts = <15>;
202 clocks = <&clks 52>, <&clks 60>;
203 clock-names = "ipg", "per";
204 status = "disabled";
205 };
207 i2c1: i2c@10012000 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
211 reg = <0x10012000 0x1000>;
212 interrupts = <12>;
213 clocks = <&clks 40>;
214 status = "disabled";
215 };
217 sdhci1: sdhci@10013000 {
218 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
219 reg = <0x10013000 0x1000>;
220 interrupts = <11>;
221 clocks = <&clks 30>, <&clks 60>;
222 clock-names = "ipg", "per";
223 dmas = <&dma 7>;
224 dma-names = "rx-tx";
225 status = "disabled";
226 };
228 sdhci2: sdhci@10014000 {
229 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
230 reg = <0x10014000 0x1000>;
231 interrupts = <10>;
232 clocks = <&clks 29>, <&clks 60>;
233 clock-names = "ipg", "per";
234 dmas = <&dma 6>;
235 dma-names = "rx-tx";
236 status = "disabled";
237 };
239 gpio1: gpio@10015000 {
240 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
241 reg = <0x10015000 0x100>;
242 interrupts = <8>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 interrupt-controller;
246 #interrupt-cells = <2>;
247 };
249 gpio2: gpio@10015100 {
250 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
251 reg = <0x10015100 0x100>;
252 interrupts = <8>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
257 };
259 gpio3: gpio@10015200 {
260 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
261 reg = <0x10015200 0x100>;
262 interrupts = <8>;
263 gpio-controller;
264 #gpio-cells = <2>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
267 };
269 gpio4: gpio@10015300 {
270 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
271 reg = <0x10015300 0x100>;
272 interrupts = <8>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 };
279 gpio5: gpio@10015400 {
280 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
281 reg = <0x10015400 0x100>;
282 interrupts = <8>;
283 gpio-controller;
284 #gpio-cells = <2>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
287 };
289 gpio6: gpio@10015500 {
290 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
291 reg = <0x10015500 0x100>;
292 interrupts = <8>;
293 gpio-controller;
294 #gpio-cells = <2>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 };
299 audmux: audmux@10016000 {
300 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
301 reg = <0x10016000 0x1000>;
302 clocks = <&clks 0>;
303 clock-names = "audmux";
304 status = "disabled";
305 };
307 cspi3: cspi@10017000 {
308 #address-cells = <1>;
309 #size-cells = <0>;
310 compatible = "fsl,imx27-cspi";
311 reg = <0x10017000 0x1000>;
312 interrupts = <6>;
313 clocks = <&clks 51>, <&clks 60>;
314 clock-names = "ipg", "per";
315 status = "disabled";
316 };
318 gpt4: timer@10019000 {
319 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
320 reg = <0x10019000 0x1000>;
321 interrupts = <4>;
322 clocks = <&clks 43>, <&clks 61>;
323 clock-names = "ipg", "per";
324 };
326 gpt5: timer@1001a000 {
327 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
328 reg = <0x1001a000 0x1000>;
329 interrupts = <3>;
330 clocks = <&clks 42>, <&clks 61>;
331 clock-names = "ipg", "per";
332 };
334 uart5: serial@1001b000 {
335 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
336 reg = <0x1001b000 0x1000>;
337 interrupts = <49>;
338 clocks = <&clks 77>, <&clks 61>;
339 clock-names = "ipg", "per";
340 status = "disabled";
341 };
343 uart6: serial@1001c000 {
344 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
345 reg = <0x1001c000 0x1000>;
346 interrupts = <48>;
347 clocks = <&clks 78>, <&clks 61>;
348 clock-names = "ipg", "per";
349 status = "disabled";
350 };
352 i2c2: i2c@1001d000 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
356 reg = <0x1001d000 0x1000>;
357 interrupts = <1>;
358 clocks = <&clks 39>;
359 status = "disabled";
360 };
362 sdhci3: sdhci@1001e000 {
363 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
364 reg = <0x1001e000 0x1000>;
365 interrupts = <9>;
366 clocks = <&clks 28>, <&clks 60>;
367 clock-names = "ipg", "per";
368 dmas = <&dma 36>;
369 dma-names = "rx-tx";
370 status = "disabled";
371 };
373 gpt6: timer@1001f000 {
374 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
375 reg = <0x1001f000 0x1000>;
376 interrupts = <2>;
377 clocks = <&clks 41>, <&clks 61>;
378 clock-names = "ipg", "per";
379 };
380 };
382 aipi@10020000 { /* AIPI2 */
383 compatible = "fsl,aipi-bus", "simple-bus";
384 #address-cells = <1>;
385 #size-cells = <1>;
386 reg = <0x10020000 0x20000>;
387 ranges;
389 fb: fb@10021000 {
390 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
391 interrupts = <61>;
392 reg = <0x10021000 0x1000>;
393 clocks = <&clks 36>, <&clks 65>, <&clks 59>;
394 clock-names = "ipg", "ahb", "per";
395 status = "disabled";
396 };
398 coda: coda@10023000 {
399 compatible = "fsl,imx27-vpu";
400 reg = <0x10023000 0x0200>;
401 interrupts = <53>;
402 clocks = <&clks 57>, <&clks 66>;
403 clock-names = "per", "ahb";
404 iram = <&iram>;
405 };
407 sahara2: sahara@10025000 {
408 compatible = "fsl,imx27-sahara";
409 reg = <0x10025000 0x1000>;
410 interrupts = <59>;
411 clocks = <&clks 32>, <&clks 64>;
412 clock-names = "ipg", "ahb";
413 };
415 clks: ccm@10027000{
416 compatible = "fsl,imx27-ccm";
417 reg = <0x10027000 0x1000>;
418 #clock-cells = <1>;
419 };
421 iim: iim@10028000 {
422 compatible = "fsl,imx27-iim";
423 reg = <0x10028000 0x1000>;
424 interrupts = <62>;
425 clocks = <&clks 38>;
426 };
428 fec: ethernet@1002b000 {
429 compatible = "fsl,imx27-fec";
430 reg = <0x1002b000 0x4000>;
431 interrupts = <50>;
432 clocks = <&clks 48>, <&clks 67>;
433 clock-names = "ipg", "ahb";
434 status = "disabled";
435 };
436 };
438 nfc: nand@d8000000 {
439 #address-cells = <1>;
440 #size-cells = <1>;
441 compatible = "fsl,imx27-nand";
442 reg = <0xd8000000 0x1000>;
443 interrupts = <29>;
444 clocks = <&clks 54>;
445 status = "disabled";
446 };
448 weim: weim@d8002000 {
449 #address-cells = <2>;
450 #size-cells = <1>;
451 compatible = "fsl,imx27-weim";
452 reg = <0xd8002000 0x1000>;
453 clocks = <&clks 0>;
454 ranges = <
455 0 0 0xc0000000 0x08000000
456 1 0 0xc8000000 0x08000000
457 2 0 0xd0000000 0x02000000
458 3 0 0xd2000000 0x02000000
459 4 0 0xd4000000 0x02000000
460 5 0 0xd6000000 0x02000000
461 >;
462 status = "disabled";
463 };
465 iram: iram@ffff4c00 {
466 compatible = "mmio-sram";
467 reg = <0xffff4c00 0xb400>;
468 };
469 };
470 };