| blob | 6d2a5343691ffabd9c95654d22addc5a746d9b8e |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
16 / {
17 aliases {
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 spi0 = &ecspi1;
28 spi1 = &ecspi2;
29 spi2 = &cspi;
30 ethernet0 = &fec;
31 };
33 tzic: tz-interrupt-controller@e0000000 {
34 compatible = "fsl,imx51-tzic", "fsl,tzic";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0xe0000000 0x4000>;
38 };
40 clocks {
41 #address-cells = <1>;
42 #size-cells = <0>;
44 ckil {
45 compatible = "fsl,imx-ckil", "fixed-clock";
46 clock-frequency = <32768>;
47 };
49 ckih1 {
50 compatible = "fsl,imx-ckih1", "fixed-clock";
51 clock-frequency = <0>;
52 };
54 ckih2 {
55 compatible = "fsl,imx-ckih2", "fixed-clock";
56 clock-frequency = <0>;
57 };
59 osc {
60 compatible = "fsl,imx-osc", "fixed-clock";
61 clock-frequency = <24000000>;
62 };
63 };
65 cpus {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 cpu@0 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a8";
71 reg = <0>;
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks 24>;
74 clock-names = "cpu";
75 operating-points = <
76 /* kHz uV (No regulator support) */
77 160000 0
78 800000 0
79 >;
80 };
81 };
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&tzic>;
88 ranges;
90 ipu: ipu@40000000 {
91 #crtc-cells = <1>;
92 compatible = "fsl,imx51-ipu";
93 reg = <0x40000000 0x20000000>;
94 interrupts = <11 10>;
95 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
96 clock-names = "bus", "di0", "di1";
97 resets = <&src 2>;
98 };
100 aips@70000000 { /* AIPS1 */
101 compatible = "fsl,aips-bus", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 reg = <0x70000000 0x10000000>;
105 ranges;
107 spba@70000000 {
108 compatible = "fsl,spba-bus", "simple-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 reg = <0x70000000 0x40000>;
112 ranges;
114 esdhc1: esdhc@70004000 {
115 compatible = "fsl,imx51-esdhc";
116 reg = <0x70004000 0x4000>;
117 interrupts = <1>;
118 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
119 clock-names = "ipg", "ahb", "per";
120 status = "disabled";
121 };
123 esdhc2: esdhc@70008000 {
124 compatible = "fsl,imx51-esdhc";
125 reg = <0x70008000 0x4000>;
126 interrupts = <2>;
127 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
128 clock-names = "ipg", "ahb", "per";
129 bus-width = <4>;
130 status = "disabled";
131 };
133 uart3: serial@7000c000 {
134 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
135 reg = <0x7000c000 0x4000>;
136 interrupts = <33>;
137 clocks = <&clks 32>, <&clks 33>;
138 clock-names = "ipg", "per";
139 status = "disabled";
140 };
142 ecspi1: ecspi@70010000 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 compatible = "fsl,imx51-ecspi";
146 reg = <0x70010000 0x4000>;
147 interrupts = <36>;
148 clocks = <&clks 51>, <&clks 52>;
149 clock-names = "ipg", "per";
150 status = "disabled";
151 };
153 ssi2: ssi@70014000 {
154 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
155 reg = <0x70014000 0x4000>;
156 interrupts = <30>;
157 clocks = <&clks 49>;
158 dmas = <&sdma 24 1 0>,
159 <&sdma 25 1 0>;
160 dma-names = "rx", "tx";
161 fsl,fifo-depth = <15>;
162 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
163 status = "disabled";
164 };
166 esdhc3: esdhc@70020000 {
167 compatible = "fsl,imx51-esdhc";
168 reg = <0x70020000 0x4000>;
169 interrupts = <3>;
170 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
171 clock-names = "ipg", "ahb", "per";
172 bus-width = <4>;
173 status = "disabled";
174 };
176 esdhc4: esdhc@70024000 {
177 compatible = "fsl,imx51-esdhc";
178 reg = <0x70024000 0x4000>;
179 interrupts = <4>;
180 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
181 clock-names = "ipg", "ahb", "per";
182 bus-width = <4>;
183 status = "disabled";
184 };
185 };
187 usbphy0: usbphy@0 {
188 compatible = "usb-nop-xceiv";
189 clocks = <&clks 124>;
190 clock-names = "main_clk";
191 status = "okay";
192 };
194 usbotg: usb@73f80000 {
195 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
196 reg = <0x73f80000 0x0200>;
197 interrupts = <18>;
198 clocks = <&clks 108>;
199 fsl,usbmisc = <&usbmisc 0>;
200 fsl,usbphy = <&usbphy0>;
201 status = "disabled";
202 };
204 usbh1: usb@73f80200 {
205 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
206 reg = <0x73f80200 0x0200>;
207 interrupts = <14>;
208 clocks = <&clks 108>;
209 fsl,usbmisc = <&usbmisc 1>;
210 status = "disabled";
211 };
213 usbh2: usb@73f80400 {
214 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
215 reg = <0x73f80400 0x0200>;
216 interrupts = <16>;
217 clocks = <&clks 108>;
218 fsl,usbmisc = <&usbmisc 2>;
219 status = "disabled";
220 };
222 usbh3: usb@73f80600 {
223 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
224 reg = <0x73f80600 0x0200>;
225 interrupts = <17>;
226 clocks = <&clks 108>;
227 fsl,usbmisc = <&usbmisc 3>;
228 status = "disabled";
229 };
231 usbmisc: usbmisc@73f80800 {
232 #index-cells = <1>;
233 compatible = "fsl,imx51-usbmisc";
234 reg = <0x73f80800 0x200>;
235 clocks = <&clks 108>;
236 };
238 gpio1: gpio@73f84000 {
239 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
240 reg = <0x73f84000 0x4000>;
241 interrupts = <50 51>;
242 gpio-controller;
243 #gpio-cells = <2>;
244 interrupt-controller;
245 #interrupt-cells = <2>;
246 };
248 gpio2: gpio@73f88000 {
249 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
250 reg = <0x73f88000 0x4000>;
251 interrupts = <52 53>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
256 };
258 gpio3: gpio@73f8c000 {
259 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
260 reg = <0x73f8c000 0x4000>;
261 interrupts = <54 55>;
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 };
268 gpio4: gpio@73f90000 {
269 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
270 reg = <0x73f90000 0x4000>;
271 interrupts = <56 57>;
272 gpio-controller;
273 #gpio-cells = <2>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 };
278 kpp: kpp@73f94000 {
279 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
280 reg = <0x73f94000 0x4000>;
281 interrupts = <60>;
282 clocks = <&clks 0>;
283 status = "disabled";
284 };
286 wdog1: wdog@73f98000 {
287 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
288 reg = <0x73f98000 0x4000>;
289 interrupts = <58>;
290 clocks = <&clks 0>;
291 };
293 wdog2: wdog@73f9c000 {
294 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
295 reg = <0x73f9c000 0x4000>;
296 interrupts = <59>;
297 clocks = <&clks 0>;
298 status = "disabled";
299 };
301 gpt: timer@73fa0000 {
302 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
303 reg = <0x73fa0000 0x4000>;
304 interrupts = <39>;
305 clocks = <&clks 36>, <&clks 41>;
306 clock-names = "ipg", "per";
307 };
309 iomuxc: iomuxc@73fa8000 {
310 compatible = "fsl,imx51-iomuxc";
311 reg = <0x73fa8000 0x4000>;
312 };
314 pwm1: pwm@73fb4000 {
315 #pwm-cells = <2>;
316 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
317 reg = <0x73fb4000 0x4000>;
318 clocks = <&clks 37>, <&clks 38>;
319 clock-names = "ipg", "per";
320 interrupts = <61>;
321 };
323 pwm2: pwm@73fb8000 {
324 #pwm-cells = <2>;
325 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
326 reg = <0x73fb8000 0x4000>;
327 clocks = <&clks 39>, <&clks 40>;
328 clock-names = "ipg", "per";
329 interrupts = <94>;
330 };
332 uart1: serial@73fbc000 {
333 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
334 reg = <0x73fbc000 0x4000>;
335 interrupts = <31>;
336 clocks = <&clks 28>, <&clks 29>;
337 clock-names = "ipg", "per";
338 status = "disabled";
339 };
341 uart2: serial@73fc0000 {
342 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
343 reg = <0x73fc0000 0x4000>;
344 interrupts = <32>;
345 clocks = <&clks 30>, <&clks 31>;
346 clock-names = "ipg", "per";
347 status = "disabled";
348 };
350 src: src@73fd0000 {
351 compatible = "fsl,imx51-src";
352 reg = <0x73fd0000 0x4000>;
353 #reset-cells = <1>;
354 };
356 clks: ccm@73fd4000{
357 compatible = "fsl,imx51-ccm";
358 reg = <0x73fd4000 0x4000>;
359 interrupts = <0 71 0x04 0 72 0x04>;
360 #clock-cells = <1>;
361 };
362 };
364 aips@80000000 { /* AIPS2 */
365 compatible = "fsl,aips-bus", "simple-bus";
366 #address-cells = <1>;
367 #size-cells = <1>;
368 reg = <0x80000000 0x10000000>;
369 ranges;
371 iim: iim@83f98000 {
372 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
373 reg = <0x83f98000 0x4000>;
374 interrupts = <69>;
375 clocks = <&clks 107>;
376 };
378 ecspi2: ecspi@83fac000 {
379 #address-cells = <1>;
380 #size-cells = <0>;
381 compatible = "fsl,imx51-ecspi";
382 reg = <0x83fac000 0x4000>;
383 interrupts = <37>;
384 clocks = <&clks 53>, <&clks 54>;
385 clock-names = "ipg", "per";
386 status = "disabled";
387 };
389 sdma: sdma@83fb0000 {
390 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
391 reg = <0x83fb0000 0x4000>;
392 interrupts = <6>;
393 clocks = <&clks 56>, <&clks 56>;
394 clock-names = "ipg", "ahb";
395 #dma-cells = <3>;
396 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
397 };
399 cspi: cspi@83fc0000 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
403 reg = <0x83fc0000 0x4000>;
404 interrupts = <38>;
405 clocks = <&clks 55>, <&clks 55>;
406 clock-names = "ipg", "per";
407 status = "disabled";
408 };
410 i2c2: i2c@83fc4000 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
414 reg = <0x83fc4000 0x4000>;
415 interrupts = <63>;
416 clocks = <&clks 35>;
417 status = "disabled";
418 };
420 i2c1: i2c@83fc8000 {
421 #address-cells = <1>;
422 #size-cells = <0>;
423 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
424 reg = <0x83fc8000 0x4000>;
425 interrupts = <62>;
426 clocks = <&clks 34>;
427 status = "disabled";
428 };
430 ssi1: ssi@83fcc000 {
431 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
432 reg = <0x83fcc000 0x4000>;
433 interrupts = <29>;
434 clocks = <&clks 48>;
435 dmas = <&sdma 28 0 0>,
436 <&sdma 29 0 0>;
437 dma-names = "rx", "tx";
438 fsl,fifo-depth = <15>;
439 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
440 status = "disabled";
441 };
443 audmux: audmux@83fd0000 {
444 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
445 reg = <0x83fd0000 0x4000>;
446 status = "disabled";
447 };
449 weim: weim@83fda000 {
450 #address-cells = <2>;
451 #size-cells = <1>;
452 compatible = "fsl,imx51-weim";
453 reg = <0x83fda000 0x1000>;
454 clocks = <&clks 57>;
455 ranges = <
456 0 0 0xb0000000 0x08000000
457 1 0 0xb8000000 0x08000000
458 2 0 0xc0000000 0x08000000
459 3 0 0xc8000000 0x04000000
460 4 0 0xcc000000 0x02000000
461 5 0 0xce000000 0x02000000
462 >;
463 status = "disabled";
464 };
466 nfc: nand@83fdb000 {
467 compatible = "fsl,imx51-nand";
468 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
469 interrupts = <8>;
470 clocks = <&clks 60>;
471 status = "disabled";
472 };
474 pata: pata@83fe0000 {
475 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
476 reg = <0x83fe0000 0x4000>;
477 interrupts = <70>;
478 clocks = <&clks 172>;
479 status = "disabled";
480 };
482 ssi3: ssi@83fe8000 {
483 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
484 reg = <0x83fe8000 0x4000>;
485 interrupts = <96>;
486 clocks = <&clks 50>;
487 dmas = <&sdma 46 0 0>,
488 <&sdma 47 0 0>;
489 dma-names = "rx", "tx";
490 fsl,fifo-depth = <15>;
491 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
492 status = "disabled";
493 };
495 fec: ethernet@83fec000 {
496 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
497 reg = <0x83fec000 0x4000>;
498 interrupts = <87>;
499 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
500 clock-names = "ipg", "ahb", "ptp";
501 status = "disabled";
502 };
503 };
504 };
505 };
507 &iomuxc {
508 audmux {
509 pinctrl_audmux_1: audmuxgrp-1 {
510 fsl,pins = <
511 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
512 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
513 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
514 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
515 >;
516 };
517 };
519 fec {
520 pinctrl_fec_1: fecgrp-1 {
521 fsl,pins = <
522 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
523 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
524 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
525 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
526 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
527 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
528 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
529 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
530 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
531 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
532 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
533 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
534 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
535 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
536 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
537 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
538 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
539 >;
540 };
542 pinctrl_fec_2: fecgrp-2 {
543 fsl,pins = <
544 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
545 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
546 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
547 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
548 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
549 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
550 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
551 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
552 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
553 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
554 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
555 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
556 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
557 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
558 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
559 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
560 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
561 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
562 >;
563 };
564 };
566 ecspi1 {
567 pinctrl_ecspi1_1: ecspi1grp-1 {
568 fsl,pins = <
569 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
570 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
571 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
572 >;
573 };
574 };
576 ecspi2 {
577 pinctrl_ecspi2_1: ecspi2grp-1 {
578 fsl,pins = <
579 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
580 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
581 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
582 >;
583 };
584 };
586 esdhc1 {
587 pinctrl_esdhc1_1: esdhc1grp-1 {
588 fsl,pins = <
589 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
590 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
591 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
592 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
593 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
594 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
595 >;
596 };
597 };
599 esdhc2 {
600 pinctrl_esdhc2_1: esdhc2grp-1 {
601 fsl,pins = <
602 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
603 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
604 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
605 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
606 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
607 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
608 >;
609 };
610 };
612 i2c2 {
613 pinctrl_i2c2_1: i2c2grp-1 {
614 fsl,pins = <
615 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
616 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
617 >;
618 };
620 pinctrl_i2c2_2: i2c2grp-2 {
621 fsl,pins = <
622 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
623 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
624 >;
625 };
627 pinctrl_i2c2_3: i2c2grp-3 {
628 fsl,pins = <
629 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
630 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
631 >;
632 };
633 };
635 ipu_disp1 {
636 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
637 fsl,pins = <
638 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
639 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
640 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
641 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
642 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
643 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
644 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
645 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
646 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
647 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
648 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
649 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
650 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
651 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
652 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
653 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
654 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
655 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
656 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
657 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
658 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
659 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
660 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
661 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
662 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
663 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
664 >;
665 };
666 };
668 ipu_disp2 {
669 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
670 fsl,pins = <
671 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
672 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
673 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
674 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
675 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
676 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
677 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
678 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
679 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
680 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
681 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
682 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
683 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
684 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
685 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
686 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
687 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
688 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
689 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
690 MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
691 >;
692 };
693 };
695 kpp {
696 pinctrl_kpp_1: kppgrp-1 {
697 fsl,pins = <
698 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
699 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
700 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
701 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
702 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
703 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
704 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
705 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
706 >;
707 };
708 };
710 pata {
711 pinctrl_pata_1: patagrp-1 {
712 fsl,pins = <
713 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
714 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
715 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
716 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
717 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
718 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
719 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
720 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
721 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
722 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
723 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
724 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
725 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
726 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
727 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
728 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
729 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
730 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
731 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
732 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
733 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
734 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
735 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
736 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
737 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
738 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
739 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
740 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
741 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
742 >;
743 };
744 };
746 uart1 {
747 pinctrl_uart1_1: uart1grp-1 {
748 fsl,pins = <
749 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
750 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
751 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
752 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
753 >;
754 };
755 };
757 uart2 {
758 pinctrl_uart2_1: uart2grp-1 {
759 fsl,pins = <
760 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
761 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
762 >;
763 };
764 };
766 uart3 {
767 pinctrl_uart3_1: uart3grp-1 {
768 fsl,pins = <
769 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
770 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
771 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
772 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
773 >;
774 };
776 pinctrl_uart3_2: uart3grp-2 {
777 fsl,pins = <
778 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
779 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
780 >;
781 };
782 };
784 usbh1 {
785 pinctrl_usbh1_1: usbh1grp-1 {
786 fsl,pins = <
787 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
788 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
789 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
790 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
791 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
792 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
793 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
794 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
795 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
796 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
797 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
798 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
799 >;
800 };
801 };
803 usbh2 {
804 pinctrl_usbh2_1: usbh2grp-1 {
805 fsl,pins = <
806 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
807 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
808 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
809 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
810 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
811 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
812 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
813 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
814 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
815 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
816 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
817 MX51_PAD_EIM_A26__USBH2_STP 0x1e5
818 >;
819 };
820 };
821 };