| blob | 9169d3025f39ed5fd2475f43f0d3cd261e71894d |
1 /*
2 * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
3 */
4 /include/ "skeleton.dtsi"
6 / {
7 #address-cells = <1>;
8 #size-cells = <1>;
10 memory {
11 reg = <0x00000000 0x04000000>,
12 <0x08000000 0x04000000>;
13 };
15 L2: l2-cache {
16 compatible = "arm,l210-cache";
17 reg = <0x10210000 0x1000>;
18 interrupt-parent = <&vica>;
19 interrupts = <30>;
20 cache-unified;
21 cache-level = <2>;
22 };
24 mtu0: mtu@101e2000 {
25 /* Nomadik system timer */
26 compatible = "st,nomadik-mtu";
27 reg = <0x101e2000 0x1000>;
28 interrupt-parent = <&vica>;
29 interrupts = <4>;
30 clocks = <&timclk>, <&pclk>;
31 clock-names = "timclk", "apb_pclk";
32 };
34 mtu1: mtu@101e3000 {
35 /* Secondary timer */
36 reg = <0x101e3000 0x1000>;
37 interrupt-parent = <&vica>;
38 interrupts = <5>;
39 clocks = <&timclk>, <&pclk>;
40 clock-names = "timclk", "apb_pclk";
41 };
43 gpio0: gpio@101e4000 {
44 compatible = "st,nomadik-gpio";
45 reg = <0x101e4000 0x80>;
46 interrupt-parent = <&vica>;
47 interrupts = <6>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
50 gpio-controller;
51 #gpio-cells = <2>;
52 gpio-bank = <0>;
53 clocks = <&pclk>;
54 };
56 gpio1: gpio@101e5000 {
57 compatible = "st,nomadik-gpio";
58 reg = <0x101e5000 0x80>;
59 interrupt-parent = <&vica>;
60 interrupts = <7>;
61 interrupt-controller;
62 #interrupt-cells = <2>;
63 gpio-controller;
64 #gpio-cells = <2>;
65 gpio-bank = <1>;
66 clocks = <&pclk>;
67 };
69 gpio2: gpio@101e6000 {
70 compatible = "st,nomadik-gpio";
71 reg = <0x101e6000 0x80>;
72 interrupt-parent = <&vica>;
73 interrupts = <8>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
76 gpio-controller;
77 #gpio-cells = <2>;
78 gpio-bank = <2>;
79 clocks = <&pclk>;
80 };
82 gpio3: gpio@101e7000 {
83 compatible = "st,nomadik-gpio";
84 reg = <0x101e7000 0x80>;
85 interrupt-parent = <&vica>;
86 interrupts = <9>;
87 interrupt-controller;
88 #interrupt-cells = <2>;
89 gpio-controller;
90 #gpio-cells = <2>;
91 gpio-bank = <3>;
92 clocks = <&pclk>;
93 };
95 pinctrl {
96 compatible = "stericsson,stn8815-pinctrl";
97 /* Pin configurations */
98 uart0 {
99 uart0_default_mux: uart0_mux {
100 u0_default_mux {
101 ste,function = "u0";
102 ste,pins = "u0_a_1";
103 };
104 };
105 };
106 uart1 {
107 uart1_default_mux: uart1_mux {
108 u1_default_mux {
109 ste,function = "u1";
110 ste,pins = "u1_a_1";
111 };
112 };
113 };
114 mmcsd {
115 mmcsd_default_mux: mmcsd_mux {
116 mmcsd_default_mux {
117 ste,function = "mmcsd";
118 ste,pins = "mmcsd_a_1";
119 };
120 };
121 mmcsd_default_mode: mmcsd_default {
122 mmcsd_default_cfg1 {
123 /* MCCLK */
124 ste,pins = "GPIO8_B10";
125 ste,output = <0>;
126 };
127 mmcsd_default_cfg2 {
128 /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
129 ste,pins = "GPIO10_C11", "GPIO15_A12",
130 "GPIO16_C13";
131 ste,output = <1>;
132 };
133 mmcsd_default_cfg3 {
134 /* MCCMD, MCDAT3-0, MCMSFBCLK */
135 ste,pins = "GPIO9_A10", "GPIO11_B11",
136 "GPIO12_A11", "GPIO13_C12",
137 "GPIO14_B12", "GPIO24_C15";
138 ste,input = <1>;
139 };
140 };
141 };
142 i2c0 {
143 i2c0_default_mux: i2c0_mux {
144 i2c0_default_mux {
145 ste,function = "i2c0";
146 ste,pins = "i2c0_a_1";
147 };
148 };
149 i2c0_default_mode: i2c0_default {
150 i2c0_default_cfg {
151 ste,pins = "GPIO62_D3", "GPIO63_D2";
152 ste,input = <0>;
153 };
154 };
155 };
156 i2c1 {
157 i2c1_default_mux: i2c1_mux {
158 i2c1_default_mux {
159 ste,function = "i2c1";
160 ste,pins = "i2c1_a_1";
161 };
162 };
163 i2c1_default_mode: i2c1_default {
164 i2c1_default_cfg {
165 ste,pins = "GPIO53_L4", "GPIO54_L3";
166 ste,input = <0>;
167 };
168 };
169 };
170 i2c2 {
171 i2c2_default_mode: i2c2_default {
172 i2c2_default_cfg {
173 ste,pins = "GPIO73_C21", "GPIO74_C20";
174 ste,input = <0>;
175 };
176 };
177 };
178 };
180 src: src@101e0000 {
181 compatible = "stericsson,nomadik-src";
182 reg = <0x101e0000 0x1000>;
183 disable-sxtalo;
184 disable-mxtalo;
186 /*
187 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
188 * that is parent of TIMCLK, PLL1 and PLL2
189 */
190 mxtal: mxtal@19.2M {
191 #clock-cells = <0>;
192 compatible = "fixed-clock";
193 clock-frequency = <19200000>;
194 };
196 /*
197 * The 2.4 MHz TIMCLK reference clock is active at
198 * boot time, this is actually the MXTALCLK @19.2 MHz
199 * divided by 8. This clock is used by the timers and
200 * watchdog. See page 105 ff.
201 */
202 timclk: timclk@2.4M {
203 #clock-cells = <0>;
204 compatible = "fixed-factor-clock";
205 clock-div = <8>;
206 clock-mult = <1>;
207 clocks = <&mxtal>;
208 };
210 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
211 pll1: pll1@0 {
212 #clock-cells = <0>;
213 compatible = "st,nomadik-pll-clock";
214 pll-id = <1>;
215 clocks = <&mxtal>;
216 };
218 /* HCLK divides the PLL1 with 1,2,3 or 4 */
219 hclk: hclk@0 {
220 #clock-cells = <0>;
221 compatible = "st,nomadik-hclk-clock";
222 clocks = <&pll1>;
223 };
224 /* The PCLK domain uses HCLK right off */
225 pclk: pclk@0 {
226 #clock-cells = <0>;
227 compatible = "fixed-factor-clock";
228 clock-div = <1>;
229 clock-mult = <1>;
230 clocks = <&hclk>;
231 };
233 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
234 pll2: pll2@0 {
235 #clock-cells = <0>;
236 compatible = "st,nomadik-pll-clock";
237 pll-id = <2>;
238 clocks = <&mxtal>;
239 };
240 clk216: clk216@216M {
241 #clock-cells = <0>;
242 compatible = "fixed-factor-clock";
243 clock-div = <4>;
244 clock-mult = <1>;
245 clocks = <&pll2>;
246 };
247 clk108: clk108@108M {
248 #clock-cells = <0>;
249 compatible = "fixed-factor-clock";
250 clock-div = <2>;
251 clock-mult = <1>;
252 clocks = <&clk216>;
253 };
254 clk72: clk72@72M {
255 #clock-cells = <0>;
256 compatible = "fixed-factor-clock";
257 /* The data sheet does not say how this is derived */
258 clock-div = <12>;
259 clock-mult = <1>;
260 clocks = <&pll2>;
261 };
262 clk48: clk48@48M {
263 #clock-cells = <0>;
264 compatible = "fixed-factor-clock";
265 /* The data sheet does not say how this is derived */
266 clock-div = <18>;
267 clock-mult = <1>;
268 clocks = <&pll2>;
269 };
270 clk27: clk27@27M {
271 #clock-cells = <0>;
272 compatible = "fixed-factor-clock";
273 clock-div = <4>;
274 clock-mult = <1>;
275 clocks = <&clk108>;
276 };
278 /* This apparently exists as well */
279 ulpiclk: ulpiclk@60M {
280 #clock-cells = <0>;
281 compatible = "fixed-clock";
282 clock-frequency = <60000000>;
283 };
285 /*
286 * IP AMBA bus clocks, driving the bus side of the
287 * peripheral clocking, clock gates.
288 */
290 hclkdma0: hclkdma0@48M {
291 #clock-cells = <0>;
292 compatible = "st,nomadik-src-clock";
293 clock-id = <0>;
294 clocks = <&hclk>;
295 };
296 hclksmc: hclksmc@48M {
297 #clock-cells = <0>;
298 compatible = "st,nomadik-src-clock";
299 clock-id = <1>;
300 clocks = <&hclk>;
301 };
302 hclksdram: hclksdram@48M {
303 #clock-cells = <0>;
304 compatible = "st,nomadik-src-clock";
305 clock-id = <2>;
306 clocks = <&hclk>;
307 };
308 hclkdma1: hclkdma1@48M {
309 #clock-cells = <0>;
310 compatible = "st,nomadik-src-clock";
311 clock-id = <3>;
312 clocks = <&hclk>;
313 };
314 hclkclcd: hclkclcd@48M {
315 #clock-cells = <0>;
316 compatible = "st,nomadik-src-clock";
317 clock-id = <4>;
318 clocks = <&hclk>;
319 };
320 pclkirda: pclkirda@48M {
321 #clock-cells = <0>;
322 compatible = "st,nomadik-src-clock";
323 clock-id = <5>;
324 clocks = <&pclk>;
325 };
326 pclkssp: pclkssp@48M {
327 #clock-cells = <0>;
328 compatible = "st,nomadik-src-clock";
329 clock-id = <6>;
330 clocks = <&pclk>;
331 };
332 pclkuart0: pclkuart0@48M {
333 #clock-cells = <0>;
334 compatible = "st,nomadik-src-clock";
335 clock-id = <7>;
336 clocks = <&pclk>;
337 };
338 pclksdi: pclksdi@48M {
339 #clock-cells = <0>;
340 compatible = "st,nomadik-src-clock";
341 clock-id = <8>;
342 clocks = <&pclk>;
343 };
344 pclki2c0: pclki2c0@48M {
345 #clock-cells = <0>;
346 compatible = "st,nomadik-src-clock";
347 clock-id = <9>;
348 clocks = <&pclk>;
349 };
350 pclki2c1: pclki2c1@48M {
351 #clock-cells = <0>;
352 compatible = "st,nomadik-src-clock";
353 clock-id = <10>;
354 clocks = <&pclk>;
355 };
356 pclkuart1: pclkuart1@48M {
357 #clock-cells = <0>;
358 compatible = "st,nomadik-src-clock";
359 clock-id = <11>;
360 clocks = <&pclk>;
361 };
362 pclkmsp0: pclkmsp0@48M {
363 #clock-cells = <0>;
364 compatible = "st,nomadik-src-clock";
365 clock-id = <12>;
366 clocks = <&pclk>;
367 };
368 hclkusb: hclkusb@48M {
369 #clock-cells = <0>;
370 compatible = "st,nomadik-src-clock";
371 clock-id = <13>;
372 clocks = <&hclk>;
373 };
374 hclkdif: hclkdif@48M {
375 #clock-cells = <0>;
376 compatible = "st,nomadik-src-clock";
377 clock-id = <14>;
378 clocks = <&hclk>;
379 };
380 hclksaa: hclksaa@48M {
381 #clock-cells = <0>;
382 compatible = "st,nomadik-src-clock";
383 clock-id = <15>;
384 clocks = <&hclk>;
385 };
386 hclksva: hclksva@48M {
387 #clock-cells = <0>;
388 compatible = "st,nomadik-src-clock";
389 clock-id = <16>;
390 clocks = <&hclk>;
391 };
392 pclkhsi: pclkhsi@48M {
393 #clock-cells = <0>;
394 compatible = "st,nomadik-src-clock";
395 clock-id = <17>;
396 clocks = <&pclk>;
397 };
398 pclkxti: pclkxti@48M {
399 #clock-cells = <0>;
400 compatible = "st,nomadik-src-clock";
401 clock-id = <18>;
402 clocks = <&pclk>;
403 };
404 pclkuart2: pclkuart2@48M {
405 #clock-cells = <0>;
406 compatible = "st,nomadik-src-clock";
407 clock-id = <19>;
408 clocks = <&pclk>;
409 };
410 pclkmsp1: pclkmsp1@48M {
411 #clock-cells = <0>;
412 compatible = "st,nomadik-src-clock";
413 clock-id = <20>;
414 clocks = <&pclk>;
415 };
416 pclkmsp2: pclkmsp2@48M {
417 #clock-cells = <0>;
418 compatible = "st,nomadik-src-clock";
419 clock-id = <21>;
420 clocks = <&pclk>;
421 };
422 pclkowm: pclkowm@48M {
423 #clock-cells = <0>;
424 compatible = "st,nomadik-src-clock";
425 clock-id = <22>;
426 clocks = <&pclk>;
427 };
428 hclkhpi: hclkhpi@48M {
429 #clock-cells = <0>;
430 compatible = "st,nomadik-src-clock";
431 clock-id = <23>;
432 clocks = <&hclk>;
433 };
434 pclkske: pclkske@48M {
435 #clock-cells = <0>;
436 compatible = "st,nomadik-src-clock";
437 clock-id = <24>;
438 clocks = <&pclk>;
439 };
440 pclkhsem: pclkhsem@48M {
441 #clock-cells = <0>;
442 compatible = "st,nomadik-src-clock";
443 clock-id = <25>;
444 clocks = <&pclk>;
445 };
446 hclk3d: hclk3d@48M {
447 #clock-cells = <0>;
448 compatible = "st,nomadik-src-clock";
449 clock-id = <26>;
450 clocks = <&hclk>;
451 };
452 hclkhash: hclkhash@48M {
453 #clock-cells = <0>;
454 compatible = "st,nomadik-src-clock";
455 clock-id = <27>;
456 clocks = <&hclk>;
457 };
458 hclkcryp: hclkcryp@48M {
459 #clock-cells = <0>;
460 compatible = "st,nomadik-src-clock";
461 clock-id = <28>;
462 clocks = <&hclk>;
463 };
464 pclkmshc: pclkmshc@48M {
465 #clock-cells = <0>;
466 compatible = "st,nomadik-src-clock";
467 clock-id = <29>;
468 clocks = <&pclk>;
469 };
470 hclkusbm: hclkusbm@48M {
471 #clock-cells = <0>;
472 compatible = "st,nomadik-src-clock";
473 clock-id = <30>;
474 clocks = <&hclk>;
475 };
476 hclkrng: hclkrng@48M {
477 #clock-cells = <0>;
478 compatible = "st,nomadik-src-clock";
479 clock-id = <31>;
480 clocks = <&hclk>;
481 };
483 /* IP kernel clocks */
484 clcdclk: clcdclk@0 {
485 #clock-cells = <0>;
486 compatible = "st,nomadik-src-clock";
487 clock-id = <36>;
488 clocks = <&clk72 &clk48>;
489 };
490 irdaclk: irdaclk@48M {
491 #clock-cells = <0>;
492 compatible = "st,nomadik-src-clock";
493 clock-id = <37>;
494 clocks = <&clk48>;
495 };
496 sspiclk: sspiclk@48M {
497 #clock-cells = <0>;
498 compatible = "st,nomadik-src-clock";
499 clock-id = <38>;
500 clocks = <&clk48>;
501 };
502 uart0clk: uart0clk@48M {
503 #clock-cells = <0>;
504 compatible = "st,nomadik-src-clock";
505 clock-id = <39>;
506 clocks = <&clk48>;
507 };
508 sdiclk: sdiclk@48M {
509 /* Also called MCCLK in some documents */
510 #clock-cells = <0>;
511 compatible = "st,nomadik-src-clock";
512 clock-id = <40>;
513 clocks = <&clk48>;
514 };
515 i2c0clk: i2c0clk@48M {
516 #clock-cells = <0>;
517 compatible = "st,nomadik-src-clock";
518 clock-id = <41>;
519 clocks = <&clk48>;
520 };
521 i2c1clk: i2c1clk@48M {
522 #clock-cells = <0>;
523 compatible = "st,nomadik-src-clock";
524 clock-id = <42>;
525 clocks = <&clk48>;
526 };
527 uart1clk: uart1clk@48M {
528 #clock-cells = <0>;
529 compatible = "st,nomadik-src-clock";
530 clock-id = <43>;
531 clocks = <&clk48>;
532 };
533 mspclk0: mspclk0@48M {
534 #clock-cells = <0>;
535 compatible = "st,nomadik-src-clock";
536 clock-id = <44>;
537 clocks = <&clk48>;
538 };
539 usbclk: usbclk@48M {
540 #clock-cells = <0>;
541 compatible = "st,nomadik-src-clock";
542 clock-id = <45>;
543 clocks = <&clk48>; /* 48 MHz not ULPI */
544 };
545 difclk: difclk@72M {
546 #clock-cells = <0>;
547 compatible = "st,nomadik-src-clock";
548 clock-id = <46>;
549 clocks = <&clk72>;
550 };
551 ipi2cclk: ipi2cclk@48M {
552 #clock-cells = <0>;
553 compatible = "st,nomadik-src-clock";
554 clock-id = <47>;
555 clocks = <&clk48>; /* Guess */
556 };
557 ipbmcclk: ipbmcclk@48M {
558 #clock-cells = <0>;
559 compatible = "st,nomadik-src-clock";
560 clock-id = <48>;
561 clocks = <&clk48>; /* Guess */
562 };
563 hsiclkrx: hsiclkrx@216M {
564 #clock-cells = <0>;
565 compatible = "st,nomadik-src-clock";
566 clock-id = <49>;
567 clocks = <&clk216>;
568 };
569 hsiclktx: hsiclktx@108M {
570 #clock-cells = <0>;
571 compatible = "st,nomadik-src-clock";
572 clock-id = <50>;
573 clocks = <&clk108>;
574 };
575 uart2clk: uart2clk@48M {
576 #clock-cells = <0>;
577 compatible = "st,nomadik-src-clock";
578 clock-id = <51>;
579 clocks = <&clk48>;
580 };
581 mspclk1: mspclk1@48M {
582 #clock-cells = <0>;
583 compatible = "st,nomadik-src-clock";
584 clock-id = <52>;
585 clocks = <&clk48>;
586 };
587 mspclk2: mspclk2@48M {
588 #clock-cells = <0>;
589 compatible = "st,nomadik-src-clock";
590 clock-id = <53>;
591 clocks = <&clk48>;
592 };
593 owmclk: owmclk@48M {
594 #clock-cells = <0>;
595 compatible = "st,nomadik-src-clock";
596 clock-id = <54>;
597 clocks = <&clk48>; /* Guess */
598 };
599 skeclk: skeclk@48M {
600 #clock-cells = <0>;
601 compatible = "st,nomadik-src-clock";
602 clock-id = <56>;
603 clocks = <&clk48>; /* Guess */
604 };
605 x3dclk: x3dclk@48M {
606 #clock-cells = <0>;
607 compatible = "st,nomadik-src-clock";
608 clock-id = <58>;
609 clocks = <&clk48>; /* Guess */
610 };
611 pclkmsp3: pclkmsp3@48M {
612 #clock-cells = <0>;
613 compatible = "st,nomadik-src-clock";
614 clock-id = <59>;
615 clocks = <&pclk>;
616 };
617 mspclk3: mspclk3@48M {
618 #clock-cells = <0>;
619 compatible = "st,nomadik-src-clock";
620 clock-id = <60>;
621 clocks = <&clk48>;
622 };
623 mshcclk: mshcclk@48M {
624 #clock-cells = <0>;
625 compatible = "st,nomadik-src-clock";
626 clock-id = <61>;
627 clocks = <&clk48>; /* Guess */
628 };
629 usbmclk: usbmclk@48M {
630 #clock-cells = <0>;
631 compatible = "st,nomadik-src-clock";
632 clock-id = <62>;
633 /* Stated as "48 MHz not ULPI clock" */
634 clocks = <&clk48>;
635 };
636 rngcclk: rngcclk@48M {
637 #clock-cells = <0>;
638 compatible = "st,nomadik-src-clock";
639 clock-id = <63>;
640 clocks = <&clk48>; /* Guess */
641 };
642 };
644 /* A NAND flash of 128 MiB */
645 fsmc: flash@40000000 {
646 compatible = "stericsson,fsmc-nand";
647 #address-cells = <1>;
648 #size-cells = <1>;
649 reg = <0x10100000 0x1000>, /* FSMC Register*/
650 <0x40000000 0x2000>, /* NAND Base DATA */
651 <0x41000000 0x2000>, /* NAND Base ADDR */
652 <0x40800000 0x2000>; /* NAND Base CMD */
653 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
654 clocks = <&hclksmc>;
655 status = "okay";
657 partition@0 {
658 label = "X-Loader(NAND)";
659 reg = <0x0 0x40000>;
660 };
661 partition@40000 {
662 label = "MemInit(NAND)";
663 reg = <0x40000 0x40000>;
664 };
665 partition@80000 {
666 label = "BootLoader(NAND)";
667 reg = <0x80000 0x200000>;
668 };
669 partition@280000 {
670 label = "Kernel zImage(NAND)";
671 reg = <0x280000 0x300000>;
672 };
673 partition@580000 {
674 label = "Root Filesystem(NAND)";
675 reg = <0x580000 0x1600000>;
676 };
677 partition@1b80000 {
678 label = "User Filesystem(NAND)";
679 reg = <0x1b80000 0x6480000>;
680 };
681 };
683 external-bus@34000000 {
684 compatible = "simple-bus";
685 reg = <0x34000000 0x1000000>;
686 #address-cells = <1>;
687 #size-cells = <1>;
688 ranges = <0 0x34000000 0x1000000>;
689 ethernet@300 {
690 compatible = "smsc,lan91c111";
691 reg = <0x300 0x0fd00>;
692 };
693 };
695 /* I2C0 connected to the STw4811 power management chip */
696 i2c0 {
697 compatible = "st,nomadik-i2c", "arm,primecell";
698 reg = <0x101f8000 0x1000>;
699 interrupt-parent = <&vica>;
700 interrupts = <20>;
701 clock-frequency = <100000>;
702 #address-cells = <1>;
703 #size-cells = <0>;
704 clocks = <&i2c0clk>, <&pclki2c0>;
705 clock-names = "mclk", "apb_pclk";
706 pinctrl-names = "default";
707 pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>;
709 stw4811@2d {
710 compatible = "st,stw4811";
711 reg = <0x2d>;
712 };
713 };
715 /* I2C1 connected to various sensors */
716 i2c1 {
717 compatible = "st,nomadik-i2c", "arm,primecell";
718 reg = <0x101f7000 0x1000>;
719 interrupt-parent = <&vica>;
720 interrupts = <21>;
721 clock-frequency = <100000>;
722 #address-cells = <1>;
723 #size-cells = <0>;
724 clocks = <&i2c1clk>, <&pclki2c1>;
725 clock-names = "mclk", "apb_pclk";
726 pinctrl-names = "default";
727 pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>;
729 camera@2d {
730 compatible = "st,camera";
731 reg = <0x10>;
732 };
733 stw5095@1a {
734 compatible = "st,stw5095";
735 reg = <0x1a>;
736 };
737 lis3lv02dl@1d {
738 compatible = "st,lis3lv02dl";
739 reg = <0x1d>;
740 };
741 };
743 /* I2C2 connected to the USB portions of the STw4811 only */
744 i2c2 {
745 compatible = "i2c-gpio";
746 gpios = <&gpio2 10 0>, /* sda */
747 <&gpio2 9 0>; /* scl */
748 #address-cells = <1>;
749 #size-cells = <0>;
750 pinctrl-names = "default";
751 pinctrl-0 = <&i2c2_default_mode>;
753 stw4811@2d {
754 compatible = "st,stw4811-usb";
755 reg = <0x2d>;
756 };
757 };
759 amba {
760 compatible = "arm,amba-bus";
761 #address-cells = <1>;
762 #size-cells = <1>;
763 ranges;
765 vica: intc@0x10140000 {
766 compatible = "arm,versatile-vic";
767 interrupt-controller;
768 #interrupt-cells = <1>;
769 reg = <0x10140000 0x20>;
770 };
772 vicb: intc@0x10140020 {
773 compatible = "arm,versatile-vic";
774 interrupt-controller;
775 #interrupt-cells = <1>;
776 reg = <0x10140020 0x20>;
777 };
779 uart0: uart@101fd000 {
780 compatible = "arm,pl011", "arm,primecell";
781 reg = <0x101fd000 0x1000>;
782 interrupt-parent = <&vica>;
783 interrupts = <12>;
784 clocks = <&uart0clk>, <&pclkuart0>;
785 clock-names = "uartclk", "apb_pclk";
786 pinctrl-names = "default";
787 pinctrl-0 = <&uart0_default_mux>;
788 };
790 uart1: uart@101fb000 {
791 compatible = "arm,pl011", "arm,primecell";
792 reg = <0x101fb000 0x1000>;
793 interrupt-parent = <&vica>;
794 interrupts = <17>;
795 clocks = <&uart1clk>, <&pclkuart1>;
796 clock-names = "uartclk", "apb_pclk";
797 pinctrl-names = "default";
798 pinctrl-0 = <&uart1_default_mux>;
799 };
801 uart2: uart@101f2000 {
802 compatible = "arm,pl011", "arm,primecell";
803 reg = <0x101f2000 0x1000>;
804 interrupt-parent = <&vica>;
805 interrupts = <28>;
806 clocks = <&uart2clk>, <&pclkuart2>;
807 clock-names = "uartclk", "apb_pclk";
808 status = "disabled";
809 };
811 rng: rng@101b0000 {
812 compatible = "arm,primecell";
813 reg = <0x101b0000 0x1000>;
814 clocks = <&rngcclk>, <&hclkrng>;
815 clock-names = "rng", "apb_pclk";
816 };
818 rtc: rtc@101e8000 {
819 compatible = "arm,pl031", "arm,primecell";
820 reg = <0x101e8000 0x1000>;
821 clocks = <&pclk>;
822 clock-names = "apb_pclk";
823 interrupt-parent = <&vica>;
824 interrupts = <10>;
825 };
827 mmcsd: sdi@101f6000 {
828 compatible = "arm,pl18x", "arm,primecell";
829 reg = <0x101f6000 0x1000>;
830 clocks = <&sdiclk>, <&pclksdi>;
831 clock-names = "mclk", "apb_pclk";
832 interrupt-parent = <&vica>;
833 interrupts = <22>;
834 max-frequency = <48000000>;
835 bus-width = <4>;
836 mmc-cap-mmc-highspeed;
837 mmc-cap-sd-highspeed;
838 cd-gpios = <&gpio3 15 0x1>;
839 cd-inverted;
840 pinctrl-names = "default";
841 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
842 };
843 };
844 };