arch/arm/boot/dts/sun5i-a10s.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         cpus {
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a8";
  22                 };
  23         };
  24
  25         memory {
  26                 reg = <0x40000000 0x20000000>;
  27         };
  28
  29         clocks {
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 ranges;
  33
  34                 /*
  35                  * This is a dummy clock, to be used as placeholder on
  36                  * other mux clocks when a specific parent clock is not
  37                  * yet implemented. It should be dropped when the driver
  38                  * is complete.
  39                  */
  40                 dummy: dummy {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <0>;
  44                 };
  45
  46                 osc24M: osc24M@01c20050 {
  47                         #clock-cells = <0>;
  48                         compatible = "allwinner,sun4i-osc-clk";
  49                         reg = <0x01c20050 0x4>;
  50                         clock-frequency = <24000000>;
  51                 };
  52
  53                 osc32k: osc32k {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <32768>;
  57                 };
  58
  59                 pll1: pll1@01c20000 {
  60                         #clock-cells = <0>;
  61                         compatible = "allwinner,sun4i-pll1-clk";
  62                         reg = <0x01c20000 0x4>;
  63                         clocks = <&osc24M>;
  64                 };
  65
  66                 /* dummy is 200M */
  67                 cpu: cpu@01c20054 {
  68                         #clock-cells = <0>;
  69                         compatible = "allwinner,sun4i-cpu-clk";
  70                         reg = <0x01c20054 0x4>;
  71                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  72                 };
  73
  74                 axi: axi@01c20054 {
  75                         #clock-cells = <0>;
  76                         compatible = "allwinner,sun4i-axi-clk";
  77                         reg = <0x01c20054 0x4>;
  78                         clocks = <&cpu>;
  79                 };
  80
  81                 axi_gates: axi_gates@01c2005c {
  82                         #clock-cells = <1>;
  83                         compatible = "allwinner,sun4i-axi-gates-clk";
  84                         reg = <0x01c2005c 0x4>;
  85                         clocks = <&axi>;
  86                         clock-output-names = "axi_dram";
  87                 };
  88
  89                 ahb: ahb@01c20054 {
  90                         #clock-cells = <0>;
  91                         compatible = "allwinner,sun4i-ahb-clk";
  92                         reg = <0x01c20054 0x4>;
  93                         clocks = <&axi>;
  94                 };
  95
  96                 ahb_gates: ahb_gates@01c20060 {
  97                         #clock-cells = <1>;
  98                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
  99                         reg = <0x01c20060 0x8>;
 100                         clocks = <&ahb>;
 101                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 102                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 103                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 104                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 105                                 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
 106                                 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
 107                                 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
 108                 };
 109
 110                 apb0: apb0@01c20054 {
 111                         #clock-cells = <0>;
 112                         compatible = "allwinner,sun4i-apb0-clk";
 113                         reg = <0x01c20054 0x4>;
 114                         clocks = <&ahb>;
 115                 };
 116
 117                 apb0_gates: apb0_gates@01c20068 {
 118                         #clock-cells = <1>;
 119                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 120                         reg = <0x01c20068 0x4>;
 121                         clocks = <&apb0>;
 122                         clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
 123                                 "apb0_ir", "apb0_keypad";
 124                 };
 125
 126                 /* dummy is pll62 */
 127                 apb1_mux: apb1_mux@01c20058 {
 128                         #clock-cells = <0>;
 129                         compatible = "allwinner,sun4i-apb1-mux-clk";
 130                         reg = <0x01c20058 0x4>;
 131                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 132                 };
 133
 134                 apb1: apb1@01c20058 {
 135                         #clock-cells = <0>;
 136                         compatible = "allwinner,sun4i-apb1-clk";
 137                         reg = <0x01c20058 0x4>;
 138                         clocks = <&apb1_mux>;
 139                 };
 140
 141                 apb1_gates: apb1_gates@01c2006c {
 142                         #clock-cells = <1>;
 143                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 144                         reg = <0x01c2006c 0x4>;
 145                         clocks = <&apb1>;
 146                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 147                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
 148                                 "apb1_uart2", "apb1_uart3";
 149                 };
 150         };
 151
 152         soc@01c00000 {
 153                 compatible = "simple-bus";
 154                 #address-cells = <1>;
 155                 #size-cells = <1>;
 156                 ranges;
 157
 158                 emac: ethernet@01c0b000 {
 159                         compatible = "allwinner,sun4i-emac";
 160                         reg = <0x01c0b000 0x1000>;
 161                         interrupts = <55>;
 162                         clocks = <&ahb_gates 17>;
 163                         status = "disabled";
 164                 };
 165
 166                 mdio@01c0b080 {
 167                         compatible = "allwinner,sun4i-mdio";
 168                         reg = <0x01c0b080 0x14>;
 169                         status = "disabled";
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                 };
 173
 174                 intc: interrupt-controller@01c20400 {
 175                         compatible = "allwinner,sun4i-ic";
 176                         reg = <0x01c20400 0x400>;
 177                         interrupt-controller;
 178                         #interrupt-cells = <1>;
 179                 };
 180
 181                 pio: pinctrl@01c20800 {
 182                         compatible = "allwinner,sun5i-a10s-pinctrl";
 183                         reg = <0x01c20800 0x400>;
 184                         interrupts = <28>;
 185                         clocks = <&apb0_gates 5>;
 186                         gpio-controller;
 187                         interrupt-controller;
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         #gpio-cells = <3>;
 191
 192                         uart0_pins_a: uart0@0 {
 193                                 allwinner,pins = "PB19", "PB20";
 194                                 allwinner,function = "uart0";
 195                                 allwinner,drive = <0>;
 196                                 allwinner,pull = <0>;
 197                         };
 198
 199                         uart2_pins_a: uart2@0 {
 200                                 allwinner,pins = "PC18", "PC19";
 201                                 allwinner,function = "uart2";
 202                                 allwinner,drive = <0>;
 203                                 allwinner,pull = <0>;
 204                         };
 205
 206                         uart3_pins_a: uart3@0 {
 207                                 allwinner,pins = "PG9", "PG10";
 208                                 allwinner,function = "uart3";
 209                                 allwinner,drive = <0>;
 210                                 allwinner,pull = <0>;
 211                         };
 212
 213                         emac_pins_a: emac0@0 {
 214                                 allwinner,pins = "PA0", "PA1", "PA2",
 215                                                 "PA3", "PA4", "PA5", "PA6",
 216                                                 "PA7", "PA8", "PA9", "PA10",
 217                                                 "PA11", "PA12", "PA13", "PA14",
 218                                                 "PA15", "PA16";
 219                                 allwinner,function = "emac";
 220                                 allwinner,drive = <0>;
 221                                 allwinner,pull = <0>;
 222                         };
 223
 224                         i2c0_pins_a: i2c0@0 {
 225                                 allwinner,pins = "PB0", "PB1";
 226                                 allwinner,function = "i2c0";
 227                                 allwinner,drive = <0>;
 228                                 allwinner,pull = <0>;
 229                         };
 230
 231                         i2c1_pins_a: i2c1@0 {
 232                                 allwinner,pins = "PB15", "PB16";
 233                                 allwinner,function = "i2c1";
 234                                 allwinner,drive = <0>;
 235                                 allwinner,pull = <0>;
 236                         };
 237
 238                         i2c2_pins_a: i2c2@0 {
 239                                 allwinner,pins = "PB17", "PB18";
 240                                 allwinner,function = "i2c2";
 241                                 allwinner,drive = <0>;
 242                                 allwinner,pull = <0>;
 243                         };
 244                 };
 245
 246                 timer@01c20c00 {
 247                         compatible = "allwinner,sun4i-timer";
 248                         reg = <0x01c20c00 0x90>;
 249                         interrupts = <22>;
 250                         clocks = <&osc24M>;
 251                 };
 252
 253                 wdt: watchdog@01c20c90 {
 254                         compatible = "allwinner,sun4i-wdt";
 255                         reg = <0x01c20c90 0x10>;
 256                 };
 257
 258                 uart0: serial@01c28000 {
 259                         compatible = "snps,dw-apb-uart";
 260                         reg = <0x01c28000 0x400>;
 261                         interrupts = <1>;
 262                         reg-shift = <2>;
 263                         reg-io-width = <4>;
 264                         clocks = <&apb1_gates 16>;
 265                         status = "disabled";
 266                 };
 267
 268                 uart1: serial@01c28400 {
 269                         compatible = "snps,dw-apb-uart";
 270                         reg = <0x01c28400 0x400>;
 271                         interrupts = <2>;
 272                         reg-shift = <2>;
 273                         reg-io-width = <4>;
 274                         clocks = <&apb1_gates 17>;
 275                         status = "disabled";
 276                 };
 277
 278                 uart2: serial@01c28800 {
 279                         compatible = "snps,dw-apb-uart";
 280                         reg = <0x01c28800 0x400>;
 281                         interrupts = <3>;
 282                         reg-shift = <2>;
 283                         reg-io-width = <4>;
 284                         clocks = <&apb1_gates 18>;
 285                         status = "disabled";
 286                 };
 287
 288                 uart3: serial@01c28c00 {
 289                         compatible = "snps,dw-apb-uart";
 290                         reg = <0x01c28c00 0x400>;
 291                         interrupts = <4>;
 292                         reg-shift = <2>;
 293                         reg-io-width = <4>;
 294                         clocks = <&apb1_gates 19>;
 295                         status = "disabled";
 296                 };
 297
 298                 i2c0: i2c@01c2ac00 {
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         compatible = "allwinner,sun4i-i2c";
 302                         reg = <0x01c2ac00 0x400>;
 303                         interrupts = <7>;
 304                         clocks = <&apb1_gates 0>;
 305                         clock-frequency = <100000>;
 306                         status = "disabled";
 307                 };
 308
 309                 i2c1: i2c@01c2b000 {
 310                         #address-cells = <1>;
 311                         #size-cells = <0>;
 312                         compatible = "allwinner,sun4i-i2c";
 313                         reg = <0x01c2b000 0x400>;
 314                         interrupts = <8>;
 315                         clocks = <&apb1_gates 1>;
 316                         clock-frequency = <100000>;
 317                         status = "disabled";
 318                 };
 319
 320                 i2c2: i2c@01c2b400 {
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         compatible = "allwinner,sun4i-i2c";
 324                         reg = <0x01c2b400 0x400>;
 325                         interrupts = <9>;
 326                         clocks = <&apb1_gates 2>;
 327                         clock-frequency = <100000>;
 328                         status = "disabled";
 329                 };
 330         };
 331 };