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x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / common / edma.c
blob8e1a0245907f85be1a460bfa785f744daf285d6f
1 /*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/slab.h>
28 #include <linux/edma.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34
35 #include <linux/platform_data/edma.h>
36
37 /* Offsets matching "struct edmacc_param" */
38 #define PARM_OPT 0x00
39 #define PARM_SRC 0x04
40 #define PARM_A_B_CNT 0x08
41 #define PARM_DST 0x0c
42 #define PARM_SRC_DST_BIDX 0x10
43 #define PARM_LINK_BCNTRLD 0x14
44 #define PARM_SRC_DST_CIDX 0x18
45 #define PARM_CCNT 0x1c
46
47 #define PARM_SIZE 0x20
48
49 /* Offsets for EDMA CC global channel registers and their shadows */
50 #define SH_ER 0x00 /* 64 bits */
51 #define SH_ECR 0x08 /* 64 bits */
52 #define SH_ESR 0x10 /* 64 bits */
53 #define SH_CER 0x18 /* 64 bits */
54 #define SH_EER 0x20 /* 64 bits */
55 #define SH_EECR 0x28 /* 64 bits */
56 #define SH_EESR 0x30 /* 64 bits */
57 #define SH_SER 0x38 /* 64 bits */
58 #define SH_SECR 0x40 /* 64 bits */
59 #define SH_IER 0x50 /* 64 bits */
60 #define SH_IECR 0x58 /* 64 bits */
61 #define SH_IESR 0x60 /* 64 bits */
62 #define SH_IPR 0x68 /* 64 bits */
63 #define SH_ICR 0x70 /* 64 bits */
64 #define SH_IEVAL 0x78
65 #define SH_QER 0x80
66 #define SH_QEER 0x84
67 #define SH_QEECR 0x88
68 #define SH_QEESR 0x8c
69 #define SH_QSER 0x90
70 #define SH_QSECR 0x94
71 #define SH_SIZE 0x200
72
73 /* Offsets for EDMA CC global registers */
74 #define EDMA_REV 0x0000
75 #define EDMA_CCCFG 0x0004
76 #define EDMA_QCHMAP 0x0200 /* 8 registers */
77 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
78 #define EDMA_QDMAQNUM 0x0260
79 #define EDMA_QUETCMAP 0x0280
80 #define EDMA_QUEPRI 0x0284
81 #define EDMA_EMR 0x0300 /* 64 bits */
82 #define EDMA_EMCR 0x0308 /* 64 bits */
83 #define EDMA_QEMR 0x0310
84 #define EDMA_QEMCR 0x0314
85 #define EDMA_CCERR 0x0318
86 #define EDMA_CCERRCLR 0x031c
87 #define EDMA_EEVAL 0x0320
88 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
89 #define EDMA_QRAE 0x0380 /* 4 registers */
90 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
91 #define EDMA_QSTAT 0x0600 /* 2 registers */
92 #define EDMA_QWMTHRA 0x0620
93 #define EDMA_QWMTHRB 0x0624
94 #define EDMA_CCSTAT 0x0640
95
96 #define EDMA_M 0x1000 /* global channel registers */
97 #define EDMA_ECR 0x1008
98 #define EDMA_ECRH 0x100C
99 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
100 #define EDMA_PARM 0x4000 /* 128 param entries */
101
102 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
103
104 #define EDMA_DCHMAP 0x0100 /* 64 registers */
105 #define CHMAP_EXIST BIT(24)
106
107 #define EDMA_MAX_DMACH 64
108 #define EDMA_MAX_PARAMENTRY 512
109
110 /*****************************************************************************/
111
112 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
113
114 static inline unsigned int edma_read(unsigned ctlr, int offset)
115 {
116 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
117 }
118
119 static inline void edma_write(unsigned ctlr, int offset, int val)
120 {
121 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
122 }
123 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
124 unsigned or)
125 {
126 unsigned val = edma_read(ctlr, offset);
127 val &= and;
128 val |= or;
129 edma_write(ctlr, offset, val);
130 }
131 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
132 {
133 unsigned val = edma_read(ctlr, offset);
134 val &= and;
135 edma_write(ctlr, offset, val);
136 }
137 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
138 {
139 unsigned val = edma_read(ctlr, offset);
140 val |= or;
141 edma_write(ctlr, offset, val);
142 }
143 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
144 {
145 return edma_read(ctlr, offset + (i << 2));
146 }
147 static inline void edma_write_array(unsigned ctlr, int offset, int i,
148 unsigned val)
149 {
150 edma_write(ctlr, offset + (i << 2), val);
151 }
152 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
153 unsigned and, unsigned or)
154 {
155 edma_modify(ctlr, offset + (i << 2), and, or);
156 }
157 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
158 {
159 edma_or(ctlr, offset + (i << 2), or);
160 }
161 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
162 unsigned or)
163 {
164 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
165 }
166 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
167 unsigned val)
168 {
169 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
170 }
171 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
172 {
173 return edma_read(ctlr, EDMA_SHADOW0 + offset);
174 }
175 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
176 int i)
177 {
178 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
179 }
180 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
181 {
182 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
183 }
184 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
185 unsigned val)
186 {
187 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
188 }
189 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
190 int param_no)
191 {
192 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
193 }
194 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
195 unsigned val)
196 {
197 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
198 }
199 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
200 unsigned and, unsigned or)
201 {
202 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
203 }
204 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
205 unsigned and)
206 {
207 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
208 }
209 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
210 unsigned or)
211 {
212 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
213 }
214
215 static inline void set_bits(int offset, int len, unsigned long *p)
216 {
217 for (; len > 0; len--)
218 set_bit(offset + (len - 1), p);
219 }
220
221 static inline void clear_bits(int offset, int len, unsigned long *p)
222 {
223 for (; len > 0; len--)
224 clear_bit(offset + (len - 1), p);
225 }
226
227 /*****************************************************************************/
228
229 /* actual number of DMA channels and slots on this silicon */
230 struct edma {
231 /* how many dma resources of each type */
232 unsigned num_channels;
233 unsigned num_region;
234 unsigned num_slots;
235 unsigned num_tc;
236 unsigned num_cc;
237 enum dma_event_q default_queue;
238
239 /* list of channels with no even trigger; terminated by "-1" */
240 const s8 *noevent;
241
242 /* The edma_inuse bit for each PaRAM slot is clear unless the
243 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
244 */
245 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
246
247 /* The edma_unused bit for each channel is clear unless
248 * it is not being used on this platform. It uses a bit
249 * of SOC-specific initialization code.
250 */
251 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
252
253 unsigned irq_res_start;
254 unsigned irq_res_end;
255
256 struct dma_interrupt_data {
257 void (*callback)(unsigned channel, unsigned short ch_status,
258 void *data);
259 void *data;
260 } intr_data[EDMA_MAX_DMACH];
261 };
262
263 static struct edma *edma_cc[EDMA_MAX_CC];
264 static int arch_num_cc;
265
266 /* dummy param set used to (re)initialize parameter RAM slots */
267 static const struct edmacc_param dummy_paramset = {
268 .link_bcntrld = 0xffff,
269 .ccnt = 1,
270 };
271
272 static const struct of_device_id edma_of_ids[] = {
273 { .compatible = "ti,edma3", },
274 {}
275 };
276
277 /*****************************************************************************/
278
279 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
280 enum dma_event_q queue_no)
281 {
282 int bit = (ch_no & 0x7) * 4;
283
284 /* default to low priority queue */
285 if (queue_no == EVENTQ_DEFAULT)
286 queue_no = edma_cc[ctlr]->default_queue;
287
288 queue_no &= 7;
289 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
290 ~(0x7 << bit), queue_no << bit);
291 }
292
293 static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
294 {
295 int bit = queue_no * 4;
296 edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
297 }
298
299 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
300 int priority)
301 {
302 int bit = queue_no * 4;
303 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
304 ((priority & 0x7) << bit));
305 }
306
307 /**
308 * map_dmach_param - Maps channel number to param entry number
309 *
310 * This maps the dma channel number to param entry numberter. In
311 * other words using the DMA channel mapping registers a param entry
312 * can be mapped to any channel
313 *
314 * Callers are responsible for ensuring the channel mapping logic is
315 * included in that particular EDMA variant (Eg : dm646x)
316 *
317 */
318 static void __init map_dmach_param(unsigned ctlr)
319 {
320 int i;
321 for (i = 0; i < EDMA_MAX_DMACH; i++)
322 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
323 }
324
325 static inline void
326 setup_dma_interrupt(unsigned lch,
327 void (*callback)(unsigned channel, u16 ch_status, void *data),
328 void *data)
329 {
330 unsigned ctlr;
331
332 ctlr = EDMA_CTLR(lch);
333 lch = EDMA_CHAN_SLOT(lch);
334
335 if (!callback)
336 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
337 BIT(lch & 0x1f));
338
339 edma_cc[ctlr]->intr_data[lch].callback = callback;
340 edma_cc[ctlr]->intr_data[lch].data = data;
341
342 if (callback) {
343 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
344 BIT(lch & 0x1f));
345 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
346 BIT(lch & 0x1f));
347 }
348 }
349
350 static int irq2ctlr(int irq)
351 {
352 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
353 return 0;
354 else if (irq >= edma_cc[1]->irq_res_start &&
355 irq <= edma_cc[1]->irq_res_end)
356 return 1;
357
358 return -1;
359 }
360
361 /******************************************************************************
362 *
363 * DMA interrupt handler
364 *
365 *****************************************************************************/
366 static irqreturn_t dma_irq_handler(int irq, void *data)
367 {
368 int ctlr;
369 u32 sh_ier;
370 u32 sh_ipr;
371 u32 bank;
372
373 ctlr = irq2ctlr(irq);
374 if (ctlr < 0)
375 return IRQ_NONE;
376
377 dev_dbg(data, "dma_irq_handler\n");
378
379 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
380 if (!sh_ipr) {
381 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
382 if (!sh_ipr)
383 return IRQ_NONE;
384 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
385 bank = 1;
386 } else {
387 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
388 bank = 0;
389 }
390
391 do {
392 u32 slot;
393 u32 channel;
394
395 dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
396
397 slot = __ffs(sh_ipr);
398 sh_ipr &= ~(BIT(slot));
399
400 if (sh_ier & BIT(slot)) {
401 channel = (bank << 5) | slot;
402 /* Clear the corresponding IPR bits */
403 edma_shadow0_write_array(ctlr, SH_ICR, bank,
404 BIT(slot));
405 if (edma_cc[ctlr]->intr_data[channel].callback)
406 edma_cc[ctlr]->intr_data[channel].callback(
407 channel, DMA_COMPLETE,
408 edma_cc[ctlr]->intr_data[channel].data);
409 }
410 } while (sh_ipr);
411
412 edma_shadow0_write(ctlr, SH_IEVAL, 1);
413 return IRQ_HANDLED;
414 }
415
416 /******************************************************************************
417 *
418 * DMA error interrupt handler
419 *
420 *****************************************************************************/
421 static irqreturn_t dma_ccerr_handler(int irq, void *data)
422 {
423 int i;
424 int ctlr;
425 unsigned int cnt = 0;
426
427 ctlr = irq2ctlr(irq);
428 if (ctlr < 0)
429 return IRQ_NONE;
430
431 dev_dbg(data, "dma_ccerr_handler\n");
432
433 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
434 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
435 (edma_read(ctlr, EDMA_QEMR) == 0) &&
436 (edma_read(ctlr, EDMA_CCERR) == 0))
437 return IRQ_NONE;
438
439 while (1) {
440 int j = -1;
441 if (edma_read_array(ctlr, EDMA_EMR, 0))
442 j = 0;
443 else if (edma_read_array(ctlr, EDMA_EMR, 1))
444 j = 1;
445 if (j >= 0) {
446 dev_dbg(data, "EMR%d %08x\n", j,
447 edma_read_array(ctlr, EDMA_EMR, j));
448 for (i = 0; i < 32; i++) {
449 int k = (j << 5) + i;
450 if (edma_read_array(ctlr, EDMA_EMR, j) &
451 BIT(i)) {
452 /* Clear the corresponding EMR bits */
453 edma_write_array(ctlr, EDMA_EMCR, j,
454 BIT(i));
455 /* Clear any SER */
456 edma_shadow0_write_array(ctlr, SH_SECR,
457 j, BIT(i));
458 if (edma_cc[ctlr]->intr_data[k].
459 callback) {
460 edma_cc[ctlr]->intr_data[k].
461 callback(k,
462 DMA_CC_ERROR,
463 edma_cc[ctlr]->intr_data
464 [k].data);
465 }
466 }
467 }
468 } else if (edma_read(ctlr, EDMA_QEMR)) {
469 dev_dbg(data, "QEMR %02x\n",
470 edma_read(ctlr, EDMA_QEMR));
471 for (i = 0; i < 8; i++) {
472 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
473 /* Clear the corresponding IPR bits */
474 edma_write(ctlr, EDMA_QEMCR, BIT(i));
475 edma_shadow0_write(ctlr, SH_QSECR,
476 BIT(i));
477
478 /* NOTE: not reported!! */
479 }
480 }
481 } else if (edma_read(ctlr, EDMA_CCERR)) {
482 dev_dbg(data, "CCERR %08x\n",
483 edma_read(ctlr, EDMA_CCERR));
484 /* FIXME: CCERR.BIT(16) ignored! much better
485 * to just write CCERRCLR with CCERR value...
486 */
487 for (i = 0; i < 8; i++) {
488 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
489 /* Clear the corresponding IPR bits */
490 edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
491
492 /* NOTE: not reported!! */
493 }
494 }
495 }
496 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
497 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
498 (edma_read(ctlr, EDMA_QEMR) == 0) &&
499 (edma_read(ctlr, EDMA_CCERR) == 0))
500 break;
501 cnt++;
502 if (cnt > 10)
503 break;
504 }
505 edma_write(ctlr, EDMA_EEVAL, 1);
506 return IRQ_HANDLED;
507 }
508
509 static int reserve_contiguous_slots(int ctlr, unsigned int id,
510 unsigned int num_slots,
511 unsigned int start_slot)
512 {
513 int i, j;
514 unsigned int count = num_slots;
515 int stop_slot = start_slot;
516 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
517
518 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
519 j = EDMA_CHAN_SLOT(i);
520 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
521 /* Record our current beginning slot */
522 if (count == num_slots)
523 stop_slot = i;
524
525 count--;
526 set_bit(j, tmp_inuse);
527
528 if (count == 0)
529 break;
530 } else {
531 clear_bit(j, tmp_inuse);
532
533 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
534 stop_slot = i;
535 break;
536 } else {
537 count = num_slots;
538 }
539 }
540 }
541
542 /*
543 * We have to clear any bits that we set
544 * if we run out parameter RAM slots, i.e we do find a set
545 * of contiguous parameter RAM slots but do not find the exact number
546 * requested as we may reach the total number of parameter RAM slots
547 */
548 if (i == edma_cc[ctlr]->num_slots)
549 stop_slot = i;
550
551 j = start_slot;
552 for_each_set_bit_from(j, tmp_inuse, stop_slot)
553 clear_bit(j, edma_cc[ctlr]->edma_inuse);
554
555 if (count)
556 return -EBUSY;
557
558 for (j = i - num_slots + 1; j <= i; ++j)
559 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
560 &dummy_paramset, PARM_SIZE);
561
562 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
563 }
564
565 static int prepare_unused_channel_list(struct device *dev, void *data)
566 {
567 struct platform_device *pdev = to_platform_device(dev);
568 int i, count, ctlr;
569 struct of_phandle_args dma_spec;
570
571 if (dev->of_node) {
572 count = of_property_count_strings(dev->of_node, "dma-names");
573 if (count < 0)
574 return 0;
575 for (i = 0; i < count; i++) {
576 if (of_parse_phandle_with_args(dev->of_node, "dmas",
577 "#dma-cells", i,
578 &dma_spec))
579 continue;
580
581 if (!of_match_node(edma_of_ids, dma_spec.np)) {
582 of_node_put(dma_spec.np);
583 continue;
584 }
585
586 clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
587 edma_cc[0]->edma_unused);
588 of_node_put(dma_spec.np);
589 }
590 return 0;
591 }
592
593 /* For non-OF case */
594 for (i = 0; i < pdev->num_resources; i++) {
595 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
596 (int)pdev->resource[i].start >= 0) {
597 ctlr = EDMA_CTLR(pdev->resource[i].start);
598 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
599 edma_cc[ctlr]->edma_unused);
600 }
601 }
602
603 return 0;
604 }
605
606 /*-----------------------------------------------------------------------*/
607
608 static bool unused_chan_list_done;
609
610 /* Resource alloc/free: dma channels, parameter RAM slots */
611
612 /**
613 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
614 * @channel: specific channel to allocate; negative for "any unmapped channel"
615 * @callback: optional; to be issued on DMA completion or errors
616 * @data: passed to callback
617 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
618 * Controller (TC) executes requests using this channel. Use
619 * EVENTQ_DEFAULT unless you really need a high priority queue.
620 *
621 * This allocates a DMA channel and its associated parameter RAM slot.
622 * The parameter RAM is initialized to hold a dummy transfer.
623 *
624 * Normal use is to pass a specific channel number as @channel, to make
625 * use of hardware events mapped to that channel. When the channel will
626 * be used only for software triggering or event chaining, channels not
627 * mapped to hardware events (or mapped to unused events) are preferable.
628 *
629 * DMA transfers start from a channel using edma_start(), or by
630 * chaining. When the transfer described in that channel's parameter RAM
631 * slot completes, that slot's data may be reloaded through a link.
632 *
633 * DMA errors are only reported to the @callback associated with the
634 * channel driving that transfer, but transfer completion callbacks can
635 * be sent to another channel under control of the TCC field in
636 * the option word of the transfer's parameter RAM set. Drivers must not
637 * use DMA transfer completion callbacks for channels they did not allocate.
638 * (The same applies to TCC codes used in transfer chaining.)
639 *
640 * Returns the number of the channel, else negative errno.
641 */
642 int edma_alloc_channel(int channel,
643 void (*callback)(unsigned channel, u16 ch_status, void *data),
644 void *data,
645 enum dma_event_q eventq_no)
646 {
647 unsigned i, done = 0, ctlr = 0;
648 int ret = 0;
649
650 if (!unused_chan_list_done) {
651 /*
652 * Scan all the platform devices to find out the EDMA channels
653 * used and clear them in the unused list, making the rest
654 * available for ARM usage.
655 */
656 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
657 prepare_unused_channel_list);
658 if (ret < 0)
659 return ret;
660
661 unused_chan_list_done = true;
662 }
663
664 if (channel >= 0) {
665 ctlr = EDMA_CTLR(channel);
666 channel = EDMA_CHAN_SLOT(channel);
667 }
668
669 if (channel < 0) {
670 for (i = 0; i < arch_num_cc; i++) {
671 channel = 0;
672 for (;;) {
673 channel = find_next_bit(edma_cc[i]->edma_unused,
674 edma_cc[i]->num_channels,
675 channel);
676 if (channel == edma_cc[i]->num_channels)
677 break;
678 if (!test_and_set_bit(channel,
679 edma_cc[i]->edma_inuse)) {
680 done = 1;
681 ctlr = i;
682 break;
683 }
684 channel++;
685 }
686 if (done)
687 break;
688 }
689 if (!done)
690 return -ENOMEM;
691 } else if (channel >= edma_cc[ctlr]->num_channels) {
692 return -EINVAL;
693 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
694 return -EBUSY;
695 }
696
697 /* ensure access through shadow region 0 */
698 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
699
700 /* ensure no events are pending */
701 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
702 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
703 &dummy_paramset, PARM_SIZE);
704
705 if (callback)
706 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
707 callback, data);
708
709 map_dmach_queue(ctlr, channel, eventq_no);
710
711 return EDMA_CTLR_CHAN(ctlr, channel);
712 }
713 EXPORT_SYMBOL(edma_alloc_channel);
714
715
716 /**
717 * edma_free_channel - deallocate DMA channel
718 * @channel: dma channel returned from edma_alloc_channel()
719 *
720 * This deallocates the DMA channel and associated parameter RAM slot
721 * allocated by edma_alloc_channel().
722 *
723 * Callers are responsible for ensuring the channel is inactive, and
724 * will not be reactivated by linking, chaining, or software calls to
725 * edma_start().
726 */
727 void edma_free_channel(unsigned channel)
728 {
729 unsigned ctlr;
730
731 ctlr = EDMA_CTLR(channel);
732 channel = EDMA_CHAN_SLOT(channel);
733
734 if (channel >= edma_cc[ctlr]->num_channels)
735 return;
736
737 setup_dma_interrupt(channel, NULL, NULL);
738 /* REVISIT should probably take out of shadow region 0 */
739
740 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
741 &dummy_paramset, PARM_SIZE);
742 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
743 }
744 EXPORT_SYMBOL(edma_free_channel);
745
746 /**
747 * edma_alloc_slot - allocate DMA parameter RAM
748 * @slot: specific slot to allocate; negative for "any unused slot"
749 *
750 * This allocates a parameter RAM slot, initializing it to hold a
751 * dummy transfer. Slots allocated using this routine have not been
752 * mapped to a hardware DMA channel, and will normally be used by
753 * linking to them from a slot associated with a DMA channel.
754 *
755 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
756 * slots may be allocated on behalf of DSP firmware.
757 *
758 * Returns the number of the slot, else negative errno.
759 */
760 int edma_alloc_slot(unsigned ctlr, int slot)
761 {
762 if (!edma_cc[ctlr])
763 return -EINVAL;
764
765 if (slot >= 0)
766 slot = EDMA_CHAN_SLOT(slot);
767
768 if (slot < 0) {
769 slot = edma_cc[ctlr]->num_channels;
770 for (;;) {
771 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
772 edma_cc[ctlr]->num_slots, slot);
773 if (slot == edma_cc[ctlr]->num_slots)
774 return -ENOMEM;
775 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
776 break;
777 }
778 } else if (slot < edma_cc[ctlr]->num_channels ||
779 slot >= edma_cc[ctlr]->num_slots) {
780 return -EINVAL;
781 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
782 return -EBUSY;
783 }
784
785 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
786 &dummy_paramset, PARM_SIZE);
787
788 return EDMA_CTLR_CHAN(ctlr, slot);
789 }
790 EXPORT_SYMBOL(edma_alloc_slot);
791
792 /**
793 * edma_free_slot - deallocate DMA parameter RAM
794 * @slot: parameter RAM slot returned from edma_alloc_slot()
795 *
796 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
797 * Callers are responsible for ensuring the slot is inactive, and will
798 * not be activated.
799 */
800 void edma_free_slot(unsigned slot)
801 {
802 unsigned ctlr;
803
804 ctlr = EDMA_CTLR(slot);
805 slot = EDMA_CHAN_SLOT(slot);
806
807 if (slot < edma_cc[ctlr]->num_channels ||
808 slot >= edma_cc[ctlr]->num_slots)
809 return;
810
811 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
812 &dummy_paramset, PARM_SIZE);
813 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
814 }
815 EXPORT_SYMBOL(edma_free_slot);
816
817
818 /**
819 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
820 * The API will return the starting point of a set of
821 * contiguous parameter RAM slots that have been requested
822 *
823 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
824 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
825 * @count: number of contiguous Paramter RAM slots
826 * @slot - the start value of Parameter RAM slot that should be passed if id
827 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
828 *
829 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
830 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
831 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
832 *
833 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
834 * set of contiguous parameter RAM slots from the "slot" that is passed as an
835 * argument to the API.
836 *
837 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
838 * starts looking for a set of contiguous parameter RAMs from the "slot"
839 * that is passed as an argument to the API. On failure the API will try to
840 * find a set of contiguous Parameter RAM slots from the remaining Parameter
841 * RAM slots
842 */
843 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
844 {
845 /*
846 * The start slot requested should be greater than
847 * the number of channels and lesser than the total number
848 * of slots
849 */
850 if ((id != EDMA_CONT_PARAMS_ANY) &&
851 (slot < edma_cc[ctlr]->num_channels ||
852 slot >= edma_cc[ctlr]->num_slots))
853 return -EINVAL;
854
855 /*
856 * The number of parameter RAM slots requested cannot be less than 1
857 * and cannot be more than the number of slots minus the number of
858 * channels
859 */
860 if (count < 1 || count >
861 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
862 return -EINVAL;
863
864 switch (id) {
865 case EDMA_CONT_PARAMS_ANY:
866 return reserve_contiguous_slots(ctlr, id, count,
867 edma_cc[ctlr]->num_channels);
868 case EDMA_CONT_PARAMS_FIXED_EXACT:
869 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
870 return reserve_contiguous_slots(ctlr, id, count, slot);
871 default:
872 return -EINVAL;
873 }
874
875 }
876 EXPORT_SYMBOL(edma_alloc_cont_slots);
877
878 /**
879 * edma_free_cont_slots - deallocate DMA parameter RAM slots
880 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
881 * @count: the number of contiguous parameter RAM slots to be freed
882 *
883 * This deallocates the parameter RAM slots allocated by
884 * edma_alloc_cont_slots.
885 * Callers/applications need to keep track of sets of contiguous
886 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
887 * API.
888 * Callers are responsible for ensuring the slots are inactive, and will
889 * not be activated.
890 */
891 int edma_free_cont_slots(unsigned slot, int count)
892 {
893 unsigned ctlr, slot_to_free;
894 int i;
895
896 ctlr = EDMA_CTLR(slot);
897 slot = EDMA_CHAN_SLOT(slot);
898
899 if (slot < edma_cc[ctlr]->num_channels ||
900 slot >= edma_cc[ctlr]->num_slots ||
901 count < 1)
902 return -EINVAL;
903
904 for (i = slot; i < slot + count; ++i) {
905 ctlr = EDMA_CTLR(i);
906 slot_to_free = EDMA_CHAN_SLOT(i);
907
908 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
909 &dummy_paramset, PARM_SIZE);
910 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
911 }
912
913 return 0;
914 }
915 EXPORT_SYMBOL(edma_free_cont_slots);
916
917 /*-----------------------------------------------------------------------*/
918
919 /* Parameter RAM operations (i) -- read/write partial slots */
920
921 /**
922 * edma_set_src - set initial DMA source address in parameter RAM slot
923 * @slot: parameter RAM slot being configured
924 * @src_port: physical address of source (memory, controller FIFO, etc)
925 * @addressMode: INCR, except in very rare cases
926 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
927 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
928 *
929 * Note that the source address is modified during the DMA transfer
930 * according to edma_set_src_index().
931 */
932 void edma_set_src(unsigned slot, dma_addr_t src_port,
933 enum address_mode mode, enum fifo_width width)
934 {
935 unsigned ctlr;
936
937 ctlr = EDMA_CTLR(slot);
938 slot = EDMA_CHAN_SLOT(slot);
939
940 if (slot < edma_cc[ctlr]->num_slots) {
941 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
942
943 if (mode) {
944 /* set SAM and program FWID */
945 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
946 } else {
947 /* clear SAM */
948 i &= ~SAM;
949 }
950 edma_parm_write(ctlr, PARM_OPT, slot, i);
951
952 /* set the source port address
953 in source register of param structure */
954 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
955 }
956 }
957 EXPORT_SYMBOL(edma_set_src);
958
959 /**
960 * edma_set_dest - set initial DMA destination address in parameter RAM slot
961 * @slot: parameter RAM slot being configured
962 * @dest_port: physical address of destination (memory, controller FIFO, etc)
963 * @addressMode: INCR, except in very rare cases
964 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
965 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
966 *
967 * Note that the destination address is modified during the DMA transfer
968 * according to edma_set_dest_index().
969 */
970 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
971 enum address_mode mode, enum fifo_width width)
972 {
973 unsigned ctlr;
974
975 ctlr = EDMA_CTLR(slot);
976 slot = EDMA_CHAN_SLOT(slot);
977
978 if (slot < edma_cc[ctlr]->num_slots) {
979 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
980
981 if (mode) {
982 /* set DAM and program FWID */
983 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
984 } else {
985 /* clear DAM */
986 i &= ~DAM;
987 }
988 edma_parm_write(ctlr, PARM_OPT, slot, i);
989 /* set the destination port address
990 in dest register of param structure */
991 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
992 }
993 }
994 EXPORT_SYMBOL(edma_set_dest);
995
996 /**
997 * edma_get_position - returns the current transfer points
998 * @slot: parameter RAM slot being examined
999 * @src: pointer to source port position
1000 * @dst: pointer to destination port position
1001 *
1002 * Returns current source and destination addresses for a particular
1003 * parameter RAM slot. Its channel should not be active when this is called.
1004 */
1005 void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
1006 {
1007 struct edmacc_param temp;
1008 unsigned ctlr;
1009
1010 ctlr = EDMA_CTLR(slot);
1011 slot = EDMA_CHAN_SLOT(slot);
1012
1013 edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
1014 if (src != NULL)
1015 *src = temp.src;
1016 if (dst != NULL)
1017 *dst = temp.dst;
1018 }
1019 EXPORT_SYMBOL(edma_get_position);
1020
1021 /**
1022 * edma_set_src_index - configure DMA source address indexing
1023 * @slot: parameter RAM slot being configured
1024 * @src_bidx: byte offset between source arrays in a frame
1025 * @src_cidx: byte offset between source frames in a block
1026 *
1027 * Offsets are specified to support either contiguous or discontiguous
1028 * memory transfers, or repeated access to a hardware register, as needed.
1029 * When accessing hardware registers, both offsets are normally zero.
1030 */
1031 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1032 {
1033 unsigned ctlr;
1034
1035 ctlr = EDMA_CTLR(slot);
1036 slot = EDMA_CHAN_SLOT(slot);
1037
1038 if (slot < edma_cc[ctlr]->num_slots) {
1039 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1040 0xffff0000, src_bidx);
1041 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1042 0xffff0000, src_cidx);
1043 }
1044 }
1045 EXPORT_SYMBOL(edma_set_src_index);
1046
1047 /**
1048 * edma_set_dest_index - configure DMA destination address indexing
1049 * @slot: parameter RAM slot being configured
1050 * @dest_bidx: byte offset between destination arrays in a frame
1051 * @dest_cidx: byte offset between destination frames in a block
1052 *
1053 * Offsets are specified to support either contiguous or discontiguous
1054 * memory transfers, or repeated access to a hardware register, as needed.
1055 * When accessing hardware registers, both offsets are normally zero.
1056 */
1057 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1058 {
1059 unsigned ctlr;
1060
1061 ctlr = EDMA_CTLR(slot);
1062 slot = EDMA_CHAN_SLOT(slot);
1063
1064 if (slot < edma_cc[ctlr]->num_slots) {
1065 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1066 0x0000ffff, dest_bidx << 16);
1067 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1068 0x0000ffff, dest_cidx << 16);
1069 }
1070 }
1071 EXPORT_SYMBOL(edma_set_dest_index);
1072
1073 /**
1074 * edma_set_transfer_params - configure DMA transfer parameters
1075 * @slot: parameter RAM slot being configured
1076 * @acnt: how many bytes per array (at least one)
1077 * @bcnt: how many arrays per frame (at least one)
1078 * @ccnt: how many frames per block (at least one)
1079 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1080 * the value to reload into bcnt when it decrements to zero
1081 * @sync_mode: ASYNC or ABSYNC
1082 *
1083 * See the EDMA3 documentation to understand how to configure and link
1084 * transfers using the fields in PaRAM slots. If you are not doing it
1085 * all at once with edma_write_slot(), you will use this routine
1086 * plus two calls each for source and destination, setting the initial
1087 * address and saying how to index that address.
1088 *
1089 * An example of an A-Synchronized transfer is a serial link using a
1090 * single word shift register. In that case, @acnt would be equal to
1091 * that word size; the serial controller issues a DMA synchronization
1092 * event to transfer each word, and memory access by the DMA transfer
1093 * controller will be word-at-a-time.
1094 *
1095 * An example of an AB-Synchronized transfer is a device using a FIFO.
1096 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1097 * The controller with the FIFO issues DMA synchronization events when
1098 * the FIFO threshold is reached, and the DMA transfer controller will
1099 * transfer one frame to (or from) the FIFO. It will probably use
1100 * efficient burst modes to access memory.
1101 */
1102 void edma_set_transfer_params(unsigned slot,
1103 u16 acnt, u16 bcnt, u16 ccnt,
1104 u16 bcnt_rld, enum sync_dimension sync_mode)
1105 {
1106 unsigned ctlr;
1107
1108 ctlr = EDMA_CTLR(slot);
1109 slot = EDMA_CHAN_SLOT(slot);
1110
1111 if (slot < edma_cc[ctlr]->num_slots) {
1112 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1113 0x0000ffff, bcnt_rld << 16);
1114 if (sync_mode == ASYNC)
1115 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1116 else
1117 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1118 /* Set the acount, bcount, ccount registers */
1119 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1120 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1121 }
1122 }
1123 EXPORT_SYMBOL(edma_set_transfer_params);
1124
1125 /**
1126 * edma_link - link one parameter RAM slot to another
1127 * @from: parameter RAM slot originating the link
1128 * @to: parameter RAM slot which is the link target
1129 *
1130 * The originating slot should not be part of any active DMA transfer.
1131 */
1132 void edma_link(unsigned from, unsigned to)
1133 {
1134 unsigned ctlr_from, ctlr_to;
1135
1136 ctlr_from = EDMA_CTLR(from);
1137 from = EDMA_CHAN_SLOT(from);
1138 ctlr_to = EDMA_CTLR(to);
1139 to = EDMA_CHAN_SLOT(to);
1140
1141 if (from >= edma_cc[ctlr_from]->num_slots)
1142 return;
1143 if (to >= edma_cc[ctlr_to]->num_slots)
1144 return;
1145 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1146 PARM_OFFSET(to));
1147 }
1148 EXPORT_SYMBOL(edma_link);
1149
1150 /**
1151 * edma_unlink - cut link from one parameter RAM slot
1152 * @from: parameter RAM slot originating the link
1153 *
1154 * The originating slot should not be part of any active DMA transfer.
1155 * Its link is set to 0xffff.
1156 */
1157 void edma_unlink(unsigned from)
1158 {
1159 unsigned ctlr;
1160
1161 ctlr = EDMA_CTLR(from);
1162 from = EDMA_CHAN_SLOT(from);
1163
1164 if (from >= edma_cc[ctlr]->num_slots)
1165 return;
1166 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1167 }
1168 EXPORT_SYMBOL(edma_unlink);
1169
1170 /*-----------------------------------------------------------------------*/
1171
1172 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1173
1174 /**
1175 * edma_write_slot - write parameter RAM data for slot
1176 * @slot: number of parameter RAM slot being modified
1177 * @param: data to be written into parameter RAM slot
1178 *
1179 * Use this to assign all parameters of a transfer at once. This
1180 * allows more efficient setup of transfers than issuing multiple
1181 * calls to set up those parameters in small pieces, and provides
1182 * complete control over all transfer options.
1183 */
1184 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1185 {
1186 unsigned ctlr;
1187
1188 ctlr = EDMA_CTLR(slot);
1189 slot = EDMA_CHAN_SLOT(slot);
1190
1191 if (slot >= edma_cc[ctlr]->num_slots)
1192 return;
1193 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1194 PARM_SIZE);
1195 }
1196 EXPORT_SYMBOL(edma_write_slot);
1197
1198 /**
1199 * edma_read_slot - read parameter RAM data from slot
1200 * @slot: number of parameter RAM slot being copied
1201 * @param: where to store copy of parameter RAM data
1202 *
1203 * Use this to read data from a parameter RAM slot, perhaps to
1204 * save them as a template for later reuse.
1205 */
1206 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1207 {
1208 unsigned ctlr;
1209
1210 ctlr = EDMA_CTLR(slot);
1211 slot = EDMA_CHAN_SLOT(slot);
1212
1213 if (slot >= edma_cc[ctlr]->num_slots)
1214 return;
1215 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1216 PARM_SIZE);
1217 }
1218 EXPORT_SYMBOL(edma_read_slot);
1219
1220 /*-----------------------------------------------------------------------*/
1221
1222 /* Various EDMA channel control operations */
1223
1224 /**
1225 * edma_pause - pause dma on a channel
1226 * @channel: on which edma_start() has been called
1227 *
1228 * This temporarily disables EDMA hardware events on the specified channel,
1229 * preventing them from triggering new transfers on its behalf
1230 */
1231 void edma_pause(unsigned channel)
1232 {
1233 unsigned ctlr;
1234
1235 ctlr = EDMA_CTLR(channel);
1236 channel = EDMA_CHAN_SLOT(channel);
1237
1238 if (channel < edma_cc[ctlr]->num_channels) {
1239 unsigned int mask = BIT(channel & 0x1f);
1240
1241 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1242 }
1243 }
1244 EXPORT_SYMBOL(edma_pause);
1245
1246 /**
1247 * edma_resume - resumes dma on a paused channel
1248 * @channel: on which edma_pause() has been called
1249 *
1250 * This re-enables EDMA hardware events on the specified channel.
1251 */
1252 void edma_resume(unsigned channel)
1253 {
1254 unsigned ctlr;
1255
1256 ctlr = EDMA_CTLR(channel);
1257 channel = EDMA_CHAN_SLOT(channel);
1258
1259 if (channel < edma_cc[ctlr]->num_channels) {
1260 unsigned int mask = BIT(channel & 0x1f);
1261
1262 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1263 }
1264 }
1265 EXPORT_SYMBOL(edma_resume);
1266
1267 int edma_trigger_channel(unsigned channel)
1268 {
1269 unsigned ctlr;
1270 unsigned int mask;
1271
1272 ctlr = EDMA_CTLR(channel);
1273 channel = EDMA_CHAN_SLOT(channel);
1274 mask = BIT(channel & 0x1f);
1275
1276 edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
1277
1278 pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
1279 edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
1280 return 0;
1281 }
1282 EXPORT_SYMBOL(edma_trigger_channel);
1283
1284 /**
1285 * edma_start - start dma on a channel
1286 * @channel: channel being activated
1287 *
1288 * Channels with event associations will be triggered by their hardware
1289 * events, and channels without such associations will be triggered by
1290 * software. (At this writing there is no interface for using software
1291 * triggers except with channels that don't support hardware triggers.)
1292 *
1293 * Returns zero on success, else negative errno.
1294 */
1295 int edma_start(unsigned channel)
1296 {
1297 unsigned ctlr;
1298
1299 ctlr = EDMA_CTLR(channel);
1300 channel = EDMA_CHAN_SLOT(channel);
1301
1302 if (channel < edma_cc[ctlr]->num_channels) {
1303 int j = channel >> 5;
1304 unsigned int mask = BIT(channel & 0x1f);
1305
1306 /* EDMA channels without event association */
1307 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1308 pr_debug("EDMA: ESR%d %08x\n", j,
1309 edma_shadow0_read_array(ctlr, SH_ESR, j));
1310 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1311 return 0;
1312 }
1313
1314 /* EDMA channel with event association */
1315 pr_debug("EDMA: ER%d %08x\n", j,
1316 edma_shadow0_read_array(ctlr, SH_ER, j));
1317 /* Clear any pending event or error */
1318 edma_write_array(ctlr, EDMA_ECR, j, mask);
1319 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1320 /* Clear any SER */
1321 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1322 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1323 pr_debug("EDMA: EER%d %08x\n", j,
1324 edma_shadow0_read_array(ctlr, SH_EER, j));
1325 return 0;
1326 }
1327
1328 return -EINVAL;
1329 }
1330 EXPORT_SYMBOL(edma_start);
1331
1332 /**
1333 * edma_stop - stops dma on the channel passed
1334 * @channel: channel being deactivated
1335 *
1336 * When @lch is a channel, any active transfer is paused and
1337 * all pending hardware events are cleared. The current transfer
1338 * may not be resumed, and the channel's Parameter RAM should be
1339 * reinitialized before being reused.
1340 */
1341 void edma_stop(unsigned channel)
1342 {
1343 unsigned ctlr;
1344
1345 ctlr = EDMA_CTLR(channel);
1346 channel = EDMA_CHAN_SLOT(channel);
1347
1348 if (channel < edma_cc[ctlr]->num_channels) {
1349 int j = channel >> 5;
1350 unsigned int mask = BIT(channel & 0x1f);
1351
1352 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1353 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1354 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1355 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1356
1357 pr_debug("EDMA: EER%d %08x\n", j,
1358 edma_shadow0_read_array(ctlr, SH_EER, j));
1359
1360 /* REVISIT: consider guarding against inappropriate event
1361 * chaining by overwriting with dummy_paramset.
1362 */
1363 }
1364 }
1365 EXPORT_SYMBOL(edma_stop);
1366
1367 /******************************************************************************
1368 *
1369 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1370 * been removed before EDMA has finished.It is usedful for removable media.
1371 * Arguments:
1372 * ch_no - channel no
1373 *
1374 * Return: zero on success, or corresponding error no on failure
1375 *
1376 * FIXME this should not be needed ... edma_stop() should suffice.
1377 *
1378 *****************************************************************************/
1379
1380 void edma_clean_channel(unsigned channel)
1381 {
1382 unsigned ctlr;
1383
1384 ctlr = EDMA_CTLR(channel);
1385 channel = EDMA_CHAN_SLOT(channel);
1386
1387 if (channel < edma_cc[ctlr]->num_channels) {
1388 int j = (channel >> 5);
1389 unsigned int mask = BIT(channel & 0x1f);
1390
1391 pr_debug("EDMA: EMR%d %08x\n", j,
1392 edma_read_array(ctlr, EDMA_EMR, j));
1393 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1394 /* Clear the corresponding EMR bits */
1395 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1396 /* Clear any SER */
1397 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1398 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1399 }
1400 }
1401 EXPORT_SYMBOL(edma_clean_channel);
1402
1403 /*
1404 * edma_clear_event - clear an outstanding event on the DMA channel
1405 * Arguments:
1406 * channel - channel number
1407 */
1408 void edma_clear_event(unsigned channel)
1409 {
1410 unsigned ctlr;
1411
1412 ctlr = EDMA_CTLR(channel);
1413 channel = EDMA_CHAN_SLOT(channel);
1414
1415 if (channel >= edma_cc[ctlr]->num_channels)
1416 return;
1417 if (channel < 32)
1418 edma_write(ctlr, EDMA_ECR, BIT(channel));
1419 else
1420 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
1421 }
1422 EXPORT_SYMBOL(edma_clear_event);
1423
1424 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1425
1426 static int edma_of_read_u32_to_s16_array(const struct device_node *np,
1427 const char *propname, s16 *out_values,
1428 size_t sz)
1429 {
1430 int ret;
1431
1432 ret = of_property_read_u16_array(np, propname, out_values, sz);
1433 if (ret)
1434 return ret;
1435
1436 /* Terminate it */
1437 *out_values++ = -1;
1438 *out_values++ = -1;
1439
1440 return 0;
1441 }
1442
1443 static int edma_xbar_event_map(struct device *dev,
1444 struct device_node *node,
1445 struct edma_soc_info *pdata, int len)
1446 {
1447 int ret, i;
1448 struct resource res;
1449 void __iomem *xbar;
1450 const s16 (*xbar_chans)[2];
1451 u32 shift, offset, mux;
1452
1453 xbar_chans = devm_kzalloc(dev,
1454 len/sizeof(s16) + 2*sizeof(s16),
1455 GFP_KERNEL);
1456 if (!xbar_chans)
1457 return -ENOMEM;
1458
1459 ret = of_address_to_resource(node, 1, &res);
1460 if (ret)
1461 return -EIO;
1462
1463 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1464 if (!xbar)
1465 return -ENOMEM;
1466
1467 ret = edma_of_read_u32_to_s16_array(node,
1468 "ti,edma-xbar-event-map",
1469 (s16 *)xbar_chans,
1470 len/sizeof(u32));
1471 if (ret)
1472 return -EIO;
1473
1474 for (i = 0; xbar_chans[i][0] != -1; i++) {
1475 shift = (xbar_chans[i][1] & 0x03) << 3;
1476 offset = xbar_chans[i][1] & 0xfffffffc;
1477 mux = readl(xbar + offset);
1478 mux &= ~(0xff << shift);
1479 mux |= xbar_chans[i][0] << shift;
1480 writel(mux, (xbar + offset));
1481 }
1482
1483 pdata->xbar_chans = xbar_chans;
1484
1485 return 0;
1486 }
1487
1488 static int edma_of_parse_dt(struct device *dev,
1489 struct device_node *node,
1490 struct edma_soc_info *pdata)
1491 {
1492 int ret = 0, i;
1493 u32 value;
1494 struct property *prop;
1495 size_t sz;
1496 struct edma_rsv_info *rsv_info;
1497 s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
1498
1499 memset(pdata, 0, sizeof(struct edma_soc_info));
1500
1501 ret = of_property_read_u32(node, "dma-channels", &value);
1502 if (ret < 0)
1503 return ret;
1504 pdata->n_channel = value;
1505
1506 ret = of_property_read_u32(node, "ti,edma-regions", &value);
1507 if (ret < 0)
1508 return ret;
1509 pdata->n_region = value;
1510
1511 ret = of_property_read_u32(node, "ti,edma-slots", &value);
1512 if (ret < 0)
1513 return ret;
1514 pdata->n_slot = value;
1515
1516 pdata->n_cc = 1;
1517
1518 rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
1519 if (!rsv_info)
1520 return -ENOMEM;
1521 pdata->rsv = rsv_info;
1522
1523 queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
1524 if (!queue_tc_map)
1525 return -ENOMEM;
1526
1527 for (i = 0; i < 3; i++) {
1528 queue_tc_map[i][0] = i;
1529 queue_tc_map[i][1] = i;
1530 }
1531 queue_tc_map[i][0] = -1;
1532 queue_tc_map[i][1] = -1;
1533
1534 pdata->queue_tc_mapping = queue_tc_map;
1535
1536 queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
1537 if (!queue_priority_map)
1538 return -ENOMEM;
1539
1540 for (i = 0; i < 3; i++) {
1541 queue_priority_map[i][0] = i;
1542 queue_priority_map[i][1] = i;
1543 }
1544 queue_priority_map[i][0] = -1;
1545 queue_priority_map[i][1] = -1;
1546
1547 pdata->queue_priority_mapping = queue_priority_map;
1548
1549 pdata->default_queue = 0;
1550
1551 prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
1552 if (prop)
1553 ret = edma_xbar_event_map(dev, node, pdata, sz);
1554
1555 return ret;
1556 }
1557
1558 static struct of_dma_filter_info edma_filter_info = {
1559 .filter_fn = edma_filter_fn,
1560 };
1561
1562 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1563 struct device_node *node)
1564 {
1565 struct edma_soc_info *info;
1566 int ret;
1567
1568 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1569 if (!info)
1570 return ERR_PTR(-ENOMEM);
1571
1572 ret = edma_of_parse_dt(dev, node, info);
1573 if (ret)
1574 return ERR_PTR(ret);
1575
1576 dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
1577 of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
1578 &edma_filter_info);
1579
1580 return info;
1581 }
1582 #else
1583 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1584 struct device_node *node)
1585 {
1586 return ERR_PTR(-ENOSYS);
1587 }
1588 #endif
1589
1590 static int edma_probe(struct platform_device *pdev)
1591 {
1592 struct edma_soc_info **info = pdev->dev.platform_data;
1593 struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
1594 s8 (*queue_priority_mapping)[2];
1595 s8 (*queue_tc_mapping)[2];
1596 int i, j, off, ln, found = 0;
1597 int status = -1;
1598 const s16 (*rsv_chans)[2];
1599 const s16 (*rsv_slots)[2];
1600 const s16 (*xbar_chans)[2];
1601 int irq[EDMA_MAX_CC] = {0, 0};
1602 int err_irq[EDMA_MAX_CC] = {0, 0};
1603 struct resource *r[EDMA_MAX_CC] = {NULL};
1604 struct resource res[EDMA_MAX_CC];
1605 char res_name[10];
1606 char irq_name[10];
1607 struct device_node *node = pdev->dev.of_node;
1608 struct device *dev = &pdev->dev;
1609 int ret;
1610
1611 if (node) {
1612 /* Check if this is a second instance registered */
1613 if (arch_num_cc) {
1614 dev_err(dev, "only one EDMA instance is supported via DT\n");
1615 return -ENODEV;
1616 }
1617
1618 ninfo[0] = edma_setup_info_from_dt(dev, node);
1619 if (IS_ERR(ninfo[0])) {
1620 dev_err(dev, "failed to get DT data\n");
1621 return PTR_ERR(ninfo[0]);
1622 }
1623
1624 info = ninfo;
1625 }
1626
1627 if (!info)
1628 return -ENODEV;
1629
1630 pm_runtime_enable(dev);
1631 ret = pm_runtime_get_sync(dev);
1632 if (ret < 0) {
1633 dev_err(dev, "pm_runtime_get_sync() failed\n");
1634 return ret;
1635 }
1636
1637 for (j = 0; j < EDMA_MAX_CC; j++) {
1638 if (!info[j]) {
1639 if (!found)
1640 return -ENODEV;
1641 break;
1642 }
1643 if (node) {
1644 ret = of_address_to_resource(node, j, &res[j]);
1645 if (!ret)
1646 r[j] = &res[j];
1647 } else {
1648 sprintf(res_name, "edma_cc%d", j);
1649 r[j] = platform_get_resource_byname(pdev,
1650 IORESOURCE_MEM,
1651 res_name);
1652 }
1653 if (!r[j]) {
1654 if (found)
1655 break;
1656 else
1657 return -ENODEV;
1658 } else {
1659 found = 1;
1660 }
1661
1662 edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
1663 if (IS_ERR(edmacc_regs_base[j]))
1664 return PTR_ERR(edmacc_regs_base[j]);
1665
1666 edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
1667 GFP_KERNEL);
1668 if (!edma_cc[j])
1669 return -ENOMEM;
1670
1671 edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
1672 EDMA_MAX_DMACH);
1673 edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
1674 EDMA_MAX_PARAMENTRY);
1675 edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
1676 EDMA_MAX_CC);
1677
1678 edma_cc[j]->default_queue = info[j]->default_queue;
1679
1680 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1681 edmacc_regs_base[j]);
1682
1683 for (i = 0; i < edma_cc[j]->num_slots; i++)
1684 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1685 &dummy_paramset, PARM_SIZE);
1686
1687 /* Mark all channels as unused */
1688 memset(edma_cc[j]->edma_unused, 0xff,
1689 sizeof(edma_cc[j]->edma_unused));
1690
1691 if (info[j]->rsv) {
1692
1693 /* Clear the reserved channels in unused list */
1694 rsv_chans = info[j]->rsv->rsv_chans;
1695 if (rsv_chans) {
1696 for (i = 0; rsv_chans[i][0] != -1; i++) {
1697 off = rsv_chans[i][0];
1698 ln = rsv_chans[i][1];
1699 clear_bits(off, ln,
1700 edma_cc[j]->edma_unused);
1701 }
1702 }
1703
1704 /* Set the reserved slots in inuse list */
1705 rsv_slots = info[j]->rsv->rsv_slots;
1706 if (rsv_slots) {
1707 for (i = 0; rsv_slots[i][0] != -1; i++) {
1708 off = rsv_slots[i][0];
1709 ln = rsv_slots[i][1];
1710 set_bits(off, ln,
1711 edma_cc[j]->edma_inuse);
1712 }
1713 }
1714 }
1715
1716 /* Clear the xbar mapped channels in unused list */
1717 xbar_chans = info[j]->xbar_chans;
1718 if (xbar_chans) {
1719 for (i = 0; xbar_chans[i][1] != -1; i++) {
1720 off = xbar_chans[i][1];
1721 clear_bits(off, 1,
1722 edma_cc[j]->edma_unused);
1723 }
1724 }
1725
1726 if (node) {
1727 irq[j] = irq_of_parse_and_map(node, 0);
1728 } else {
1729 sprintf(irq_name, "edma%d", j);
1730 irq[j] = platform_get_irq_byname(pdev, irq_name);
1731 }
1732 edma_cc[j]->irq_res_start = irq[j];
1733 status = devm_request_irq(&pdev->dev, irq[j],
1734 dma_irq_handler, 0, "edma",
1735 &pdev->dev);
1736 if (status < 0) {
1737 dev_dbg(&pdev->dev,
1738 "devm_request_irq %d failed --> %d\n",
1739 irq[j], status);
1740 return status;
1741 }
1742
1743 if (node) {
1744 err_irq[j] = irq_of_parse_and_map(node, 2);
1745 } else {
1746 sprintf(irq_name, "edma%d_err", j);
1747 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1748 }
1749 edma_cc[j]->irq_res_end = err_irq[j];
1750 status = devm_request_irq(&pdev->dev, err_irq[j],
1751 dma_ccerr_handler, 0,
1752 "edma_error", &pdev->dev);
1753 if (status < 0) {
1754 dev_dbg(&pdev->dev,
1755 "devm_request_irq %d failed --> %d\n",
1756 err_irq[j], status);
1757 return status;
1758 }
1759
1760 for (i = 0; i < edma_cc[j]->num_channels; i++)
1761 map_dmach_queue(j, i, info[j]->default_queue);
1762
1763 queue_tc_mapping = info[j]->queue_tc_mapping;
1764 queue_priority_mapping = info[j]->queue_priority_mapping;
1765
1766 /* Event queue to TC mapping */
1767 for (i = 0; queue_tc_mapping[i][0] != -1; i++)
1768 map_queue_tc(j, queue_tc_mapping[i][0],
1769 queue_tc_mapping[i][1]);
1770
1771 /* Event queue priority mapping */
1772 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1773 assign_priority_to_queue(j,
1774 queue_priority_mapping[i][0],
1775 queue_priority_mapping[i][1]);
1776
1777 /* Map the channel to param entry if channel mapping logic
1778 * exist
1779 */
1780 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1781 map_dmach_param(j);
1782
1783 for (i = 0; i < info[j]->n_region; i++) {
1784 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1785 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1786 edma_write_array(j, EDMA_QRAE, i, 0x0);
1787 }
1788 arch_num_cc++;
1789 }
1790
1791 return 0;
1792 }
1793
1794 static struct platform_driver edma_driver = {
1795 .driver = {
1796 .name = "edma",
1797 .of_match_table = edma_of_ids,
1798 },
1799 .probe = edma_probe,
1800 };
1801
1802 static int __init edma_init(void)
1803 {
1804 return platform_driver_probe(&edma_driver, edma_probe);
1805 }
1806 arch_initcall(edma_init);
1807
Linux with added FPC-III support