2 * linux/arch/arm/common/timer-sp.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/clk.h>
22 #include <linux/clocksource.h>
23 #include <linux/clockchips.h>
24 #include <linux/err.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/sched_clock.h>
33 #include <asm/hardware/arm_timer.h>
34 #include <asm/hardware/timer-sp.h>
36 static long __init
sp804_get_clock_rate(struct clk
*clk
)
41 err
= clk_prepare(clk
);
43 pr_err("sp804: clock failed to prepare: %d\n", err
);
48 err
= clk_enable(clk
);
50 pr_err("sp804: clock failed to enable: %d\n", err
);
56 rate
= clk_get_rate(clk
);
58 pr_err("sp804: clock failed to get rate: %ld\n", rate
);
67 static void __iomem
*sched_clock_base
;
69 static u32
sp804_read(void)
71 return ~readl_relaxed(sched_clock_base
+ TIMER_VALUE
);
74 void __init
__sp804_clocksource_and_sched_clock_init(void __iomem
*base
,
82 clk
= clk_get_sys("sp804", name
);
84 pr_err("sp804: clock not found: %d\n",
90 rate
= sp804_get_clock_rate(clk
);
95 /* setup timer 0 as free-running clocksource */
96 writel(0, base
+ TIMER_CTRL
);
97 writel(0xffffffff, base
+ TIMER_LOAD
);
98 writel(0xffffffff, base
+ TIMER_VALUE
);
99 writel(TIMER_CTRL_32BIT
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
,
102 clocksource_mmio_init(base
+ TIMER_VALUE
, name
,
103 rate
, 200, 32, clocksource_mmio_readl_down
);
105 if (use_sched_clock
) {
106 sched_clock_base
= base
;
107 setup_sched_clock(sp804_read
, 32, rate
);
112 static void __iomem
*clkevt_base
;
113 static unsigned long clkevt_reload
;
116 * IRQ handler for the timer
118 static irqreturn_t
sp804_timer_interrupt(int irq
, void *dev_id
)
120 struct clock_event_device
*evt
= dev_id
;
122 /* clear the interrupt */
123 writel(1, clkevt_base
+ TIMER_INTCLR
);
125 evt
->event_handler(evt
);
130 static void sp804_set_mode(enum clock_event_mode mode
,
131 struct clock_event_device
*evt
)
133 unsigned long ctrl
= TIMER_CTRL_32BIT
| TIMER_CTRL_IE
;
135 writel(ctrl
, clkevt_base
+ TIMER_CTRL
);
138 case CLOCK_EVT_MODE_PERIODIC
:
139 writel(clkevt_reload
, clkevt_base
+ TIMER_LOAD
);
140 ctrl
|= TIMER_CTRL_PERIODIC
| TIMER_CTRL_ENABLE
;
143 case CLOCK_EVT_MODE_ONESHOT
:
144 /* period set, and timer enabled in 'next_event' hook */
145 ctrl
|= TIMER_CTRL_ONESHOT
;
148 case CLOCK_EVT_MODE_UNUSED
:
149 case CLOCK_EVT_MODE_SHUTDOWN
:
154 writel(ctrl
, clkevt_base
+ TIMER_CTRL
);
157 static int sp804_set_next_event(unsigned long next
,
158 struct clock_event_device
*evt
)
160 unsigned long ctrl
= readl(clkevt_base
+ TIMER_CTRL
);
162 writel(next
, clkevt_base
+ TIMER_LOAD
);
163 writel(ctrl
| TIMER_CTRL_ENABLE
, clkevt_base
+ TIMER_CTRL
);
168 static struct clock_event_device sp804_clockevent
= {
169 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
|
170 CLOCK_EVT_FEAT_DYNIRQ
,
171 .set_mode
= sp804_set_mode
,
172 .set_next_event
= sp804_set_next_event
,
176 static struct irqaction sp804_timer_irq
= {
178 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
179 .handler
= sp804_timer_interrupt
,
180 .dev_id
= &sp804_clockevent
,
183 void __init
__sp804_clockevents_init(void __iomem
*base
, unsigned int irq
, struct clk
*clk
, const char *name
)
185 struct clock_event_device
*evt
= &sp804_clockevent
;
189 clk
= clk_get_sys("sp804", name
);
191 pr_err("sp804: %s clock not found: %d\n", name
,
196 rate
= sp804_get_clock_rate(clk
);
201 clkevt_reload
= DIV_ROUND_CLOSEST(rate
, HZ
);
204 evt
->cpumask
= cpu_possible_mask
;
206 writel(0, base
+ TIMER_CTRL
);
208 setup_irq(irq
, &sp804_timer_irq
);
209 clockevents_config_and_register(evt
, rate
, 0xf, 0xffffffff);
212 static void __init
sp804_of_init(struct device_node
*np
)
214 static bool initialized
= false;
218 struct clk
*clk1
, *clk2
;
219 const char *name
= of_get_property(np
, "compatible", NULL
);
221 base
= of_iomap(np
, 0);
225 /* Ensure timers are disabled */
226 writel(0, base
+ TIMER_CTRL
);
227 writel(0, base
+ TIMER_2_BASE
+ TIMER_CTRL
);
229 if (initialized
|| !of_device_is_available(np
))
232 clk1
= of_clk_get(np
, 0);
236 /* Get the 2nd clock if the timer has 2 timer clocks */
237 if (of_count_phandle_with_args(np
, "clocks", "#clock-cells") == 3) {
238 clk2
= of_clk_get(np
, 1);
240 pr_err("sp804: %s clock not found: %d\n", np
->name
,
247 irq
= irq_of_parse_and_map(np
, 0);
251 of_property_read_u32(np
, "arm,sp804-has-irq", &irq_num
);
253 __sp804_clockevents_init(base
+ TIMER_2_BASE
, irq
, clk2
, name
);
254 __sp804_clocksource_and_sched_clock_init(base
, name
, clk1
, 1);
256 __sp804_clockevents_init(base
, irq
, clk1
, name
);
257 __sp804_clocksource_and_sched_clock_init(base
+ TIMER_2_BASE
,
266 CLOCKSOURCE_OF_DECLARE(sp804
, "arm,sp804", sp804_of_init
);
268 static void __init
integrator_cp_of_init(struct device_node
*np
)
270 static int init_count
= 0;
273 const char *name
= of_get_property(np
, "compatible", NULL
);
275 base
= of_iomap(np
, 0);
279 /* Ensure timer is disabled */
280 writel(0, base
+ TIMER_CTRL
);
282 if (init_count
== 2 || !of_device_is_available(np
))
286 sp804_clocksource_init(base
, name
);
288 irq
= irq_of_parse_and_map(np
, 0);
292 sp804_clockevents_init(base
, irq
, name
);
300 CLOCKSOURCE_OF_DECLARE(intcp
, "arm,integrator-cp-timer", integrator_cp_of_init
);