| blob | ec3e5cf46308108616387013f0f86f124dcf114f |
1 /*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
18 #include <asm/assembler.h>
19 #include <asm/memory.h>
20 #include <asm/glue-df.h>
21 #include <asm/glue-pf.h>
22 #include <asm/vfpmacros.h>
23 #ifndef CONFIG_MULTI_IRQ_HANDLER
24 #include <mach/entry-macro.S>
25 #endif
26 #include <asm/thread_notify.h>
27 #include <asm/unwind.h>
28 #include <asm/unistd.h>
29 #include <asm/tls.h>
30 #include <asm/system_info.h>
32 #include "entry-header.S"
33 #include <asm/entry-macro-multi.S>
35 /*
36 * Interrupt handling.
37 */
38 .macro irq_handler
39 #ifdef CONFIG_MULTI_IRQ_HANDLER
40 ldr r1, =handle_arch_irq
41 mov r0, sp
42 adr lr, BSYM(9997f)
43 ldr pc, [r1]
44 #else
45 arch_irq_handler_default
46 #endif
47 9997:
48 .endm
50 .macro pabt_helper
51 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
52 #ifdef MULTI_PABORT
53 ldr ip, .LCprocfns
54 mov lr, pc
55 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
56 #else
57 bl CPU_PABORT_HANDLER
58 #endif
59 .endm
61 .macro dabt_helper
63 @
64 @ Call the processor-specific abort handler:
65 @
66 @ r2 - pt_regs
67 @ r4 - aborted context pc
68 @ r5 - aborted context psr
69 @
70 @ The abort handler must return the aborted address in r0, and
71 @ the fault status register in r1. r9 must be preserved.
72 @
73 #ifdef MULTI_DABORT
74 ldr ip, .LCprocfns
75 mov lr, pc
76 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
77 #else
78 bl CPU_DABORT_HANDLER
79 #endif
80 .endm
82 #ifdef CONFIG_KPROBES
83 .section .kprobes.text,"ax",%progbits
84 #else
85 .text
86 #endif
88 /*
89 * Invalid mode handlers
90 */
91 .macro inv_entry, reason
92 sub sp, sp, #S_FRAME_SIZE
93 ARM( stmib sp, {r1 - lr} )
94 THUMB( stmia sp, {r0 - r12} )
95 THUMB( str sp, [sp, #S_SP] )
96 THUMB( str lr, [sp, #S_LR] )
97 mov r1, #\reason
98 .endm
100 __pabt_invalid:
101 inv_entry BAD_PREFETCH
102 b common_invalid
103 ENDPROC(__pabt_invalid)
105 __dabt_invalid:
106 inv_entry BAD_DATA
107 b common_invalid
108 ENDPROC(__dabt_invalid)
110 __irq_invalid:
111 inv_entry BAD_IRQ
112 b common_invalid
113 ENDPROC(__irq_invalid)
115 __und_invalid:
116 inv_entry BAD_UNDEFINSTR
118 @
119 @ XXX fall through to common_invalid
120 @
122 @
123 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
124 @
125 common_invalid:
126 zero_fp
128 ldmia r0, {r4 - r6}
129 add r0, sp, #S_PC @ here for interlock avoidance
130 mov r7, #-1 @ "" "" "" ""
131 str r4, [sp] @ save preserved r0
132 stmia r0, {r5 - r7} @ lr_<exception>,
133 @ cpsr_<exception>, "old_r0"
135 mov r0, sp
136 b bad_mode
137 ENDPROC(__und_invalid)
139 /*
140 * SVC mode handlers
141 */
143 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
144 #define SPFIX(code...) code
145 #else
146 #define SPFIX(code...)
147 #endif
149 .macro svc_entry, stack_hole=0
150 UNWIND(.fnstart )
151 UNWIND(.save {r0 - pc} )
152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
153 #ifdef CONFIG_THUMB2_KERNEL
154 SPFIX( str r0, [sp] ) @ temporarily saved
155 SPFIX( mov r0, sp )
156 SPFIX( tst r0, #4 ) @ test original stack alignment
157 SPFIX( ldr r0, [sp] ) @ restored
158 #else
159 SPFIX( tst sp, #4 )
160 #endif
161 SPFIX( subeq sp, sp, #4 )
162 stmia sp, {r1 - r12}
164 ldmia r0, {r3 - r5}
165 add r7, sp, #S_SP - 4 @ here for interlock avoidance
166 mov r6, #-1 @ "" "" "" ""
167 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
168 SPFIX( addeq r2, r2, #4 )
169 str r3, [sp, #-4]! @ save the "real" r0 copied
170 @ from the exception stack
172 mov r3, lr
174 @
175 @ We are now ready to fill in the remaining blanks on the stack:
176 @
177 @ r2 - sp_svc
178 @ r3 - lr_svc
179 @ r4 - lr_<exception>, already fixed up for correct return/restart
180 @ r5 - spsr_<exception>
181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
182 @
183 stmia r7, {r2 - r6}
185 #ifdef CONFIG_TRACE_IRQFLAGS
186 bl trace_hardirqs_off
187 #endif
188 .endm
190 .align 5
191 __dabt_svc:
192 svc_entry
193 mov r2, sp
194 dabt_helper
195 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
196 svc_exit r5 @ return from exception
197 UNWIND(.fnend )
198 ENDPROC(__dabt_svc)
200 .align 5
201 __irq_svc:
202 svc_entry
203 irq_handler
205 #ifdef CONFIG_PREEMPT
206 get_thread_info tsk
207 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
208 ldr r0, [tsk, #TI_FLAGS] @ get flags
209 teq r8, #0 @ if preempt count != 0
210 movne r0, #0 @ force flags to 0
211 tst r0, #_TIF_NEED_RESCHED
212 blne svc_preempt
213 #endif
215 svc_exit r5, irq = 1 @ return from exception
216 UNWIND(.fnend )
217 ENDPROC(__irq_svc)
219 .ltorg
221 #ifdef CONFIG_PREEMPT
222 svc_preempt:
223 mov r8, lr
224 1: bl preempt_schedule_irq @ irq en/disable is done inside
225 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
226 tst r0, #_TIF_NEED_RESCHED
227 moveq pc, r8 @ go again
228 b 1b
229 #endif
231 __und_fault:
232 @ Correct the PC such that it is pointing at the instruction
233 @ which caused the fault. If the faulting instruction was ARM
234 @ the PC will be pointing at the next instruction, and have to
235 @ subtract 4. Otherwise, it is Thumb, and the PC will be
236 @ pointing at the second half of the Thumb instruction. We
237 @ have to subtract 2.
238 ldr r2, [r0, #S_PC]
239 sub r2, r2, r1
240 str r2, [r0, #S_PC]
241 b do_undefinstr
242 ENDPROC(__und_fault)
244 .align 5
245 __und_svc:
246 #ifdef CONFIG_KPROBES
247 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
248 @ it obviously needs free stack space which then will belong to
249 @ the saved context.
250 svc_entry 64
251 #else
252 svc_entry
253 #endif
254 @
255 @ call emulation code, which returns using r9 if it has emulated
256 @ the instruction, or the more conventional lr if we are to treat
257 @ this as a real undefined instruction
258 @
259 @ r0 - instruction
260 @
261 #ifndef CONFIG_THUMB2_KERNEL
262 ldr r0, [r4, #-4]
263 #else
264 mov r1, #2
265 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
266 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
267 blo __und_svc_fault
268 ldrh r9, [r4] @ bottom 16 bits
269 add r4, r4, #2
270 str r4, [sp, #S_PC]
271 orr r0, r9, r0, lsl #16
272 #endif
273 adr r9, BSYM(__und_svc_finish)
274 mov r2, r4
275 bl call_fpe
277 mov r1, #4 @ PC correction to apply
278 __und_svc_fault:
279 mov r0, sp @ struct pt_regs *regs
280 bl __und_fault
282 __und_svc_finish:
283 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
284 svc_exit r5 @ return from exception
285 UNWIND(.fnend )
286 ENDPROC(__und_svc)
288 .align 5
289 __pabt_svc:
290 svc_entry
291 mov r2, sp @ regs
292 pabt_helper
293 svc_exit r5 @ return from exception
294 UNWIND(.fnend )
295 ENDPROC(__pabt_svc)
297 .align 5
298 .LCcralign:
299 .word cr_alignment
300 #ifdef MULTI_DABORT
301 .LCprocfns:
302 .word processor
303 #endif
304 .LCfp:
305 .word fp_enter
307 /*
308 * User mode handlers
309 *
310 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
311 */
313 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
314 #error "sizeof(struct pt_regs) must be a multiple of 8"
315 #endif
317 .macro usr_entry
318 UNWIND(.fnstart )
319 UNWIND(.cantunwind ) @ don't unwind the user space
320 sub sp, sp, #S_FRAME_SIZE
321 ARM( stmib sp, {r1 - r12} )
322 THUMB( stmia sp, {r0 - r12} )
324 ldmia r0, {r3 - r5}
325 add r0, sp, #S_PC @ here for interlock avoidance
326 mov r6, #-1 @ "" "" "" ""
328 str r3, [sp] @ save the "real" r0 copied
329 @ from the exception stack
331 @
332 @ We are now ready to fill in the remaining blanks on the stack:
333 @
334 @ r4 - lr_<exception>, already fixed up for correct return/restart
335 @ r5 - spsr_<exception>
336 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
337 @
338 @ Also, separately save sp_usr and lr_usr
339 @
340 stmia r0, {r4 - r6}
341 ARM( stmdb r0, {sp, lr}^ )
342 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
344 @
345 @ Enable the alignment trap while in kernel mode
346 @
347 alignment_trap r0
349 @
350 @ Clear FP to mark the first stack frame
351 @
352 zero_fp
354 #ifdef CONFIG_IRQSOFF_TRACER
355 bl trace_hardirqs_off
356 #endif
357 ct_user_exit save = 0
358 .endm
360 .macro kuser_cmpxchg_check
361 #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \
362 !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
363 #ifndef CONFIG_MMU
364 #warning "NPTL on non MMU needs fixing"
365 #else
366 @ Make sure our user space atomic helper is restarted
367 @ if it was interrupted in a critical region. Here we
368 @ perform a quick test inline since it should be false
369 @ 99.9999% of the time. The rest is done out of line.
370 cmp r4, #TASK_SIZE
371 blhs kuser_cmpxchg64_fixup
372 #endif
373 #endif
374 .endm
376 .align 5
377 __dabt_usr:
378 usr_entry
379 kuser_cmpxchg_check
380 mov r2, sp
381 dabt_helper
382 b ret_from_exception
383 UNWIND(.fnend )
384 ENDPROC(__dabt_usr)
386 .align 5
387 __irq_usr:
388 usr_entry
389 kuser_cmpxchg_check
390 irq_handler
391 get_thread_info tsk
392 mov why, #0
393 b ret_to_user_from_irq
394 UNWIND(.fnend )
395 ENDPROC(__irq_usr)
397 .ltorg
399 .align 5
400 __und_usr:
401 usr_entry
403 mov r2, r4
404 mov r3, r5
406 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
407 @ faulting instruction depending on Thumb mode.
408 @ r3 = regs->ARM_cpsr
409 @
410 @ The emulation code returns using r9 if it has emulated the
411 @ instruction, or the more conventional lr if we are to treat
412 @ this as a real undefined instruction
413 @
414 adr r9, BSYM(ret_from_exception)
416 tst r3, #PSR_T_BIT @ Thumb mode?
417 bne __und_usr_thumb
418 sub r4, r2, #4 @ ARM instr at LR - 4
419 1: ldrt r0, [r4]
420 #ifdef CONFIG_CPU_ENDIAN_BE8
421 rev r0, r0 @ little endian instruction
422 #endif
423 @ r0 = 32-bit ARM instruction which caused the exception
424 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
425 @ r4 = PC value for the faulting instruction
426 @ lr = 32-bit undefined instruction function
427 adr lr, BSYM(__und_usr_fault_32)
428 b call_fpe
430 __und_usr_thumb:
431 @ Thumb instruction
432 sub r4, r2, #2 @ First half of thumb instr at LR - 2
433 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
434 /*
435 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
436 * can never be supported in a single kernel, this code is not applicable at
437 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
438 * made about .arch directives.
439 */
440 #if __LINUX_ARM_ARCH__ < 7
441 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
442 #define NEED_CPU_ARCHITECTURE
443 ldr r5, .LCcpu_architecture
444 ldr r5, [r5]
445 cmp r5, #CPU_ARCH_ARMv7
446 blo __und_usr_fault_16 @ 16bit undefined instruction
447 /*
448 * The following code won't get run unless the running CPU really is v7, so
449 * coding round the lack of ldrht on older arches is pointless. Temporarily
450 * override the assembler target arch with the minimum required instead:
451 */
452 .arch armv6t2
453 #endif
454 2: ldrht r5, [r4]
455 cmp r5, #0xe800 @ 32bit instruction if xx != 0
456 blo __und_usr_fault_16 @ 16bit undefined instruction
457 3: ldrht r0, [r2]
458 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
459 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
460 orr r0, r0, r5, lsl #16
461 adr lr, BSYM(__und_usr_fault_32)
462 @ r0 = the two 16-bit Thumb instructions which caused the exception
463 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
464 @ r4 = PC value for the first 16-bit Thumb instruction
465 @ lr = 32bit undefined instruction function
467 #if __LINUX_ARM_ARCH__ < 7
468 /* If the target arch was overridden, change it back: */
469 #ifdef CONFIG_CPU_32v6K
470 .arch armv6k
471 #else
472 .arch armv6
473 #endif
474 #endif /* __LINUX_ARM_ARCH__ < 7 */
475 #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
476 b __und_usr_fault_16
477 #endif
478 UNWIND(.fnend)
479 ENDPROC(__und_usr)
481 /*
482 * The out of line fixup for the ldrt instructions above.
483 */
484 .pushsection .fixup, "ax"
485 .align 2
486 4: mov pc, r9
487 .popsection
488 .pushsection __ex_table,"a"
489 .long 1b, 4b
490 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
491 .long 2b, 4b
492 .long 3b, 4b
493 #endif
494 .popsection
496 /*
497 * Check whether the instruction is a co-processor instruction.
498 * If yes, we need to call the relevant co-processor handler.
499 *
500 * Note that we don't do a full check here for the co-processor
501 * instructions; all instructions with bit 27 set are well
502 * defined. The only instructions that should fault are the
503 * co-processor instructions. However, we have to watch out
504 * for the ARM6/ARM7 SWI bug.
505 *
506 * NEON is a special case that has to be handled here. Not all
507 * NEON instructions are co-processor instructions, so we have
508 * to make a special case of checking for them. Plus, there's
509 * five groups of them, so we have a table of mask/opcode pairs
510 * to check against, and if any match then we branch off into the
511 * NEON handler code.
512 *
513 * Emulators may wish to make use of the following registers:
514 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
515 * r2 = PC value to resume execution after successful emulation
516 * r9 = normal "successful" return address
517 * r10 = this threads thread_info structure
518 * lr = unrecognised instruction return address
519 * IRQs disabled, FIQs enabled.
520 */
521 @
522 @ Fall-through from Thumb-2 __und_usr
523 @
524 #ifdef CONFIG_NEON
525 get_thread_info r10 @ get current thread
526 adr r6, .LCneon_thumb_opcodes
527 b 2f
528 #endif
529 call_fpe:
530 get_thread_info r10 @ get current thread
531 #ifdef CONFIG_NEON
532 adr r6, .LCneon_arm_opcodes
533 2: ldr r5, [r6], #4 @ mask value
534 ldr r7, [r6], #4 @ opcode bits matching in mask
535 cmp r5, #0 @ end mask?
536 beq 1f
537 and r8, r0, r5
538 cmp r8, r7 @ NEON instruction?
539 bne 2b
540 mov r7, #1
541 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
542 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
543 b do_vfp @ let VFP handler handle this
544 1:
545 #endif
546 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
547 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
548 moveq pc, lr
549 and r8, r0, #0x00000f00 @ mask out CP number
550 THUMB( lsr r8, r8, #8 )
551 mov r7, #1
552 add r6, r10, #TI_USED_CP
553 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
554 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
555 #ifdef CONFIG_IWMMXT
556 @ Test if we need to give access to iWMMXt coprocessors
557 ldr r5, [r10, #TI_FLAGS]
558 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
559 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
560 bcs iwmmxt_task_enable
561 #endif
562 ARM( add pc, pc, r8, lsr #6 )
563 THUMB( lsl r8, r8, #2 )
564 THUMB( add pc, r8 )
565 nop
567 movw_pc lr @ CP#0
568 W(b) do_fpe @ CP#1 (FPE)
569 W(b) do_fpe @ CP#2 (FPE)
570 movw_pc lr @ CP#3
571 #ifdef CONFIG_CRUNCH
572 b crunch_task_enable @ CP#4 (MaverickCrunch)
573 b crunch_task_enable @ CP#5 (MaverickCrunch)
574 b crunch_task_enable @ CP#6 (MaverickCrunch)
575 #else
576 movw_pc lr @ CP#4
577 movw_pc lr @ CP#5
578 movw_pc lr @ CP#6
579 #endif
580 movw_pc lr @ CP#7
581 movw_pc lr @ CP#8
582 movw_pc lr @ CP#9
583 #ifdef CONFIG_VFP
584 W(b) do_vfp @ CP#10 (VFP)
585 W(b) do_vfp @ CP#11 (VFP)
586 #else
587 movw_pc lr @ CP#10 (VFP)
588 movw_pc lr @ CP#11 (VFP)
589 #endif
590 movw_pc lr @ CP#12
591 movw_pc lr @ CP#13
592 movw_pc lr @ CP#14 (Debug)
593 movw_pc lr @ CP#15 (Control)
595 #ifdef NEED_CPU_ARCHITECTURE
596 .align 2
597 .LCcpu_architecture:
598 .word __cpu_architecture
599 #endif
601 #ifdef CONFIG_NEON
602 .align 6
604 .LCneon_arm_opcodes:
605 .word 0xfe000000 @ mask
606 .word 0xf2000000 @ opcode
608 .word 0xff100000 @ mask
609 .word 0xf4000000 @ opcode
611 .word 0x00000000 @ mask
612 .word 0x00000000 @ opcode
614 .LCneon_thumb_opcodes:
615 .word 0xef000000 @ mask
616 .word 0xef000000 @ opcode
618 .word 0xff100000 @ mask
619 .word 0xf9000000 @ opcode
621 .word 0x00000000 @ mask
622 .word 0x00000000 @ opcode
623 #endif
625 do_fpe:
626 enable_irq
627 ldr r4, .LCfp
628 add r10, r10, #TI_FPSTATE @ r10 = workspace
629 ldr pc, [r4] @ Call FP module USR entry point
631 /*
632 * The FP module is called with these registers set:
633 * r0 = instruction
634 * r2 = PC+4
635 * r9 = normal "successful" return address
636 * r10 = FP workspace
637 * lr = unrecognised FP instruction return address
638 */
640 .pushsection .data
641 ENTRY(fp_enter)
642 .word no_fp
643 .popsection
645 ENTRY(no_fp)
646 mov pc, lr
647 ENDPROC(no_fp)
649 __und_usr_fault_32:
650 mov r1, #4
651 b 1f
652 __und_usr_fault_16:
653 mov r1, #2
654 1: enable_irq
655 mov r0, sp
656 adr lr, BSYM(ret_from_exception)
657 b __und_fault
658 ENDPROC(__und_usr_fault_32)
659 ENDPROC(__und_usr_fault_16)
661 .align 5
662 __pabt_usr:
663 usr_entry
664 mov r2, sp @ regs
665 pabt_helper
666 UNWIND(.fnend )
667 /* fall through */
668 /*
669 * This is the return code to user mode for abort handlers
670 */
671 ENTRY(ret_from_exception)
672 UNWIND(.fnstart )
673 UNWIND(.cantunwind )
674 get_thread_info tsk
675 mov why, #0
676 b ret_to_user
677 UNWIND(.fnend )
678 ENDPROC(__pabt_usr)
679 ENDPROC(ret_from_exception)
681 /*
682 * Register switch for ARMv3 and ARMv4 processors
683 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
684 * previous and next are guaranteed not to be the same.
685 */
686 ENTRY(__switch_to)
687 UNWIND(.fnstart )
688 UNWIND(.cantunwind )
689 add ip, r1, #TI_CPU_SAVE
690 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
691 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
692 THUMB( str sp, [ip], #4 )
693 THUMB( str lr, [ip], #4 )
694 ldr r4, [r2, #TI_TP_VALUE]
695 ldr r5, [r2, #TI_TP_VALUE + 4]
696 #ifdef CONFIG_CPU_USE_DOMAINS
697 ldr r6, [r2, #TI_CPU_DOMAIN]
698 #endif
699 switch_tls r1, r4, r5, r3, r7
700 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
701 ldr r7, [r2, #TI_TASK]
702 ldr r8, =__stack_chk_guard
703 ldr r7, [r7, #TSK_STACK_CANARY]
704 #endif
705 #ifdef CONFIG_CPU_USE_DOMAINS
706 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
707 #endif
708 mov r5, r0
709 add r4, r2, #TI_CPU_SAVE
710 ldr r0, =thread_notify_head
711 mov r1, #THREAD_NOTIFY_SWITCH
712 bl atomic_notifier_call_chain
713 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
714 str r7, [r8]
715 #endif
716 THUMB( mov ip, r4 )
717 mov r0, r5
718 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
719 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
720 THUMB( ldr sp, [ip], #4 )
721 THUMB( ldr pc, [ip] )
722 UNWIND(.fnend )
723 ENDPROC(__switch_to)
725 __INIT
727 /*
728 * User helpers.
729 *
730 * Each segment is 32-byte aligned and will be moved to the top of the high
731 * vector page. New segments (if ever needed) must be added in front of
732 * existing ones. This mechanism should be used only for things that are
733 * really small and justified, and not be abused freely.
734 *
735 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
736 */
737 THUMB( .arm )
739 .macro usr_ret, reg
740 #ifdef CONFIG_ARM_THUMB
741 bx \reg
742 #else
743 mov pc, \reg
744 #endif
745 .endm
747 .macro kuser_pad, sym, size
748 .if (. - \sym) & 3
749 .rept 4 - (. - \sym) & 3
750 .byte 0
751 .endr
752 .endif
753 .rept (\size - (. - \sym)) / 4
754 .word 0xe7fddef1
755 .endr
756 .endm
758 #ifdef CONFIG_KUSER_HELPERS
759 .align 5
760 .globl __kuser_helper_start
761 __kuser_helper_start:
763 /*
764 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
765 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
766 */
768 __kuser_cmpxchg64: @ 0xffff0f60
770 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
772 /*
773 * Poor you. No fast solution possible...
774 * The kernel itself must perform the operation.
775 * A special ghost syscall is used for that (see traps.c).
776 */
777 stmfd sp!, {r7, lr}
778 ldr r7, 1f @ it's 20 bits
779 swi __ARM_NR_cmpxchg64
780 ldmfd sp!, {r7, pc}
781 1: .word __ARM_NR_cmpxchg64
783 #elif defined(CONFIG_CPU_32v6K)
785 stmfd sp!, {r4, r5, r6, r7}
786 ldrd r4, r5, [r0] @ load old val
787 ldrd r6, r7, [r1] @ load new val
788 smp_dmb arm
789 1: ldrexd r0, r1, [r2] @ load current val
790 eors r3, r0, r4 @ compare with oldval (1)
791 eoreqs r3, r1, r5 @ compare with oldval (2)
792 strexdeq r3, r6, r7, [r2] @ store newval if eq
793 teqeq r3, #1 @ success?
794 beq 1b @ if no then retry
795 smp_dmb arm
796 rsbs r0, r3, #0 @ set returned val and C flag
797 ldmfd sp!, {r4, r5, r6, r7}
798 usr_ret lr
800 #elif !defined(CONFIG_SMP)
802 #ifdef CONFIG_MMU
804 /*
805 * The only thing that can break atomicity in this cmpxchg64
806 * implementation is either an IRQ or a data abort exception
807 * causing another process/thread to be scheduled in the middle of
808 * the critical sequence. The same strategy as for cmpxchg is used.
809 */
810 stmfd sp!, {r4, r5, r6, lr}
811 ldmia r0, {r4, r5} @ load old val
812 ldmia r1, {r6, lr} @ load new val
813 1: ldmia r2, {r0, r1} @ load current val
814 eors r3, r0, r4 @ compare with oldval (1)
815 eoreqs r3, r1, r5 @ compare with oldval (2)
816 2: stmeqia r2, {r6, lr} @ store newval if eq
817 rsbs r0, r3, #0 @ set return val and C flag
818 ldmfd sp!, {r4, r5, r6, pc}
820 .text
821 kuser_cmpxchg64_fixup:
822 @ Called from kuser_cmpxchg_fixup.
823 @ r4 = address of interrupted insn (must be preserved).
824 @ sp = saved regs. r7 and r8 are clobbered.
825 @ 1b = first critical insn, 2b = last critical insn.
826 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
827 mov r7, #0xffff0fff
828 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
829 subs r8, r4, r7
830 rsbcss r8, r8, #(2b - 1b)
831 strcs r7, [sp, #S_PC]
832 #if __LINUX_ARM_ARCH__ < 6
833 bcc kuser_cmpxchg32_fixup
834 #endif
835 mov pc, lr
836 .previous
838 #else
839 #warning "NPTL on non MMU needs fixing"
840 mov r0, #-1
841 adds r0, r0, #0
842 usr_ret lr
843 #endif
845 #else
846 #error "incoherent kernel configuration"
847 #endif
849 kuser_pad __kuser_cmpxchg64, 64
851 __kuser_memory_barrier: @ 0xffff0fa0
852 smp_dmb arm
853 usr_ret lr
855 kuser_pad __kuser_memory_barrier, 32
857 __kuser_cmpxchg: @ 0xffff0fc0
859 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
861 /*
862 * Poor you. No fast solution possible...
863 * The kernel itself must perform the operation.
864 * A special ghost syscall is used for that (see traps.c).
865 */
866 stmfd sp!, {r7, lr}
867 ldr r7, 1f @ it's 20 bits
868 swi __ARM_NR_cmpxchg
869 ldmfd sp!, {r7, pc}
870 1: .word __ARM_NR_cmpxchg
872 #elif __LINUX_ARM_ARCH__ < 6
874 #ifdef CONFIG_MMU
876 /*
877 * The only thing that can break atomicity in this cmpxchg
878 * implementation is either an IRQ or a data abort exception
879 * causing another process/thread to be scheduled in the middle
880 * of the critical sequence. To prevent this, code is added to
881 * the IRQ and data abort exception handlers to set the pc back
882 * to the beginning of the critical section if it is found to be
883 * within that critical section (see kuser_cmpxchg_fixup).
884 */
885 1: ldr r3, [r2] @ load current val
886 subs r3, r3, r0 @ compare with oldval
887 2: streq r1, [r2] @ store newval if eq
888 rsbs r0, r3, #0 @ set return val and C flag
889 usr_ret lr
891 .text
892 kuser_cmpxchg32_fixup:
893 @ Called from kuser_cmpxchg_check macro.
894 @ r4 = address of interrupted insn (must be preserved).
895 @ sp = saved regs. r7 and r8 are clobbered.
896 @ 1b = first critical insn, 2b = last critical insn.
897 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
898 mov r7, #0xffff0fff
899 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
900 subs r8, r4, r7
901 rsbcss r8, r8, #(2b - 1b)
902 strcs r7, [sp, #S_PC]
903 mov pc, lr
904 .previous
906 #else
907 #warning "NPTL on non MMU needs fixing"
908 mov r0, #-1
909 adds r0, r0, #0
910 usr_ret lr
911 #endif
913 #else
915 smp_dmb arm
916 1: ldrex r3, [r2]
917 subs r3, r3, r0
918 strexeq r3, r1, [r2]
919 teqeq r3, #1
920 beq 1b
921 rsbs r0, r3, #0
922 /* beware -- each __kuser slot must be 8 instructions max */
923 ALT_SMP(b __kuser_memory_barrier)
924 ALT_UP(usr_ret lr)
926 #endif
928 kuser_pad __kuser_cmpxchg, 32
930 __kuser_get_tls: @ 0xffff0fe0
931 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
932 usr_ret lr
933 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
934 kuser_pad __kuser_get_tls, 16
935 .rep 3
936 .word 0 @ 0xffff0ff0 software TLS value, then
937 .endr @ pad up to __kuser_helper_version
939 __kuser_helper_version: @ 0xffff0ffc
940 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
942 .globl __kuser_helper_end
943 __kuser_helper_end:
945 #endif
947 THUMB( .thumb )
949 /*
950 * Vector stubs.
951 *
952 * This code is copied to 0xffff1000 so we can use branches in the
953 * vectors, rather than ldr's. Note that this code must not exceed
954 * a page size.
955 *
956 * Common stub entry macro:
957 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
958 *
959 * SP points to a minimal amount of processor-private memory, the address
960 * of which is copied into r0 for the mode specific abort handler.
961 */
962 .macro vector_stub, name, mode, correction=0
963 .align 5
965 vector_\name:
966 .if \correction
967 sub lr, lr, #\correction
968 .endif
970 @
971 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
972 @ (parent CPSR)
973 @
974 stmia sp, {r0, lr} @ save r0, lr
975 mrs lr, spsr
976 str lr, [sp, #8] @ save spsr
978 @
979 @ Prepare for SVC32 mode. IRQs remain disabled.
980 @
981 mrs r0, cpsr
982 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
983 msr spsr_cxsf, r0
985 @
986 @ the branch table must immediately follow this code
987 @
988 and lr, lr, #0x0f
989 THUMB( adr r0, 1f )
990 THUMB( ldr lr, [r0, lr, lsl #2] )
991 mov r0, sp
992 ARM( ldr lr, [pc, lr, lsl #2] )
993 movs pc, lr @ branch to handler in SVC mode
994 ENDPROC(vector_\name)
996 .align 2
997 @ handler addresses follow this label
998 1:
999 .endm
1001 .section .stubs, "ax", %progbits
1002 __stubs_start:
1003 @ This must be the first word
1004 .word vector_swi
1006 vector_rst:
1007 ARM( swi SYS_ERROR0 )
1008 THUMB( svc #0 )
1009 THUMB( nop )
1010 b vector_und
1012 /*
1013 * Interrupt dispatcher
1014 */
1015 vector_stub irq, IRQ_MODE, 4
1017 .long __irq_usr @ 0 (USR_26 / USR_32)
1018 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1019 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1020 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1021 .long __irq_invalid @ 4
1022 .long __irq_invalid @ 5
1023 .long __irq_invalid @ 6
1024 .long __irq_invalid @ 7
1025 .long __irq_invalid @ 8
1026 .long __irq_invalid @ 9
1027 .long __irq_invalid @ a
1028 .long __irq_invalid @ b
1029 .long __irq_invalid @ c
1030 .long __irq_invalid @ d
1031 .long __irq_invalid @ e
1032 .long __irq_invalid @ f
1034 /*
1035 * Data abort dispatcher
1036 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1037 */
1038 vector_stub dabt, ABT_MODE, 8
1040 .long __dabt_usr @ 0 (USR_26 / USR_32)
1041 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1042 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1043 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1044 .long __dabt_invalid @ 4
1045 .long __dabt_invalid @ 5
1046 .long __dabt_invalid @ 6
1047 .long __dabt_invalid @ 7
1048 .long __dabt_invalid @ 8
1049 .long __dabt_invalid @ 9
1050 .long __dabt_invalid @ a
1051 .long __dabt_invalid @ b
1052 .long __dabt_invalid @ c
1053 .long __dabt_invalid @ d
1054 .long __dabt_invalid @ e
1055 .long __dabt_invalid @ f
1057 /*
1058 * Prefetch abort dispatcher
1059 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1060 */
1061 vector_stub pabt, ABT_MODE, 4
1063 .long __pabt_usr @ 0 (USR_26 / USR_32)
1064 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1065 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1066 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1067 .long __pabt_invalid @ 4
1068 .long __pabt_invalid @ 5
1069 .long __pabt_invalid @ 6
1070 .long __pabt_invalid @ 7
1071 .long __pabt_invalid @ 8
1072 .long __pabt_invalid @ 9
1073 .long __pabt_invalid @ a
1074 .long __pabt_invalid @ b
1075 .long __pabt_invalid @ c
1076 .long __pabt_invalid @ d
1077 .long __pabt_invalid @ e
1078 .long __pabt_invalid @ f
1080 /*
1081 * Undef instr entry dispatcher
1082 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1083 */
1084 vector_stub und, UND_MODE
1086 .long __und_usr @ 0 (USR_26 / USR_32)
1087 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1088 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1089 .long __und_svc @ 3 (SVC_26 / SVC_32)
1090 .long __und_invalid @ 4
1091 .long __und_invalid @ 5
1092 .long __und_invalid @ 6
1093 .long __und_invalid @ 7
1094 .long __und_invalid @ 8
1095 .long __und_invalid @ 9
1096 .long __und_invalid @ a
1097 .long __und_invalid @ b
1098 .long __und_invalid @ c
1099 .long __und_invalid @ d
1100 .long __und_invalid @ e
1101 .long __und_invalid @ f
1103 .align 5
1105 /*=============================================================================
1106 * Address exception handler
1107 *-----------------------------------------------------------------------------
1108 * These aren't too critical.
1109 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1110 */
1112 vector_addrexcptn:
1113 b vector_addrexcptn
1115 /*=============================================================================
1116 * Undefined FIQs
1117 *-----------------------------------------------------------------------------
1118 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1119 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1120 * Basically to switch modes, we *HAVE* to clobber one register... brain
1121 * damage alert! I don't think that we can execute any code in here in any
1122 * other mode than FIQ... Ok you can switch to another mode, but you can't
1123 * get out of that mode without clobbering one register.
1124 */
1125 vector_fiq:
1126 subs pc, lr, #4
1128 .globl vector_fiq_offset
1129 .equ vector_fiq_offset, vector_fiq
1131 .section .vectors, "ax", %progbits
1132 __vectors_start:
1133 W(b) vector_rst
1134 W(b) vector_und
1135 W(ldr) pc, __vectors_start + 0x1000
1136 W(b) vector_pabt
1137 W(b) vector_dabt
1138 W(b) vector_addrexcptn
1139 W(b) vector_irq
1140 W(b) vector_fiq
1142 .data
1144 .globl cr_alignment
1145 .globl cr_no_alignment
1146 cr_alignment:
1147 .space 4
1148 cr_no_alignment:
1149 .space 4
1151 #ifdef CONFIG_MULTI_IRQ_HANDLER
1152 .globl handle_arch_irq
1153 handle_arch_irq:
1154 .space 4
1155 #endif