2 * arch/arm/mach-at91/at91sam9263.c
4 * Copyright (C) 2007 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
15 #include <asm/proc-fns.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
20 #include <mach/at91sam9263.h>
21 #include <mach/at91_pmc.h>
24 #include "at91_rstc.h"
30 /* --------------------------------------------------------------------
32 * -------------------------------------------------------------------- */
35 * The peripheral clocks.
37 static struct clk pioA_clk
= {
39 .pmc_mask
= 1 << AT91SAM9263_ID_PIOA
,
40 .type
= CLK_TYPE_PERIPHERAL
,
42 static struct clk pioB_clk
= {
44 .pmc_mask
= 1 << AT91SAM9263_ID_PIOB
,
45 .type
= CLK_TYPE_PERIPHERAL
,
47 static struct clk pioCDE_clk
= {
49 .pmc_mask
= 1 << AT91SAM9263_ID_PIOCDE
,
50 .type
= CLK_TYPE_PERIPHERAL
,
52 static struct clk usart0_clk
= {
54 .pmc_mask
= 1 << AT91SAM9263_ID_US0
,
55 .type
= CLK_TYPE_PERIPHERAL
,
57 static struct clk usart1_clk
= {
59 .pmc_mask
= 1 << AT91SAM9263_ID_US1
,
60 .type
= CLK_TYPE_PERIPHERAL
,
62 static struct clk usart2_clk
= {
64 .pmc_mask
= 1 << AT91SAM9263_ID_US2
,
65 .type
= CLK_TYPE_PERIPHERAL
,
67 static struct clk mmc0_clk
= {
69 .pmc_mask
= 1 << AT91SAM9263_ID_MCI0
,
70 .type
= CLK_TYPE_PERIPHERAL
,
72 static struct clk mmc1_clk
= {
74 .pmc_mask
= 1 << AT91SAM9263_ID_MCI1
,
75 .type
= CLK_TYPE_PERIPHERAL
,
77 static struct clk can_clk
= {
79 .pmc_mask
= 1 << AT91SAM9263_ID_CAN
,
80 .type
= CLK_TYPE_PERIPHERAL
,
82 static struct clk twi_clk
= {
84 .pmc_mask
= 1 << AT91SAM9263_ID_TWI
,
85 .type
= CLK_TYPE_PERIPHERAL
,
87 static struct clk spi0_clk
= {
89 .pmc_mask
= 1 << AT91SAM9263_ID_SPI0
,
90 .type
= CLK_TYPE_PERIPHERAL
,
92 static struct clk spi1_clk
= {
94 .pmc_mask
= 1 << AT91SAM9263_ID_SPI1
,
95 .type
= CLK_TYPE_PERIPHERAL
,
97 static struct clk ssc0_clk
= {
99 .pmc_mask
= 1 << AT91SAM9263_ID_SSC0
,
100 .type
= CLK_TYPE_PERIPHERAL
,
102 static struct clk ssc1_clk
= {
104 .pmc_mask
= 1 << AT91SAM9263_ID_SSC1
,
105 .type
= CLK_TYPE_PERIPHERAL
,
107 static struct clk ac97_clk
= {
109 .pmc_mask
= 1 << AT91SAM9263_ID_AC97C
,
110 .type
= CLK_TYPE_PERIPHERAL
,
112 static struct clk tcb_clk
= {
114 .pmc_mask
= 1 << AT91SAM9263_ID_TCB
,
115 .type
= CLK_TYPE_PERIPHERAL
,
117 static struct clk pwm_clk
= {
119 .pmc_mask
= 1 << AT91SAM9263_ID_PWMC
,
120 .type
= CLK_TYPE_PERIPHERAL
,
122 static struct clk macb_clk
= {
124 .pmc_mask
= 1 << AT91SAM9263_ID_EMAC
,
125 .type
= CLK_TYPE_PERIPHERAL
,
127 static struct clk dma_clk
= {
129 .pmc_mask
= 1 << AT91SAM9263_ID_DMA
,
130 .type
= CLK_TYPE_PERIPHERAL
,
132 static struct clk twodge_clk
= {
134 .pmc_mask
= 1 << AT91SAM9263_ID_2DGE
,
135 .type
= CLK_TYPE_PERIPHERAL
,
137 static struct clk udc_clk
= {
139 .pmc_mask
= 1 << AT91SAM9263_ID_UDP
,
140 .type
= CLK_TYPE_PERIPHERAL
,
142 static struct clk isi_clk
= {
144 .pmc_mask
= 1 << AT91SAM9263_ID_ISI
,
145 .type
= CLK_TYPE_PERIPHERAL
,
147 static struct clk lcdc_clk
= {
149 .pmc_mask
= 1 << AT91SAM9263_ID_LCDC
,
150 .type
= CLK_TYPE_PERIPHERAL
,
152 static struct clk ohci_clk
= {
154 .pmc_mask
= 1 << AT91SAM9263_ID_UHP
,
155 .type
= CLK_TYPE_PERIPHERAL
,
158 static struct clk
*periph_clocks
[] __initdata
= {
186 static struct clk_lookup periph_clocks_lookups
[] = {
187 /* One additional fake clock for macb_hclk */
188 CLKDEV_CON_ID("hclk", &macb_clk
),
189 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk
),
190 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk
),
191 CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk
),
192 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk
),
193 CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk
),
194 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk
),
195 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk
),
196 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk
),
197 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk
),
198 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk
),
199 CLKDEV_CON_DEV_ID(NULL
, "i2c-at91sam9260.0", &twi_clk
),
200 /* fake hclk clock */
201 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk
),
202 CLKDEV_CON_ID("pioA", &pioA_clk
),
203 CLKDEV_CON_ID("pioB", &pioB_clk
),
204 CLKDEV_CON_ID("pioC", &pioCDE_clk
),
205 CLKDEV_CON_ID("pioD", &pioCDE_clk
),
206 CLKDEV_CON_ID("pioE", &pioCDE_clk
),
207 /* more usart lookup table for DT entries */
208 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck
),
209 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk
),
210 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk
),
211 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk
),
212 /* more tc lookup table for DT entries */
213 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk
),
214 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk
),
215 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk
),
216 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk
),
217 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk
),
218 CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk
),
219 CLKDEV_CON_DEV_ID(NULL
, "fff88000.i2c", &twi_clk
),
220 CLKDEV_CON_DEV_ID(NULL
, "fffff200.gpio", &pioA_clk
),
221 CLKDEV_CON_DEV_ID(NULL
, "fffff400.gpio", &pioB_clk
),
222 CLKDEV_CON_DEV_ID(NULL
, "fffff600.gpio", &pioCDE_clk
),
223 CLKDEV_CON_DEV_ID(NULL
, "fffff800.gpio", &pioCDE_clk
),
224 CLKDEV_CON_DEV_ID(NULL
, "fffffa00.gpio", &pioCDE_clk
),
227 static struct clk_lookup usart_clocks_lookups
[] = {
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck
),
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk
),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk
),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk
),
235 * The four programmable clocks.
236 * You must configure pin multiplexing to bring these signals out.
238 static struct clk pck0
= {
240 .pmc_mask
= AT91_PMC_PCK0
,
241 .type
= CLK_TYPE_PROGRAMMABLE
,
244 static struct clk pck1
= {
246 .pmc_mask
= AT91_PMC_PCK1
,
247 .type
= CLK_TYPE_PROGRAMMABLE
,
250 static struct clk pck2
= {
252 .pmc_mask
= AT91_PMC_PCK2
,
253 .type
= CLK_TYPE_PROGRAMMABLE
,
256 static struct clk pck3
= {
258 .pmc_mask
= AT91_PMC_PCK3
,
259 .type
= CLK_TYPE_PROGRAMMABLE
,
263 static void __init
at91sam9263_register_clocks(void)
267 for (i
= 0; i
< ARRAY_SIZE(periph_clocks
); i
++)
268 clk_register(periph_clocks
[i
]);
270 clkdev_add_table(periph_clocks_lookups
,
271 ARRAY_SIZE(periph_clocks_lookups
));
272 clkdev_add_table(usart_clocks_lookups
,
273 ARRAY_SIZE(usart_clocks_lookups
));
281 /* --------------------------------------------------------------------
283 * -------------------------------------------------------------------- */
285 static struct at91_gpio_bank at91sam9263_gpio
[] __initdata
= {
287 .id
= AT91SAM9263_ID_PIOA
,
288 .regbase
= AT91SAM9263_BASE_PIOA
,
290 .id
= AT91SAM9263_ID_PIOB
,
291 .regbase
= AT91SAM9263_BASE_PIOB
,
293 .id
= AT91SAM9263_ID_PIOCDE
,
294 .regbase
= AT91SAM9263_BASE_PIOC
,
296 .id
= AT91SAM9263_ID_PIOCDE
,
297 .regbase
= AT91SAM9263_BASE_PIOD
,
299 .id
= AT91SAM9263_ID_PIOCDE
,
300 .regbase
= AT91SAM9263_BASE_PIOE
,
304 /* --------------------------------------------------------------------
305 * AT91SAM9263 processor initialization
306 * -------------------------------------------------------------------- */
308 static void __init
at91sam9263_map_io(void)
310 at91_init_sram(0, AT91SAM9263_SRAM0_BASE
, AT91SAM9263_SRAM0_SIZE
);
311 at91_init_sram(1, AT91SAM9263_SRAM1_BASE
, AT91SAM9263_SRAM1_SIZE
);
314 static void __init
at91sam9263_ioremap_registers(void)
316 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC
);
317 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC
);
318 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0
, 512);
319 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1
, 512);
320 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT
);
321 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0
);
322 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1
);
323 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX
);
326 static void __init
at91sam9263_initialize(void)
328 arm_pm_idle
= at91sam9_idle
;
329 arm_pm_restart
= at91sam9_alt_restart
;
331 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0
);
332 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1
);
334 /* Register GPIO subsystem */
335 at91_gpio_init(at91sam9263_gpio
, 5);
338 /* --------------------------------------------------------------------
339 * Interrupt initialization
340 * -------------------------------------------------------------------- */
343 * The default interrupt priority levels (0 = lowest, 7 = highest).
345 static unsigned int at91sam9263_default_irq_priority
[NR_AIC_IRQS
] __initdata
= {
346 7, /* Advanced Interrupt Controller (FIQ) */
347 7, /* System Peripherals */
348 1, /* Parallel IO Controller A */
349 1, /* Parallel IO Controller B */
350 1, /* Parallel IO Controller C, D and E */
356 0, /* Multimedia Card Interface 0 */
357 0, /* Multimedia Card Interface 1 */
359 6, /* Two-Wire Interface */
360 5, /* Serial Peripheral Interface 0 */
361 5, /* Serial Peripheral Interface 1 */
362 4, /* Serial Synchronous Controller 0 */
363 4, /* Serial Synchronous Controller 1 */
364 5, /* AC97 Controller */
365 0, /* Timer Counter 0, 1 and 2 */
366 0, /* Pulse Width Modulation Controller */
369 0, /* 2D Graphic Engine */
370 2, /* USB Device Port */
371 0, /* Image Sensor Interface */
372 3, /* LDC Controller */
373 0, /* DMA Controller */
375 2, /* USB Host port */
376 0, /* Advanced Interrupt Controller (IRQ0) */
377 0, /* Advanced Interrupt Controller (IRQ1) */
380 AT91_SOC_START(at91sam9263
)
381 .map_io
= at91sam9263_map_io
,
382 .default_irq_priority
= at91sam9263_default_irq_priority
,
383 .extern_irq
= (1 << AT91SAM9263_ID_IRQ0
) | (1 << AT91SAM9263_ID_IRQ1
),
384 .ioremap_registers
= at91sam9263_ioremap_registers
,
385 .register_clocks
= at91sam9263_register_clocks
,
386 .init
= at91sam9263_initialize
,