x86/efi: Enforce CONFIG_RELOCATABLE for EFI boot stub
[linux/fpc-iii.git] / arch / arm / mach-at91 / at91sam926x_time.c
blobbb392320a0dd39d978bd5f1d3e861d2fce14b14c
1 /*
2 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
6 * Converted to ClockSource/ClockEvents by David Brownell.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/clockchips.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
21 #include <asm/mach/time.h>
23 #define AT91_PIT_MR 0x00 /* Mode Register */
24 #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
25 #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
26 #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
28 #define AT91_PIT_SR 0x04 /* Status Register */
29 #define AT91_PIT_PITS (1 << 0) /* Timer Status */
31 #define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
32 #define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
33 #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
34 #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
36 #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
37 #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
39 static u32 pit_cycle; /* write-once */
40 static u32 pit_cnt; /* access only w/system irq blocked */
41 static void __iomem *pit_base_addr __read_mostly;
43 static inline unsigned int pit_read(unsigned int reg_offset)
45 return __raw_readl(pit_base_addr + reg_offset);
48 static inline void pit_write(unsigned int reg_offset, unsigned long value)
50 __raw_writel(value, pit_base_addr + reg_offset);
54 * Clocksource: just a monotonic counter of MCK/16 cycles.
55 * We don't care whether or not PIT irqs are enabled.
57 static cycle_t read_pit_clk(struct clocksource *cs)
59 unsigned long flags;
60 u32 elapsed;
61 u32 t;
63 raw_local_irq_save(flags);
64 elapsed = pit_cnt;
65 t = pit_read(AT91_PIT_PIIR);
66 raw_local_irq_restore(flags);
68 elapsed += PIT_PICNT(t) * pit_cycle;
69 elapsed += PIT_CPIV(t);
70 return elapsed;
73 static struct clocksource pit_clk = {
74 .name = "pit",
75 .rating = 175,
76 .read = read_pit_clk,
77 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
82 * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
84 static void
85 pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
87 switch (mode) {
88 case CLOCK_EVT_MODE_PERIODIC:
89 /* update clocksource counter */
90 pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
91 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
92 | AT91_PIT_PITIEN);
93 break;
94 case CLOCK_EVT_MODE_ONESHOT:
95 BUG();
96 /* FALLTHROUGH */
97 case CLOCK_EVT_MODE_SHUTDOWN:
98 case CLOCK_EVT_MODE_UNUSED:
99 /* disable irq, leaving the clocksource active */
100 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
101 break;
102 case CLOCK_EVT_MODE_RESUME:
103 break;
107 static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
109 /* Disable timer */
110 pit_write(AT91_PIT_MR, 0);
113 static void at91sam926x_pit_reset(void)
115 /* Disable timer and irqs */
116 pit_write(AT91_PIT_MR, 0);
118 /* Clear any pending interrupts, wait for PIT to stop counting */
119 while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
120 cpu_relax();
122 /* Start PIT but don't enable IRQ */
123 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
126 static void at91sam926x_pit_resume(struct clock_event_device *cedev)
128 at91sam926x_pit_reset();
131 static struct clock_event_device pit_clkevt = {
132 .name = "pit",
133 .features = CLOCK_EVT_FEAT_PERIODIC,
134 .shift = 32,
135 .rating = 100,
136 .set_mode = pit_clkevt_mode,
137 .suspend = at91sam926x_pit_suspend,
138 .resume = at91sam926x_pit_resume,
143 * IRQ handler for the timer.
145 static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
148 * irqs should be disabled here, but as the irq is shared they are only
149 * guaranteed to be off if the timer irq is registered first.
151 WARN_ON_ONCE(!irqs_disabled());
153 /* The PIT interrupt may be disabled, and is shared */
154 if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
155 && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
156 unsigned nr_ticks;
158 /* Get number of ticks performed before irq, and ack it */
159 nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
160 do {
161 pit_cnt += pit_cycle;
162 pit_clkevt.event_handler(&pit_clkevt);
163 nr_ticks--;
164 } while (nr_ticks);
166 return IRQ_HANDLED;
169 return IRQ_NONE;
172 static struct irqaction at91sam926x_pit_irq = {
173 .name = "at91_tick",
174 .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
175 .handler = at91sam926x_pit_interrupt,
176 .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
179 #ifdef CONFIG_OF
180 static struct of_device_id pit_timer_ids[] = {
181 { .compatible = "atmel,at91sam9260-pit" },
182 { /* sentinel */ }
185 static int __init of_at91sam926x_pit_init(void)
187 struct device_node *np;
188 int ret;
190 np = of_find_matching_node(NULL, pit_timer_ids);
191 if (!np)
192 goto err;
194 pit_base_addr = of_iomap(np, 0);
195 if (!pit_base_addr)
196 goto node_err;
198 /* Get the interrupts property */
199 ret = irq_of_parse_and_map(np, 0);
200 if (!ret) {
201 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
202 goto ioremap_err;
204 at91sam926x_pit_irq.irq = ret;
206 of_node_put(np);
208 return 0;
210 ioremap_err:
211 iounmap(pit_base_addr);
212 node_err:
213 of_node_put(np);
214 err:
215 return -EINVAL;
217 #else
218 static int __init of_at91sam926x_pit_init(void)
220 return -EINVAL;
222 #endif
225 * Set up both clocksource and clockevent support.
227 void __init at91sam926x_pit_init(void)
229 unsigned long pit_rate;
230 unsigned bits;
231 int ret;
233 /* For device tree enabled device: initialize here */
234 of_at91sam926x_pit_init();
237 * Use our actual MCK to figure out how many MCK/16 ticks per
238 * 1/HZ period (instead of a compile-time constant LATCH).
240 pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
241 pit_cycle = (pit_rate + HZ/2) / HZ;
242 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
244 /* Initialize and enable the timer */
245 at91sam926x_pit_reset();
248 * Register clocksource. The high order bits of PIV are unused,
249 * so this isn't a 32-bit counter unless we get clockevent irqs.
251 bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
252 pit_clk.mask = CLOCKSOURCE_MASK(bits);
253 clocksource_register_hz(&pit_clk, pit_rate);
255 /* Set up irq handler */
256 ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
257 if (ret)
258 pr_crit("AT91: PIT: Unable to setup IRQ\n");
260 /* Set up and register clockevents */
261 pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
262 pit_clkevt.cpumask = cpumask_of(0);
263 clockevents_register_device(&pit_clkevt);
266 void __init at91sam926x_ioremap_pit(u32 addr)
268 #if defined(CONFIG_OF)
269 struct device_node *np =
270 of_find_matching_node(NULL, pit_timer_ids);
272 if (np) {
273 of_node_put(np);
274 return;
276 #endif
277 pit_base_addr = ioremap(addr, 16);
279 if (!pit_base_addr)
280 panic("Impossible to ioremap PIT\n");